Patent Application
20110169551
The present invention relates, in general, to integrated circuits and, more particularly, to temperature sensors.
Temperature sensors are used in a variety circuits including, but not limited to measuring the temperature of semiconductor chips that include circuits such as microprocessors, voltage regulators, digital-to-analog converters, digital filters, etc. Analog temperature sensors typically generate an output voltage that increases with increasing temperature, where the temperature coefficient may be about +10 millivolts per degree Celsius and a DC offset voltage may be about 500 mV, allowing negative temperature measurements down to −40 degrees Celsius. A drawback with temperature sensors having temperature coefficients and DC offset voltages in this range is that they use high minimum supply voltages which are unsuitable for portable applications such as, for example, laptop computers, cellular phones, portable digital assistants, or the like. These types of temperature sensors are also unsuitable for nonportable applications because they are inefficient and waste power.
Accordingly, it would be advantageous to have a temperature sensor and a method for sensing temperature capable of having a controlled temperature coefficient and capable of operating at low supply voltage levels. It would be of further advantage for the temperature sensor and method to be cost efficient to implement.
The present invention will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawing figures, in which like reference characters designate like elements and in which:
Current generator module 12 is comprised of a proportional to absolute temperature current generator stage 32 coupled to an output stage 34. More particularly, current generator stage 32 is comprised of P-channel field effect transistors (FETs) 40 and 42 having gate terminals commonly connected together and source terminals commonly connected together. The source terminals are coupled for receiving a source of operating potential such as, for example, VDD. It should be noted that the commonly connected gate terminals form an input terminal or node 13. The drain terminal of P-channel FET 40 is connected to an emitter terminal of a PNP bipolar transistor 44 and the drain terminal of P-channel FET 42 is connected to a terminal of an impedance 48. By way of example, impedance 48 is a resistor. The other terminal of resistor 48 is connected to the emitter terminal of PNP bipolar transistor 46. The base terminals of PNP bipolar transistors 44 and 46 are commonly connected together and to the collector terminals of PNP bipolar transistors 44 and 46. Thus, PNP bipolar transistors 44 and 46 are configured as diodes. Transistor 46 has an emitter area that is N times larger than the emitter area of transistor 44. The collector and base terminals of PNP bipolar transistors 44 and 46 are coupled for receiving a source of operating potential such as VSS. By way of example, source of operating potential VSS is at a ground potential. PNP bipolar transistors 44 and 46 and impedance 48 cooperate to form a delta base-emitter voltage (ΔVBE) generator circuit 51 having input nodes 52 and 54.
Proportional to absolute temperature generator stage 32 of current generator module 12 further includes an error amplifier 50 having an inverting input terminal connected to the drain and emitter terminals of P-channel FET 40 and PNP bipolar transistor 44, respectively, a noninverting input terminal connected to the drain terminal of P-channel FET 42 and to the terminal of resistor 48 that is connected to the drain terminal of P-channel FET 42, and an output terminal connected to the gate terminals of P-channel field effect transistors 40 and 42. The commonly connected drain terminal of P-channel FET 40, emitter terminal of PNP bipolar transistor 44, and inverting input terminal of error amplifier 50 form node 52 that may serve as output terminal 16 of current generator module 12. The noninverting input terminal of error amplifier 50 is connected to the drain terminal of P-channel FET 42 and to the terminal of resistor 48 that is connected to the drain terminal of P-channel FET 42 form node 54.
Output stage 34 includes a P-channel FET 56 having a source terminal connected to the source terminals of P-channel FETs 40 and 42, a gate terminal connected to the output terminal of error amplifier 50 and to the gate terminals of P-channel FETs 40 and 42, and a drain terminal connected to a terminal of an impedance 58 to form a node 60. By way of example, impedance 58 is a resistor. The other terminal of resistor 58 is connected to the base terminals and collector terminals of PNP bipolar transistors 44 and 46. It should be noted that FETs 40, 42, and 56 cooperate to form a current mirror 57. By way of example, FETs 40, 42, and 56 are Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).
Buffer stage 18 comprises an amplifier 62 having a noninverting input terminal 20 connected to output terminal 16 and thus to node 52 and an inverting input terminal 21 connected to its output terminal 22. Amplifier 62 may be an operational amplifier, an operational transconductance amplifier, or the like.
Amplifier stage 24 comprises an amplifier 64 having a noninverting input terminal 26 connected to output terminal 14 of current generator module 12, an inverting input terminal 27 coupled to output terminal 22 of buffer stage 18 through an impedance 68, and an output terminal 30 coupled through an impedance 70 to its inverting input terminal 27 and to a terminal of impedance 68 to form a node 72. Amplifier 64 may be an operational amplifier, an operational transconductance amplifier, or the like. By way of example, impedances 68 and 70 are resistors. It should be noted that the noninverting input terminal of amplifier 64 may serve as input terminal 26 of amplifier stage 24 and the output terminal of amplifier 64 may serve as output terminal 30 of temperature sensor 10. An output voltage that appears at the output terminal of amplifier 64 serves as the output voltage of temperature sensor 10 and thus appears at output terminal 30. The output voltage appearing at output terminal 30 is proportional to the temperature in centigrade or Celsius and has a DC offset voltage.
It should be further noted that the source and drain terminals of a FET may be referred to as current carrying electrodes, current conducting electrodes, sources, and drains and the gate terminal of a FET may be referred to as a control electrode, a control terminal, a gate terminal, or a gate. Similarly, the collector and emitter terminals of a bipolar transistor may be referred to as current carrying electrodes, current conducting electrodes, collectors, and emitters and the base terminal of a bipolar transistor may be referred to as a control electrode, a control terminal, a base terminal, or a base.
Although FETs 40, 42, and 56 are shown and described as being P-channel transistors, this is not a limitation of the present invention. Alternatively FETs 40, 42, and 56 can be N-channel FETs. Likewise, transistors 44 and 46 being shown and described as PNP bipolar transistors are not limitations of the present invention. Alternatively, transistors 44 and 46 may be NPN bipolar transistors. It should be noted that FETs and bipolar transistors refer to the types of transistors, whereas the conductivity types of FETs 40, 42, and 56 and bipolar transistors 44 and 46 refer to their majority charge carriers. Thus, an N-channel FET is a type of transistor in which electrons are the majority charge carrier and a P-channel FET is a type of transistor in which holes are the majority charge carrier. An NPN bipolar transistor is a type of transistor in which electrons are the majority charge carrier and a PNP bipolar transistor is a type of transistor in which holes are the majority charge carrier.
By way of example, P-channel FETs 40 and 42 have a normalized area of one, whereas P-channel transistor 56 has an area of M, where M is a multiplier of the areas of P-channel FETs 40 and 42. Similarly, PNP bipolar transistor 44 has a normalized area of one and PNP bipolar transistor 46 has an area of N, where N is a multiplier of the area of PNP bipolar transistor 44. In accordance with this embodiment, if the area of P-channel FETs 40 and 42 is unity, the area of P-channel FET 56 is M times one and if the area of PNP bipolar transistor 44 is unity, the area of PNP bipolar transistor 46 is N times one. It should be further understood that the types of transistors are not limitations of embodiments in accordance with the present invention, i.e., transistors 40, 42, and 56 may be N-channel FETs and transistors 44 and 46 may be NPN bipolar transistors.
Optionally, temperature sensor 10 includes a start-up circuit 74 which places current generator module 12 at a stable operating point when power is applied to temperature sensor 10.
In operation, power is applied to temperature sensor 10 and as discussed above start-up circuit 74 places current generator module 12 at a stable operating point. Start-up circuit 74 places a voltage at input terminal 13 which sets a voltage at the gates of P-channel FETs 40, 42, and 56 and causes currents I1, I2, and I3 to flow from their respective drains. Because P-channel FETs 40 and 42 have substantially the same channel length to width (L/W) ratios and the same gate to source voltages, currents I1 and I2 are substantially equal. Although P-channel FET 56 has the same gate to source voltage as P-channel FETs 40 and 42, its length to width ratio is different from those of P-channel FETs 40 and 42 by the factor “M.” Thus, the drain current I3 of P-channel FET 56 is a multiple of currents I1 and I2 by the factor “M,” i.e., I3=M*I1=M*I2. It should be noted that P-channel FETs 40, 42, and 56 have the same gate to source voltage because their gate terminals are electrically connected together and coupled for receiving the same source voltage and their source terminals are electrically connected together and coupled for receiving the same source voltage.
Currents I1 and I2 are transmitted to PNP bipolar transistors 44 and 46, respectively. Although the currents flowing to PNP bipolar transistors 44 and 46 are the same, the current densities of PNP bipolar transistors 44 and 46 are different because they have different emitter areas. For example, if the emitter area of PNP bipolar transistor 44 is normalized to one, the emitter area of PNP bipolar transistor 46 is “N,” where “N” is the ratio of the emitter area of PNP bipolar transistor 46 to the emitter area of PNP bipolar transistor 44. Because error amplifier 50 maintains the voltages at nodes 52 and 54 at substantially the same voltage level and PNP bipolar transistors 44 and 46 are configured as diodes having different emitter areas, the voltage V48 across resistor 48 is given by:
V
48
=ΔV
BE
=V
T*ln(N) Equation 1
where:
VT is the thermal voltage given by k*T/q in which k is Boltzmann's constant, q is the magnitude of electronic charge, and T is absolute temperature in degrees Kelvin; and
N is the ratio of the emitter area of PNP bipolar transistor 46 to the emitter area of PNP bipolar transistor 44.
The voltage at node 60 and hence the voltage at output terminal 14 can be determined from voltage V48 given by Equation 1 in conjunction with Equation 2:
V
60
=M*ΔV
BE*(R58/R48) Equation 2
where:
R58 is the resistance value of resistor 58; and
R48 is the resistance value of resistor 48.
Substituting Equation 1 into Equation 2 yields:
V
60
=M*V
T*ln(N)*(R58/R48) Equation 3
Voltage V60 at output terminal 14 is a voltage that is proportional to absolute temperature VPTAT. It should be noted that the value of resistor 58 can be substantially reduced when the value of M is three or greater.
The voltage at node 52 and hence the voltage at output terminal 16 when operating potential VSS is ground is given by Equation 4 as:
V
52
=V
EB44
=V
T*ln(IC44/IS44) Equation 4
where:
VEB44 is the emitter-base voltage of PNP bipolar transistor 44;
IC44 is the collector current of PNP bipolar transistor 44; and
IS44 is the emitter-base saturation current of PNP bipolar transistor 44.
Voltage V52 at output terminal 16 is a voltage that is complementary to absolute temperature VCTAT.
Emitter-base voltage VEB44, i.e., voltage V52 when operating potential VSS is at ground potential, which is a voltage that is complementary to absolute temperature, is buffered using an amplifier 62 in a unity gain configuration to inhibit additional current from flowing into or out of node 52. An output voltage VOUT62 that is complementary to absolute temperature appears at output terminal 22 and at input terminal 28 of amplifier stage 24. Assuming buffer amplifier 62 and amplifier 64 of amplifier stage 24 are ideal, the output voltage VOUT appearing at output terminal 30 is given by:
V
OUT
=V
PTAT+(VPTAT−VCTAT)*(R70/R68) Equation 5
where:
It should be noted that there is a temperature T0 at which output voltage VOUT, voltage VPTAT, and voltage VCTAT are equal at terminals 30, 14, and 16, respectively, i.e., VOUT(T0)=VPTAT(T0)=VCTAT(T0). By way of example, voltage VCTAT is 660 millivolts (mV) at 300 degrees Kelvin (° K) and the temperature coefficient of voltage VCTAT is −2 mV per degree Celsius (° C.). In this example, at temperature T0 (if T0 is less than 27° C. or 300° K) voltage VCTAT is given by Equation 6:
V
PTAT(T0)=660 mV+(2 mV/° C.)*(27° C.−T0) Equation 6
If output voltage VOUT is 500 mV at 0° C. or 273° K) and the temperature coefficient of voltage VOUT is 10 mV/° C., then at temperature T0 (if T0 is less than 27° C. or 300° K) voltage VOUT(To) is given by Equation 7:
V
OUT(T0)=500 mV+(10 mV/° C.)*T0 Equation 7
Setting voltage VPTAT(T0) equal to voltage VOUT(T0) gives a value for temperature T0 of approximately 17.8° C.
The minimum supply voltage VCC can be determined using the maximum value between voltages VPTAT and VCTAT, the magnitude of the threshold voltage (VTHP) for P-channel FETs used at the inputs of amplifiers 50, 62, and 64, and the overdrive voltage (VOVP) for the P-channel FETs used to bias the input stages of amplifiers 50, 62, and 64. The minimum supply voltage VDDMIN is given by Equation 8:
V
DDMIN=MAX{VCTAT,VPTAT}+|VTHP|+|VOVP|
V
DDMIN=0.95V+0.7V+0.15V=1.8V Equation 8
Thus, in accordance with this example the supply voltage can be as low as 1.8V.
Analyzing the slopes of the plots of voltages VOUT, VPTAT, and VPTAT in
∂VPTAT/∂T=VPTAT/T=VPTAT(300° K)/300° K.≈700 mV/300° K.≈2.34 mV/° K=2.34 mV/° C. Equation 9
Voltage VPTAT at 300° K is given by Equation 10:
V
PTAT(300° K)≈VCTAT(300° K)−2*(27° C.−T0)*(∂VCTAT/∂T)=660 mV−2*(27° C.−17.8° C.)*(−2 mV/° C.)≈700 mV. Equation 10
The ratio of resistor values for resistors 70 and 68 can be determined from Equation 11:
TC
OUT
=∂V
OUT
/∂T=(∂VPTAT/∂T)*(1+R70/R68)−(∂VCTAT/∂T)*(R70/R68)TCOUT=10 mV/° C. Equation 11
Thus, the ratio of resistance values R70/R68 equals 1.765.
The ratio can be set by trimming one or both of resistance values R70 and R68.
By now it should be appreciated that a temperature sensor and a method for sensing temperature have been provided. In accordance with embodiments, the temperature sensor generates a voltage that is proportional to absolute temperature and a voltage that is complementary to absolute temperature that are further processed to generate an output voltage that has a low temperature spread and a controlled coefficient of thermal expansion of for example +10 millivolts per degree Celsius over a temperature range of, for example, −40° C. to 125° C., and a DC offset voltage of, for example, 500 mV). The voltage that is complementary to absolute temperature is buffered through a unity gain buffer to generate a buffered voltage VOUT62 that is complementary to absolute temperature. Output voltage VOUT is generated from buffered voltage VOUT62 at input terminal 28 and the voltage VPTAT that is proportional to absolute temperature at input terminal 26. In generating output voltage VOUT, buffered voltage VOUT62 is multiplied by a gain factor that comprises a ratio of the resistance value of resistor 70, R70, to the resistance value of resistor 68, R68. It should be noted that amplifier stage 24 is referred to as a differential amplifier stage because the portion of output voltage VOUT derived from input terminal 28 has a gain factor that comprises the product of the ratio of the resistance value of resistor 70 to the resistance value of resistor 68 and negative one, i.e., −R70/R68 and the portion of output voltage VOUT derived from input terminal 26 is the sum of the ratio of the resistance value of resistor 70 to the resistance value of resistor 68 and one, i.e. 1+R70/R68.
The unity gain buffer and the differential amplifier stage may be configured using P-channel FETs for the input devices of the amplifiers. Thus, the input devices of the unity gain buffer and amplifier 64 may be P-channel FETs configured as a differential pair. Although the supply voltage that can be used with the temperature sensor in accordance with embodiments is low, using the P-channel FETs for the input devices of the unity gain buffer stage and the amplifier 64 further lowers the voltage levels for the supply voltage. The operating parameters of the temperature sensor can be further optimized by trimming resistors that may be present in the differential amplifier stage.
Although specific embodiments have been disclosed herein, it is not intended that the invention be limited to the disclosed embodiments. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. It is intended that the invention encompass all such modifications and variations as fall within the scope of the appended claims.
