Claims
- 1. A method of testing an integrated circuit comprising the steps of:
- providing model circuitry on the integrated circuit, said model circuitry having a plurality of transistors with a size ratio proportional to the minimum desired beta characteristic of the transistors on the integrated circuit, said transistors being coupled so that the current drawn by said transistors is proportional to said size ratio of said transistors;
- providing a test node coupled to a pin of said integrated circuit and to said model circuitry;
- measuring DC characteristics of said model circuitry by observing the current drawn by said transistors within said model circuitry in response to certain voltages being applied at said test node, said observations being made without enabling the other circuitry on the integrated circuit; and
- estimating the operating performance of the transistors within the integrated circuit from the observed current measurements of the model circuitry.
- 2. The method of claim 1 wherein said step of measuring DC characteristics comprises the steps of:
- applying a voltage ramp signal at said pin of said integrated circuit coupled to said test node; and
- measuring the ratio of current through said node to voltage at said node.
- 3. The method of claim 2 and further comprising the step of comparing the ratio of current to voltage to a predetermined ratio.
- 4. The method of claim 1 wherein said step of providing model circuitry further includes the step of providing a test circuit having a resistor, such that the current to voltage ratio at said node varies responsive to variations in the resistive value of said resistor relative to a predetermined nominal resistive value.
- 5. The method of claim 1 wherein said step of providing model circuitry further includes the step of providing a first transistor, such that the current to voltage ratio at said node varies responsive to variations in the gain of said transistor to a predetermined gain.
- 6. The method of claim 5 wherein said step of providing model circuitry further includes the step of providing a second transistor having a size ratio in comparison with said first transistor equal to a desired gain.
- 7. The method of claim 5 wherein said step of providing model circuitry further includes the step of providing a diode coupled such that the current drawn by the model circuitry varies responsive to the forward bias voltage of said diode.
- 8. The method of claim 5 wherein said step of observing the current drawn by said model circuitry comprises the step of applying a voltage to the test node and measuring the current through said test node.
- 9. The method of claim 8 wherein said step of applying a voltage comprises the step of applying a voltage to said package pin of the integrated circuit, said package pin connected to said test node.
- 10. The method of claim 1 wherein said step of providing model circuitry comprises the step of providing model circuitry which is enabled responsive to a signal provided on said test node.
Parent Case Info
This is a division of application Ser. No. 07/919,071, filed Jul. 23, 1992, now U.S. Pat. No. 5,196,787.
US Referenced Citations (3)
Divisions (1)
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Number |
Date |
Country |
Parent |
919071 |
Jul 1992 |
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