This invention concerns testing of semiconductor devices, particularly testing using multi-byte programming.
Semiconductor devices, including memory devices, are tested prior to their sale to determine whether the devices contain any defects. Testing may occur after wafer fabrication or after package assembly. During testing, the semiconductor device is attached to a test card (also known as a socket board or interface board) which in turn is connected to an external tester which tests the semiconductor devices.
Testing can have a major impact on the production costs of semiconductor devices. It is desirable to keep testing time as short as possible in order to keep production costs down. However, while more testing logic and testing functions may be built into a device in order to speed up testing time, these result in an overall larger die size when a smaller die size is usually preferred.
Multi-byte programming may also be used to decrease testing time. Current implementations of multi-byte programming employ external fixed time programming, since no minimum fixed time programming may be used given variation of different byte program characteristics within the die. Therefore, there is no way to determine that all the bytes were able to program correctly within a minimum fixed time.
It would be desirable to decrease testing time while not appreciably increasing the die size of a semiconductor device.
One embodiment of the invention is a method for testing a device. The method comprises: a) entering a multi-byte programming mode; b) programming a plurality of bytes, each byte programmed with identical data; and c) verifying each programmed byte one byte at a time, returning to step b) if any byte fails to verify, otherwise waiting for a next command.
In another embodiment, a semiconductor device comprises a memory array and a peripheral circuit. The peripheral circuit includes: 1) a controller configured to select a multi-byte programming mode; 2) a program data circuit configured to simultaneously program a selected plurality of bytes of the memory array with identical data when the multi-byte programming mode is selected, the program data circuit configured to be coupled to selected columns in the memory array corresponding to the selected plurality of bytes when the multi-byte programming mode is selected; and 3) a set of sense amplifier configured to verify each byte of the plurality of bytes one byte at a time, the sense amplifier configured to be coupled to selected columns in the memory array corresponding to the selected byte to be verified.
In yet another embodiment, a processor-readable medium stores instructions that, when executed by a processor, perform steps of a method. The method comprises: a) entering a multi-byte programming mode; b) programming a plurality of bytes, each byte programmed with identical data; and c) verifying each programmed byte one byte at a time, returning to step b) if any byte fails to verify, otherwise waiting for a next command.
An exemplary configuration of a testing environment is shown in
The cells in the memory array of the device under test are programmed with test data prior to a verification procedure. Programmed bytes are verified during the testing procedure. Verification includes determining whether the programming margin is acceptable. An acceptable programming margin is obtained when more electrical charge is stored in a cell's floating gate than is required to turn the cell off (i.e., logical 0) but the amount of charge stored does not overstress or otherwise damage the cell. If the programming margin is not acceptable, charge may be lost, causing the cell to become erased.
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If the programming margin is not acceptable (block 26), and if the multi-byte programming mode has been selected (block 28), the controller will generate a signal to turn on multiple columns in the memory array during a programming phase, i.e., multiple bytes will be selected for programming (block 30). The selected columns are then simultaneously programmed with the same data using a program pulse (block 32). The selected columns, corresponding to the selected bytes, are deselected following the programming pulse (block 34). If the multi-byte programming mode has not been selected (block 28), regular byte programming is performed, and the byte that failed to verify is programmed with a program pulse (block 32) and is then deselected (block 34).
Following the programming operation, the first byte in the plurality of programmed bytes is verified (block 24). If the programming margin is acceptable (block 26), and if multi-byte programming mode has been selected (block 36), the address counter increments one byte (block 38). Provided the byte previously verified was not the last byte to be verified (block 40), the verification process continues (block 24). However, if the byte previously verified was the last byte to be verified (block 40), the polling bit is reset (42), indicating that the multi-byte programming with internal verify process is finished (block 44).
In multi-byte programming mode, if the current byte fails to verify due to programming margin (block 26), all the bytes under test loop back to the multi-byte programming phase again (block 28 et seq.).
Parameters for testing may be set externally. These parameters include, but are not limited to, the number of bytes under programming, and the maximum number of attempts to program a byte. In some embodiments, the strength of programming could be increased if bytes continue to fail to verify.
Using the multi-byte programming mode discussed above, the entire memory array can be programmed and verified as fast as the internal time clock of the device under test permits. In multi-byte programming mode, 2p selected columns in each I/O circuit are programmed, where p is an integer.
Code segments for implementing the multi-byte programming method may be implemented in hardware, software, firmware or a combination thereof. The code segments may be stored and executed by either a processor associated with the device under test or a processor associated with the tester. (The term “processor” should be understood to encompass a microcontroller, controller microprocessor, processor, etc.) The program or code segments can be stored in a processor-readable medium or transmitted by a computer data signal embodied in a carrier wave over a transmission medium or communication link. The processor-readable medium may include any medium that can store or transfer information, such as instructions which, when executed by a processor, perform steps of a method. Examples of the processor-readable medium include an electronic circuit, a semiconductor memory device, a ROM, a flash memory, an erasable ROM (EROM), a floppy diskette, a CD-ROM, an optical disk, a hard disk, a fiber optic medium, a radio frequency (RF) link, etc. The computer data signal may include any signal that can propagate over a transmission medium such as electronic network channels, optical fibers, air, electromagnetic, RF links, etc. The code segments may be downloaded via computer networks such as the Internet, Intranet, etc.
In one exemplary embodiment, a hardwired controller implements multi-byte programming. In this embodiment, the code segments are translated into the internal logic. In another exemplary embodiment, a microcontroller implements multi-byte programming. In this embodiment, the code segments could be either translated into the internal logic or downloaded externally via the tester.
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The above description is illustrative and not restrictive. Variations of the invention will be apparent to those of skill in the art. The scope of the invention should therefore be determined not by reference to the above description but instead with reference to the appended claims.