This application claims the priority of Chinese Patent Application No. 202110548445.3, submitted to the Chinese Intellectual Property Office on May 19, 2021, the disclosure of which is incorporated herein in its entirety by reference.
Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular, to a test structure of an integrated circuit.
A latch-up is a parasitic effect unique to a CMOS process, which can lead to a circuit failure and even chip burnout. In a CMOS integrated circuit, a parasitic NPN transistor is electrically unstable and is susceptible to a latch-up under the influence of static electricity or related voltage transients. When a latch-up occurs, the NPN transistor is in an amplified state, an emitter is forward-biased, and a collector is reverse-biased. While a semiconductor component forms a low-impedance path between a power supply voltage and ground, a positive feedback loop enables the circuit to maintain the low-impedance path, resulting in a high current and permanent damage to the chip.
In order to ensure the reliability of the chip, it is necessary to avoid the latch-up of the integrated circuit. Therefore, in a chip development stage, it is necessary to test various parasitic NPN transistor structures that may exist in the integrated circuit and extract corresponding rule parameters to design the integrated circuit, so as to avoid the latch-up.
According to a first aspect, an embodiment of the present disclosure provides a test structure of an integrated circuit, including:
a first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region;
wherein the first N-type heavily doped region, the second N-type heavily doped region, and the first P-type heavily doped region are all located on a P-type substrate; there is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and there is a second distance between the second N-type heavily doped region and the first P-type heavily doped region; and
the test structure is configured to test electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.
According to a second aspect, an embodiment of the present disclosure provides a test structure of an integrated circuit, including:
a first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region;
wherein the first N-type heavily doped region is located in an N well, the second N-type heavily doped region and the first P-type heavily doped region are both located on a P-type substrate, and the N well is located on the P-type substrate;
there is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and there is a second distance between the second N-type heavily doped region and the first P-type heavily doped region; and
the test structure is configured to test electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.
According to a third aspect, an embodiment of the present disclosure provides a test structure of an integrated circuit, including:
a first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region;
wherein the first N-type heavily doped region is located in a deep N well, the second N-type heavily doped region and the first P-type heavily doped region are both located on a P-type substrate, the deep N well is located in an N well, and the N well is located on the P-type substrate;
there is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and there is a second distance between the second N-type heavily doped region and the first P-type heavily doped region; and
the test structure is configured to test electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.
According to a fourth aspect, an embodiment of the present disclosure provides a test structure of an integrated circuit, including:
a first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region;
wherein the second N-type heavily doped region is located in an N well, the first N-type heavily doped region and the first P-type heavily doped region are located on a P-type substrate, and the N well is located on the P-type substrate;
there is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and there is a second distance between the second N-type heavily doped region and the first P-type heavily doped region; and
the test structure is configured to test electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.
According to a fifth aspect, an embodiment of the present disclosure provides a test structure of an integrated circuit, including:
a first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region;
wherein the second N-type heavily doped region is located in a deep N well , the first N-type heavily doped region and the first P-type heavily doped region are both located on a P-type substrate, the deep N well is located in an N well, and the N well is located on the P-type substrate;
there is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and there is a second distance between the second N-type heavily doped region and the first P-type heavily doped region; and
the test structure is configured to test electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.
According to a sixth aspect, an embodiment of the present disclosure provides a test structure of an integrated circuit, including:
a first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region;
wherein the first N-type heavily doped region is located in a first N well, the second N-type heavily doped region is located in a second N well, and the first P-type heavily doped region, the first N well, and the second N well are all located on a P-type substrate;
there is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and there is a second distance between the second N-type heavily doped region and the first P-type heavily doped region; and
the test structure is configured to test electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.
According to a seventh aspect, an embodiment of the present disclosure provides a test structure of an integrated circuit, including:
a first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region;
wherein the first N-type heavily doped region is located in a first N well, the second N-type heavily doped region is located in a deep N well, the first P-type heavily doped region is located on a P-type substrate, the first N well is located on the P-type substrate, the deep N well is located in a second N well, and the second N well is located on the P-type substrate;
there is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and there is a second distance between the second N-type heavily doped region and the first P-type heavily doped region; and
the test structure is configured to test electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.
According to an eighth aspect, an embodiment of the present disclosure provides a test structure of an integrated circuit, including:
a first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region;
wherein the second N-type heavily doped region is located in a first N well, the first N-type heavily doped region is located in a deep N well, the first P-type heavily doped region is located on a P-type substrate, the first N well is located on the P-type substrate, the deep N well is located in a second N well, and the second N well is located on the P-type substrate;
there is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and there is a second distance between the second N-type heavily doped region and the first P-type heavily doped region; and
the test structure is configured to test electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.
According to a ninth aspect, an embodiment of the present disclosure provides a test structure of an integrated circuit, including:
a first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region;
wherein the first N-type heavily doped region is located in a first deep N well, the second N-type heavily doped region is located in a second deep N well, the first P-type heavily doped region is located on a P-type substrate, the first deep N well is located in a first N well, the second deep N well is located in a second N well, and the first N well and the second N well are located on the P-type substrate;
there is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and there is a second distance between the second N-type heavily doped region and the first P-type heavily doped region; and
the test structure is configured to test electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.
To describe the technical solutions in the embodiments of the present disclosure or in the prior art more clearly, the following briefly describes the accompanying drawings required for describing the embodiments or the prior art. Apparently, the accompanying drawings in the following description show some embodiments of the present disclosure, and a person of ordinary skill in the art may still derive other drawings from these accompanying drawings without creative efforts.
In order to ensure the reliability of the chip, it is necessary to avoid the latch-up of the integrated circuit. Therefore, in a chip development stage, it is necessary to test various parasitic NPN transistor structures that may exist in the integrated circuit and extract corresponding rule parameters to design the integrated circuit, so as to avoid the latch-up.
Accordingly, a test structure of an integrated circuit provided by the embodiments of the present disclosure includes a first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region; there is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and there is a second distance between the second N-type heavily doped region and the first P-type heavily doped region; electrical parameters of the integrated circuit corresponding to the test structure are tested by adjusting at least one of the first distance and the second distance. A correspondence between these electrical parameters and the first distance as well as the second distance can represent latch-up characteristics of the parasitic NPN transistor; the first distance and the second distance of the integrated circuit having the test structure can be set according to the latch-up characteristics, to avoid a latch-up in an operation process of the integrated circuit having the test structure, thereby improving the chip reliability.
Some optional implementations of the present disclosure are described below with reference to the accompanying drawings. Those skilled in the art should understand that the implementations below are merely illustrative rather than exhaustive enumerations. Based on these implementations, those skilled in the art can substitute, splice or combine certain features or certain examples, which shall still be considered as the disclosure of the present disclosure.
As shown in
It should be noted that, the electrical parameters under test may include a trigger voltage of the latch-up, a holding voltage of the latch-up, a trigger current of the latch-up, and a holding current of the latch-up. With a higher trigger voltage, the latch-up is less likely to occur; with a higher holding voltage, it is more difficult to maintain the latch-up. Assuming that a normal operating voltage is 1.1V, a trigger voltage of 1.2V corresponds to a higher risk of causing a latch-up, and a trigger voltage of 2V corresponds to a lower risk of causing a latch-up. Similarly, the same principle applies to the holding voltage. It should be noted that, the holding voltage is generally less than the trigger voltage.
The test structure of an integrated circuit includes a first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region; there is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and there is a second distance between the second N-type heavily doped region and the first P-type heavily doped region; electrical parameters of the integrated circuit corresponding to the test structure are tested by adjusting at least one of the first distance and the second distance, wherein the electrical parameters are the trigger voltage of the latch-up, the holding voltage of the latch-up, the trigger current of the latch-up, and the holding current of the latch-up as described above. A correspondence between these electrical parameters and the first distance as well as the second distance can represent latch-up characteristics of the parasitic NPN transistor; the first distance and the second distance of the integrated circuit having the test structure can be set according to the latch-up characteristics, to avoid a latch-up in an operation process of the integrated circuit having the test structure, thereby improving the chip reliability.
It should be noted that, the test structure of an integrated circuit can be tested by using a Transmission Line Pulse (TLP): a contact terminal of the TLP is connected to a pin of the test structure of an integrated circuit, to inject a current to the pin, so as to test electrical parameters of a latch-up of the test structure of an integrated circuit.
The following briefly introduces 9 test structures of an integrated circuit. As shown in
With reference to
Further, the first N-type heavily doped region 21, the second N-type heavily doped region 22, and the first P-type heavily doped region 23 form a parasitic NPN transistor; the test structure is configured to test latch-up characteristics of the parasitic NPN transistor.
Further, the P-type substrate 20 has a parasitic resistor 24, and the parasitic resistor 24 has a first terminal connected to the first P-type heavily doped region 23 and a second terminal connected to a base of the parasitic NPN transistor.
Before the test structure of an integrated circuit in this embodiment needs to be powered on and connected before being tested. As shown in
Specifically, the base of the parasitic NPN transistor is the P-type substrate 20, and a gain from the base to a collector may be dozens of times. In an equivalent circuit formed by the parasitic NPN transistor and the parasitic resistor 24, the parasitic NPN transistor has two states: a high-resistance blocking state, and a low-resistance latch-up state. When not triggered by an external interference, the parasitic NPN transistor is in the high-resistance blocking state, i.e., an initial state of the parasitic NPN transistor. In this case, a current gain is extremely small, and no latch-up occurs. When a collector current or voltage of the parasitic NPN transistor increases to a preset value abruptly, the parasitic NPN transistor may end the high-resistance blocking state and enter the low-resistance latch-up state. In this case, the parasitic NPN transistor will form a negative blocking state between the power supply voltage VDD and the ground terminal VSS. In this case, an amplified state of the parasitic NPN transistor can be continuously driven with a very small current, the emitter is forward-biased, and the collector is reverse-biased, thus generating a latch-up.
When the test structure of an integrated circuit in this embodiment is tested, and the first distance L1 and the second distance L2 have a first group of set values, a voltage applied to the power terminal VDD is gradually increased from 0V, for example, gradually increased from 0V to 2V, and a current between the power terminal VDD and the ground terminal VSS is monitored. When the current between the power terminal VDD and the ground terminal VSS increases abruptly, it is determined that a latch-up occurs. In this way, a correspondence between the first group of set values and the trigger voltage of the latch-up, the holding voltage of the latch-up, the trigger current of the latch-up, as well as the holding current of the latch-up can be obtained, that is, the latch-up characteristics of the parasitic NPN transistor are obtained. A second group of set values can be obtained by adjusting at least one of the first distance L1 and the second distance L2. Then, through the foregoing test method, a correspondence between the second group of set values and the trigger voltage of the latch-up, the holding voltage of the latch-up, the trigger current of the latch-up, as well as the holding current of the latch-up can be obtained. Similarly, a plurality of correspondences can be obtained; the first distance and the second distance of the integrated circuit having the test structure can be obtained according to the correspondences, to avoid a latch-up in an operation process of the integrated circuit having the test structure, thereby improving the chip reliability.
In the test structure of an integrated circuit provided by this embodiment, electrical parameters of the integrated circuit corresponding to the test structure are tested by adjusting at least one of the first distance and the second distance. A correspondence between these electrical parameters and the first distance as well as the second distance can represent latch-up characteristics of the parasitic NPN transistor; a design rule of the integrated circuit having the test structure can be defined according to the latch-up characteristics, to avoid a latch-up in an operation process of the integrated circuit having the test structure, thereby improving the chip reliability.
With reference to
Further, the N well 311, the second N-type heavily doped region 32, and the first P-type heavily doped region 33 form a parasitic NPN transistor, and the test structure is configured to test latch-up characteristics of the parasitic NPN transistor.
Further, the P-type substrate 30 has a parasitic resistor 34, and the parasitic resistor 34 has a first terminal connected to the first P-type heavily doped region 33 and a second terminal connected to a base of the parasitic NPN transistor.
Before the test structure of an integrated circuit in this embodiment needs to be powered on and connected before being tested. As shown in
Specifically, the base of the parasitic NPN transistor is the P-type substrate 30, and a gain from the base to a collector may be dozens of times. In an equivalent circuit formed by the parasitic NPN transistor and the parasitic resistor 34, the parasitic NPN transistor has two states: a high-resistance blocking state, and a low-resistance latch-up state. When not triggered by an external interference, the parasitic NPN transistor is in the high-resistance blocking state, i.e., an initial state of the parasitic NPN transistor. In this case, a current gain is extremely small, and no latch-up occurs. When a collector current of the parasitic NPN transistor increases to a preset value abruptly, the parasitic NPN transistor may end the high-resistance blocking state and enter the low-resistance latch-up state. In this case, the parasitic NPN transistor will form a negative blocking state between the power supply voltage VDD and the ground terminal VSS. In this case, an amplified state of the parasitic NPN transistor can be continuously driven with a very small current, the emitter is forward-biased, and the collector is reverse-biased, thus generating a latch-up.
When the test structure of an integrated circuit in this embodiment is tested, and the first distance L1 and the second distance L2 have a first group of set values, a voltage applied to the power terminal VDD is gradually increased from 0V, for example, gradually increased from 0V to 2V, and a current between the power terminal VDD and the ground terminal VSS is monitored. When the current between the power terminal VDD and the ground terminal VSS increases abruptly, it is determined that a latch-up occurs. In this way, a correspondence between the first group of set values and the trigger voltage of the latch-up, the holding voltage of the latch-up, the trigger current of the latch-up, as well as the holding current of the latch-up can be obtained, that is, the latch-up characteristics of the parasitic NPN transistor are obtained. A second group of set values can be obtained by adjusting at least one of the first distance L1 and the second distance L2. Then, through the foregoing test method, a correspondence between the second group of set values and the trigger voltage of the latch-up, the holding voltage of the latch-up, the trigger current of the latch-up, as well as the holding current of the latch-up can be obtained. Similarly, a plurality of correspondences can be obtained; the first distance and the second distance of the integrated circuit having the test structure can be obtained according to the correspondences, to avoid a latch-up in an operation process of the integrated circuit having the test structure, thereby improving the chip reliability.
In the test structure of an integrated circuit provided by this embodiment, electrical parameters of the integrated circuit corresponding to the test structure are tested by adjusting at least one of the first distance and the second distance. A correspondence between these electrical parameters and the first distance as well as the second distance can represent latch-up characteristics of the parasitic NPN transistor; a design rule of the integrated circuit having the test structure can be defined according to the latch-up characteristics, to avoid a latch-up in an operation process of the integrated circuit having the test structure, thereby improving the chip reliability.
With reference to
Further, the deep N well 411, the second N-type heavily doped region 42, and the first P-type heavily doped region 43 form a parasitic NPN transistor, and the test structure is configured to test latch-up characteristics of the parasitic NPN transistor.
Further, the P-type substrate 40 has a parasitic resistor 44, and the parasitic resistor 44 has a first terminal connected to the first P-type heavily doped region 43 and a second terminal connected to a base of the parasitic NPN transistor.
Before the test structure of an integrated circuit in this embodiment needs to be powered on and connected before being tested. As shown in
Specifically, the base of the parasitic NPN transistor is the P-type substrate 40, and a gain from the base to a collector may be dozens of times. In an equivalent circuit formed by the parasitic NPN transistor and the parasitic resistor 44, the parasitic NPN transistor has two states: a high-resistance blocking state, and a low-resistance latch-up state. When not triggered by an external interference, the parasitic NPN transistor is in the high-resistance blocking state, i.e., an initial state of the parasitic NPN transistor. In this case, a current gain is extremely small, and no latch-up occurs. When a collector current of the parasitic NPN transistor increases to a preset value abruptly, the parasitic NPN transistor may end the high-resistance blocking state and enter the low-resistance latch-up state. In this case, the parasitic NPN transistor will form a negative blocking state between the power supply voltage VDD and the ground terminal VSS. In this case, an amplified state of the parasitic NPN transistor can be continuously driven with a very small current, the emitter is forward-biased, and the collector is reverse-biased, thus generating a latch-up.
When the test structure of an integrated circuit in this embodiment is tested, and the first distance L1 and the second distance L2 have a first group of set values, a voltage applied to the power terminal VDD is gradually increased from 0V, for example, gradually increased from 0V to 2V, and a current between the power terminal VDD and the ground terminal VSS is monitored. When the current between the power terminal VDD and the ground terminal VSS increases abruptly, it is determined that a latch-up occurs. In this way, a correspondence between the first group of set values and the trigger voltage of the latch-up, the holding voltage of the latch-up, the trigger current of the latch-up, as well as the holding current of the latch-up can be obtained, that is, the latch-up characteristics of the parasitic NPN transistor are obtained. A second group of set values can be obtained by adjusting at least one of the first distance L1 and the second distance L2. Then, through the foregoing test method, a correspondence between the second group of set values and the trigger voltage of the latch-up, the holding voltage of the latch-up, the trigger current of the latch-up, as well as the holding current of the latch-up can be obtained. Similarly, a plurality of correspondences can be obtained; the first distance and the second distance of the integrated circuit having the test structure can be obtained according to the correspondences, to avoid a latch-up in an operation process of the integrated circuit having the test structure, thereby improving the chip reliability.
In the test structure of an integrated circuit provided by this embodiment, electrical parameters of the integrated circuit corresponding to the test structure are tested by adjusting at least one of the first distance and the second distance. A correspondence between these electrical parameters and the first distance as well as the second distance can represent latch-up characteristics of the parasitic NPN transistor; a design rule of the integrated circuit having the test structure can be defined according to the latch-up characteristics, to avoid a latch-up in an operation process of the integrated circuit having the test structure, thereby improving the chip reliability.
With reference to
Further, the N well 521, the first N-type heavily doped region 51, and the first P-type heavily doped region 53 form a parasitic NPN transistor, and the test structure is configured to test latch-up characteristics of the parasitic NPN transistor.
Further, the P-type substrate 50 has a parasitic resistor 54, and the parasitic resistor 54 has a first terminal connected to the first P-type heavily doped region 53 and a second terminal connected to a base of the parasitic NPN transistor.
Before the test structure of an integrated circuit in this embodiment needs to be powered on and connected before being tested. As shown in
Specifically, the base of the parasitic NPN transistor is the P-type substrate 50, and a gain from the base to a collector may be dozens of times. In an equivalent circuit formed by the parasitic NPN transistor and the parasitic resistor 54, the parasitic NPN transistor has two states: a high-resistance blocking state, and a low-resistance latch-up state. When not triggered by an external interference, the parasitic NPN transistor is in the high-resistance blocking state, i.e., an initial state of the parasitic NPN transistor. In this case, a current gain is extremely small, and no latch-up occurs. When a collector current of the parasitic NPN transistor increases to a preset value abruptly, the parasitic NPN transistor may end the high-resistance blocking state and enter the low-resistance latch-up state. In this case, the parasitic NPN transistor will form a negative blocking state between the power supply voltage VDD and the ground terminal VSS. In this case, an amplified state of the parasitic NPN transistor can be continuously driven with a very small current, the emitter is forward-biased, and the collector is reverse-biased, thus generating a latch-up.
When the test structure of an integrated circuit in this embodiment is tested, and the first distance L1 and the second distance L2 have a first group of set values, a voltage applied to the power terminal VDD is gradually increased from 0V, for example, gradually increased from 0V to 2V, and a current between the power terminal VDD and the ground terminal VSS is monitored. When the current between the power terminal VDD and the ground terminal VSS increases abruptly, it is determined that a latch-up occurs. In this way, a correspondence between the first group of set values and the trigger voltage of the latch-up, the holding voltage of the latch-up, the trigger current of the latch-up, as well as the holding current of the latch-up can be obtained, that is, the latch-up characteristics of the parasitic NPN transistor are obtained. A second group of set values can be obtained by adjusting at least one of the first distance L1 and the second distance L2. Then, through the foregoing test method, a correspondence between the second group of set values and the trigger voltage of the latch-up, the holding voltage of the latch-up, the trigger current of the latch-up, as well as the holding current of the latch-up can be obtained. Similarly, a plurality of correspondences can be obtained; the first distance and the second distance of the integrated circuit having the test structure can be obtained according to the correspondences, to avoid a latch-up in an operation process of the integrated circuit having the test structure, thereby improving the chip reliability.
In the test structure of an integrated circuit provided by this embodiment, electrical parameters of the integrated circuit corresponding to the test structure are tested by adjusting at least one of the first distance and the second distance. A correspondence between these electrical parameters and the first distance as well as the second distance can represent latch-up characteristics of the parasitic NPN transistor; a design rule of the integrated circuit having the test structure can be defined according to the latch-up characteristics, to avoid a latch-up in an operation process of the integrated circuit having the test structure, thereby improving the chip reliability.
With reference to
Further, the deep N well 621, the first N-type heavily doped region 61, and the first P-type heavily doped region 63 form a parasitic NPN transistor; the test structure is configured to test latch-up characteristics of the parasitic NPN transistor.
Further, the P-type substrate 60 has a parasitic resistor 64, and the parasitic resistor 64 has a first terminal connected to the first P-type heavily doped region 63 and a second terminal connected to a base of the parasitic NPN transistor.
Before the test structure of an integrated circuit in this embodiment needs to be powered on and connected before being tested. As shown in
Specifically, the base of the parasitic NPN transistor is the P-type substrate 60, and a gain from the base to a collector may be dozens of times. In an equivalent circuit formed by the parasitic NPN transistor and the parasitic resistor 64, the parasitic NPN transistor has two states: a high-resistance blocking state, and a low-resistance latch-up state. When not triggered by an external interference, the parasitic NPN transistor is in the high-resistance blocking state, i.e., an initial state of the parasitic NPN transistor. In this case, a current gain is extremely small, and no latch-up occurs. When a collector current of the parasitic NPN transistor increases to a preset value abruptly, the parasitic NPN transistor may end the high-resistance blocking state and enter the low-resistance latch-up state. In this case, the parasitic NPN transistor will form a negative blocking state between the power supply voltage VDD and the ground terminal VSS. In this case, an amplified state of the parasitic NPN transistor can be continuously driven with a very small current, the emitter is forward-biased, and the collector is reverse-biased, thus generating a latch-up.
When the test structure of an integrated circuit in this embodiment is tested, and the first distance L1 and the second distance L2 have a first group of set values, a voltage applied to the power terminal VDD is gradually increased from 0V, for example, gradually increased from 0V to 2V, and a current between the power terminal VDD and the ground terminal VSS is monitored. When the current between the power terminal VDD and the ground terminal VSS increases abruptly, it is determined that a latch-up occurs. In this way, a correspondence between the first group of set values and the trigger voltage of the latch-up, the holding voltage of the latch-up, the trigger current of the latch-up, as well as the holding current of the latch-up can be obtained, that is, the latch-up characteristics of the parasitic NPN transistor are obtained. A second group of set values can be obtained by adjusting at least one of the first distance L1 and the second distance L2. Then, through the foregoing test method, a correspondence between the second group of set values and the trigger voltage of the latch-up, the holding voltage of the latch-up, the trigger current of the latch-up, as well as the holding current of the latch-up can be obtained. Similarly, a plurality of correspondences can be obtained; the first distance and the second distance of the integrated circuit having the test structure can be obtained according to the correspondences, to avoid a latch-up in an operation process of the integrated circuit having the test structure, thereby improving the chip reliability.
In the test structure of an integrated circuit provided by this embodiment, electrical parameters of the integrated circuit corresponding to the test structure are tested by adjusting at least one of the first distance and the second distance. A correspondence between these electrical parameters and the first distance as well as the second distance can represent latch-up characteristics of the parasitic NPN transistor; a design rule of the integrated circuit having the test structure can be defined according to the latch-up characteristics, to avoid a latch-up in an operation process of the integrated circuit having the test structure, thereby improving the chip reliability.
With reference to
Further, the first N well 711, the second N well 721, and the first P-type heavily doped region 73 form a parasitic NPN transistor; the test structure is configured to test latch-up characteristics of the parasitic NPN transistor.
Further, the P-type substrate 70 has a parasitic resistor 74, and the parasitic resistor 74 has a first terminal connected to the first P-type heavily doped region 73, and a second terminal connected to a base of the parasitic NPN transistor.
Before the test structure of an integrated circuit in this embodiment needs to be powered on and connected before being tested. As shown in
Specifically, the base of the parasitic NPN transistor is the P-type substrate 70, and a gain from the base to a collector may be dozens of times. In an equivalent circuit formed by the parasitic NPN transistor and the parasitic resistor 74, the parasitic NPN transistor has two states: a high-resistance blocking state, and a low-resistance latch-up state. When not triggered by an external interference, the parasitic NPN transistor is in the high-resistance blocking state, i.e., an initial state of the parasitic NPN transistor. In this case, a current gain is extremely small, and no latch-up occurs. When a collector current of the parasitic NPN transistor increases to a preset value abruptly, the parasitic NPN transistor may end the high-resistance blocking state and enter the low-resistance latch-up state. In this case, the parasitic NPN transistor will form a negative blocking state between the power supply voltage VDD and the ground terminal VSS. In this case, an amplified state of the parasitic NPN transistor can be continuously driven with a very small current, the emitter is forward-biased, and the collector is reverse-biased, thus generating a latch-up.
When the test structure of an integrated circuit in this embodiment is tested, and the first distance L1 and the second distance L2 have a first group of set values, a voltage applied to the power terminal VDD is gradually increased from 0V, for example, gradually increased from 0V to 2V, and a current between the power terminal VDD and the ground terminal VSS is monitored. When the current between the power terminal VDD and the ground terminal VSS increases abruptly, it is determined that a latch-up occurs. In this way, a correspondence between the first group of set values and the trigger voltage of the latch-up, the holding voltage of the latch-up, the trigger current of the latch-up, as well as the holding current of the latch-up can be obtained, that is, the latch-up characteristics of the parasitic NPN transistor are obtained. A second group of set values can be obtained by adjusting at least one of the first distance L1 and the second distance L2. Then, through the foregoing test method, a correspondence between the second group of set values and the trigger voltage of the latch-up, the holding voltage of the latch-up, the trigger current of the latch-up, as well as the holding current of the latch-up can be obtained. Similarly, a plurality of correspondences can be obtained; the first distance and the second distance of the integrated circuit having the test structure can be obtained according to the correspondences, to avoid a latch-up in an operation process of the integrated circuit having the test structure, thereby improving the chip reliability.
In the test structure of an integrated circuit provided by this embodiment, electrical parameters of the integrated circuit corresponding to the test structure are tested by adjusting at least one of the first distance and the second distance. A correspondence between these electrical parameters and the first distance as well as the second distance can represent latch-up characteristics of the parasitic NPN transistor; a design rule of the integrated circuit having the test structure can be defined according to the latch-up characteristics, to avoid a latch-up in an operation process of the integrated circuit having the test structure, thereby improving the chip reliability.
With reference to
Further, the first N well 811, the deep N well 821, and the first P-type heavily doped region 83 form a parasitic NPN transistor; the test structure is configured to test latch-up characteristics of the parasitic NPN transistor.
Further, the P-type substrate 80 has a parasitic resistor 84, and the parasitic resistor 84 has a first terminal connected to the first P-type heavily doped region 83 and a second terminal connected to a base of the parasitic NPN transistor.
Before the test structure of an integrated circuit in this embodiment needs to be powered on and connected before being tested. As shown in
Specifically, the base of the parasitic NPN transistor is the P-type substrate 80, and a gain from the base to a collector may be dozens of times. In an equivalent circuit formed by the parasitic NPN transistor and the parasitic resistor 84, the parasitic NPN transistor has two states: a high-resistance blocking state, and a low-resistance latch-up state. When not triggered by an external interference, the parasitic NPN transistor is in the high-resistance blocking state, i.e., an initial state of the parasitic NPN transistor. In this case, a current gain is extremely small, and no latch-up occurs. When a collector current of the parasitic NPN transistor increases to a preset value abruptly, the parasitic NPN transistor may end the high-resistance blocking state and enter the low-resistance latch-up state. In this case, the parasitic NPN transistor will form a negative blocking state between the power supply voltage VDD and the ground terminal VSS. In this case, an amplified state of the parasitic NPN transistor can be continuously driven with a very small current, the emitter is forward-biased, and the collector is reverse-biased, thus generating a latch-up.
When the test structure of an integrated circuit in this embodiment is tested, and the first distance L1 and the second distance L2 have a first group of set values, a voltage applied to the power terminal VDD is gradually increased from 0V, for example, gradually increased from 0V to 2V, and a current between the power terminal VDD and the ground terminal VSS is monitored. When the current between the power terminal VDD and the ground terminal VSS increases abruptly, it is determined that a latch-up occurs. In this way, a correspondence between the first group of set values and the trigger voltage of the latch-up, the holding voltage of the latch-up, the trigger current of the latch-up, as well as the holding current of the latch-up can be obtained, that is, the latch-up characteristics of the parasitic NPN transistor are obtained. A second group of set values can be obtained by adjusting at least one of the first distance L1 and the second distance L2. Then, through the foregoing test method, a correspondence between the second group of set values and the trigger voltage of the latch-up, the holding voltage of the latch-up, the trigger current of the latch-up, as well as the holding current of the latch-up can be obtained. Similarly, a plurality of correspondences can be obtained; the first distance and the second distance of the integrated circuit having the test structure can be obtained according to the correspondences, to avoid a latch-up in an operation process of the integrated circuit having the test structure, thereby improving the chip reliability.
In the test structure of an integrated circuit provided by this embodiment, electrical parameters of the integrated circuit corresponding to the test structure are tested by adjusting at least one of the first distance and the second distance. A correspondence between these electrical parameters and the first distance as well as the second distance can represent latch-up characteristics of the parasitic NPN transistor; a design rule of the integrated circuit having the test structure can be defined according to the latch-up characteristics, to avoid a latch-up in an operation process of the integrated circuit having the test structure, thereby improving the chip reliability.
With reference to
Further, the first N well 921, the deep N well 911, and the first P-type heavily doped region 93 form a parasitic NPN transistor; the test structure is configured to test latch-up characteristics of the parasitic NPN transistor.
Further, the P-type substrate 90 has a parasitic resistor 94, and the parasitic resistor 94 has a first terminal connected to the first P-type heavily doped region 93 and a second terminal connected to a base of the parasitic NPN transistor.
Before the test structure of an integrated circuit in this embodiment needs to be powered on and connected before being tested. As shown in
Specifically, the base of the parasitic NPN transistor is the P-type substrate 90, and a gain from the base to a collector may be dozens of times. In an equivalent circuit formed by the parasitic NPN transistor and the parasitic resistor 94, the parasitic NPN transistor has two states: a high-resistance blocking state, and a low-resistance latch-up state. When not triggered by an external interference, the parasitic NPN transistor is in the high-resistance blocking state, i.e., an initial state of the parasitic NPN transistor. In this case, a current gain is extremely small, and no latch-up occurs. When a collector current of the parasitic NPN transistor increases to a preset value abruptly, the parasitic NPN transistor may end the high-resistance blocking state and enter the low-resistance latch-up state. In this case, the parasitic NPN transistor will form a negative blocking state between the power supply voltage VDD and the ground terminal VSS. In this case, an amplified state of the parasitic NPN transistor can be continuously driven with a very small current, the emitter is forward-biased, and the collector is reverse-biased, thus generating a latch-up.
When the test structure of an integrated circuit in this embodiment is tested, and the first distance L1 and the second distance L2 have a first group of set values, a voltage applied to the power terminal VDD is gradually increased from 0V, for example, gradually increased from 0V to 2V, and a current between the power terminal VDD and the ground terminal VSS is monitored. When the current between the power terminal VDD and the ground terminal VSS increases abruptly, it is determined that a latch-up occurs. In this way, a correspondence between the first group of set values and the trigger voltage of the latch-up, the holding voltage of the latch-up, the trigger current of the latch-up, as well as the holding current of the latch-up can be obtained, that is, the latch-up characteristics of the parasitic NPN transistor are obtained. A second group of set values can be obtained by adjusting at least one of the first distance L1 and the second distance L2. Then, through the foregoing test method, a correspondence between the second group of set values and the trigger voltage of the latch-up, the holding voltage of the latch-up, the trigger current of the latch-up, as well as the holding current of the latch-up can be obtained. Similarly, a plurality of correspondences can be obtained; the first distance and the second distance of the integrated circuit having the test structure can be obtained according to the correspondences, to avoid a latch-up in an operation process of the integrated circuit having the test structure, thereby improving the chip reliability.
In the test structure of an integrated circuit provided by this embodiment, electrical parameters of the integrated circuit corresponding to the test structure are tested by adjusting at least one of the first distance and the second distance. A correspondence between these electrical parameters and the first distance as well as the second distance can represent latch-up characteristics of the parasitic NPN transistor; a design rule of the integrated circuit having the test structure can be defined according to the latch-up characteristics, to avoid a latch-up in an operation process of the integrated circuit having the test structure, thereby improving the chip reliability.
With reference to
Further, the first deep N well 1011, the second deep N well 1021, and the first P-type heavily doped region 103 form a parasitic NPN transistor; the test structure is configured to test latch-up characteristics of the parasitic NPN transistor.
Further, the P-type substrate 100 has a parasitic resistor 104, and the parasitic resistor 104 has a first terminal connected to the first P-type heavily doped region 103 and a second terminal connected to a base of the parasitic NPN transistor.
Before the test structure of an integrated circuit in this embodiment needs to be powered on and connected before being tested. As shown in
Specifically, the base of the parasitic NPN transistor is the P-type substrate 100, and a gain from the base to a collector may be dozens of times. In an equivalent circuit formed by the parasitic NPN transistor and the parasitic resistor 104, the parasitic NPN transistor has two states: a high-resistance blocking state, and a low-resistance latch-up state. When not triggered by an external interference, the parasitic NPN transistor is in the high-resistance blocking state, i.e., an initial state of the parasitic NPN transistor. In this case, a current gain is extremely small, and no latch-up occurs. When a collector current of the parasitic NPN transistor increases to a preset value abruptly, the parasitic NPN transistor may end the high-resistance blocking state and enter the low-resistance latch-up state. In this case, the parasitic NPN transistor will form a negative blocking state between the power supply voltage VDD and the ground terminal VSS. In this case, an amplified state of the parasitic NPN transistor can be continuously driven with a very small current, the emitter is forward-biased, and the collector is reverse-biased, thus generating a latch-up.
When the test structure of an integrated circuit in this embodiment is tested, and the first distance L1 and the second distance L2 have a first group of set values, a voltage applied to the power terminal VDD is gradually increased from 0V, for example, gradually increased from 0V to 2V, and a current between the power terminal VDD and the ground terminal VSS is monitored. When the current between the power terminal VDD and the ground terminal VSS increases abruptly, it is determined that a latch-up occurs. In this way, a correspondence between the first group of set values and the trigger voltage of the latch-up, the holding voltage of the latch-up, the trigger current of the latch-up, as well as the holding current of the latch-up can be obtained, that is, the latch-up characteristics of the parasitic NPN transistor are obtained. A second group of set values can be obtained by adjusting at least one of the first distance L1 and the second distance L2. Then, through the foregoing test method, a correspondence between the second group of set values and the trigger voltage of the latch-up, the holding voltage of the latch-up, the trigger current of the latch-up, as well as the holding current of the latch-up can be obtained. Similarly, a plurality of correspondences can be obtained; the first distance and the second distance of the integrated circuit having the test structure can be obtained according to the correspondences, to avoid a latch-up in an operation process of the integrated circuit having the test structure, thereby improving the chip reliability.
In the test structure of an integrated circuit provided by this embodiment, electrical parameters of the integrated circuit corresponding to the test structure are tested by adjusting at least one of the first distance and the second distance. A correspondence between these electrical parameters and the first distance as well as the second distance can represent latch-up characteristics of the parasitic NPN transistor; a design rule of the integrated circuit having the test structure can be defined according to the latch-up characteristics, to avoid a latch-up in an operation process of the integrated circuit having the test structure, thereby improving the chip reliability.
A person skilled in the art can clearly understand that, for convenience and brevity of description, the division of the foregoing functional modules is merely an example for description. In practical application, the functions may be assigned to and completed by different functional modules as required. That is, the internal structure of the apparatus is divided into different functional modules, to complete all or some of the functions described above. Reference may be made to the corresponding process in the foregoing method embodiments for the specific working process of the foregoing apparatus. Details are not described herein again.
Finally, it should be noted that the foregoing embodiments are used only to explain the technical solutions of the present disclosure, but are not intended to limit the present disclosure. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions on some or all technical features therein. The modifications or substitutions do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.
Number | Date | Country | Kind |
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202110548445.3 | May 2021 | CN | national |