Patent Application
20050012514
1. Field of the Invention
This invention relates to test systems and, more particularly, to boards having feed-through contacts for conveying signals of a device under test.
2. Description of the Related Art
Output signals from a device under test may be analyzed in a variety of ways. One way is to use a test circuit board or patch board. The output signals which are to be analyzed may be routed or coupled to the test board and then further routed to an analyzer port for connection to an analyzer. In some test systems, a test circuit board may be connected directly to the device under test using cables, connectors and sockets. In other test systems, the device under test may be mounted to a standard system board and the test circuit board may be coupled to the system board using cables, connectors or other means.
Depending on the frequencies of the output signals, the loading placed on the output signals by the analyzer and by the wiring and traces of the test circuit board may be sufficient to distort the output signals. This distortion may cause incorrect measurements and may possibly even preclude normal system operation. Accordingly, when probing any signal it may be advantageous to keep the lead lengths of any probe wires as short as possible to reduce the amount of load that the probe adds to the output signal. In addition, it may be desirable to isolate the probe or test elements from the output drive of the device under test.
Various embodiments of a test system including an apparatus for conveying signals between a first circuit board and a second circuit board. In one embodiment, the apparatus includes a dielectric substrate having a first side forming a first surface and a second side forming a second surface. The apparatus also includes a plurality of contact pins each configured to convey electrical signals. Each of the contact pins may extend through the dielectric substrate and may protrude beyond the first surface and the second surface. In addition, one or more of the contact pins may be formed using a pliable resistive material.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.
Turning now to
In one embodiment, DUT 20 may be a high performance processor, for example. During operation, DUT 20 may output signals on a variety of contacts. As described in greater detail below, in one embodiment, to capture and analyze the output signals on analyzer 50 the signals may be routed to analyzer 50 through an interposer 60 and test board (not shown in
Depending on the frequency of the signal produced at output signal contact 21 of DUT 20, the load created by signal path 45 and analyzer 40 may cause distortion of the output signal. Accordingly, lead lengths and associated test wiring should be minimized. In addition, series resistor R1 may provide some signal isolation from analyzer 50, thereby minimizing loading effects of the test circuit board and analyzer 50. As will be described in greater detail below in conjunction with the description of
Referring to
Backing plate 180 may be used to provide a compressive force for “sandwiching” test board 170, interposer 160, system board 150, DUT 20 and heat sink 120 together. In the illustrated embodiment, thumb-screws or other suitable fasteners may be used to fasten backing plate 180 to heat sink 120. This arrangement may compress each contact on DUT 20, interposer 160 and test chip 40 to their respective contact pads on their respective circuit boards.
In the illustrated embodiment, DUT 20 uses a ball grid array (BGA) for its contact pinout. The BGA forms a given footprint pattern. The footprint pattern of DUT 20 is mated to a footprint pattern 155 on system board 150. Footprint pattern 155 is provided on both the top and bottom surface of system board 150. To keep lead lengths as short as possible, the footprint pattern on each board surface is symmetrically matching and also positioned opposite each other. Accordingly, a footprint pattern on the bottom surface of interposer 160 mates to footprint pattern 155 on the top surface of system board 150. In addition, a footprint pattern on the top surface of interposer 160 mates to a footprint pattern on the bottom surface of test board 170, and so forth. It is noted that although a BGA footprint pattern is used in the illustrated embodiment, other embodiments are contemplated in which other footprint patterns may be used.
In one embodiment, system board 150 may be any circuit board which is used in the normal operation of DUT 20. For example, if DUT 20 is a processor, system board 150 may be a processor motherboard. However, in other embodiments, system board 150 may be special circuit board designed to emulate a typical system environment as seen from DUT 20.
In the illustrated embodiment, test board 170 is a circuit board which provides signal paths for conveying output signals from DUT 20 to analyzer connector 190 for use by the analyzer (not shown in
In the illustrated embodiment, interposer 160 may provide a means for conveying signals from system board 150 to test board 170 while allowing clearance of other components on system board 150. In other words, interposer 160 may be a spacer which also conveys signals. In one embodiment, interposer 160 includes a plurality of contact pins 165 for conveying the signals. As described above, one or more of the contact pins may provide a series resistance, such as resistance R1 of
It is noted that many conventional contact pin polymers used to convey signals are made using highly conductive materials (e.g., a silver-based polymer) having very low or even negligible resistance values.
Turning to
In one embodiment, dielectric substrate 310 may be implemented using materials such as FR4, for example, which is commonly used to manufacture circuit board substrates. In addition, through-holes 320 may be bored completely through dielectric substrate 310. Contact pins 165 may be positioned to extend through the through-holes and to protrude above the top and bottom surfaces of dielectric substrate 310. As described above, contact pins 165 may be arranged across the surface of dielectric substrate 310 in a footprint pattern that matches a footprint pattern of another board such as footprint pattern 155 of
In addition contact pins 165 may be implemented using pliable resistive material that may provide a compression connection when mated between system board 150 and test board 170.
To minimize the loading effects of analyzer 50 of
In one embodiment, the resistance value of the resistive material may have the same order of magnitude as the characteristic impedance value of the signal traces and drives associated with the conveyance of the signal. Thus, in one embodiment, the resistive material may provide a resistance value greater than 5 ohms. For example, in one specific implementation, a resistance value of 20 ohms may be appropriate depending on the frequency of the signal, the signal trace characteristics and the impedance of the output driver of DUT 20. This is in contrast to conventional conductive polymers which strive to keep the resistance value as small as practicable. It is noted that generally speaking, the resistive value should not be large enough to prevent propagation of the signals through interposer 160.
Referring to
As described above, contact pin 165 may be implemented using a resistive material such as a resistive polymer, for example, having a controllable and predetermined resistance which may provide a series resistance R1 to a signal propagated through contact pin 165.
Although the embodiments above have been described in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.
