Patent Application
20100213968
The present invention relates to the testing of integrated circuits at the manufacture stage and in particular to a test insert provided for this purpose.
In modern semiconductor processes a plurality of integrated circuits are formed simultaneously on a single wafer. Each integrated circuit may contain millions of circuit elements manufactured with many masks and layers. Correspondingly, each integrated circuit may comprise millions of connections or contacts between the various layers. In recent years there has been an increase in the number of active elements in a typical integrated circuit. This has lead to a corresponding increase in the number of interconnections, or contacts, between the various layers that go to make up the integrated circuit.
In normal practise, on each semiconductor wafer in addition to the integrated circuits, one or more test inserts are formed. The test inserts are formed in place of an integrated circuit for use as process control and quality monitoring aids. The test inserts contain a number of representative circuit and interconnect elements connected to one or more access contacts to allow their individual and collective performance to be measured or determined. Since each such test insert occupies a potential integrated circuit location they reduce the number of integrated circuits that can be formed on a single wafer. This inefficiency has the effect of increasing the unit cost per integrated circuit.
As an alternative, in some processes a small test insert array comprising only a few transistors is provided for each individual integrated circuit. Use of a small test insert array using only transistors is not always a reliable test of the wafer process integrity, particularly if a number of more complex components are provided in the integrated circuits. Accordingly this can be seen as a waste of space and an unnecessary expense.
It is therefore desirable to provide a test insert that at least partly overcomes or alleviates the above problems.
According to a first aspect, there is provided a test insert for an integrated circuit of the type formed on a wafer and having one or more interconnected layers, the test insert comprising: a plurality of interlayer contacts providing a plurality of conducting paths between the layers of the integrated circuit; one or more access contacts for providing connections between the plurality of connecting paths and external circuitry so as to allow one or more signals to be conducted through one or more of the conducting paths to provide an indication of the quality of the manufacturing process, the interlayer contacts and the access contacts both being provided at or within the boundary area of the integrated circuit.
Such a test insert is suitable to enable the quality of interlayer contacts to be determined at each integrated circuit within a wafer. This enables statistical information relating to the likely quality and reliability of circuit elements to be gathered across all sites on a wafer, thus improving quality control and reliability.
According to a second aspect, there is provided a method of testing an integrated circuit in accordance with the first aspect of the present invention, the method comprising the steps of: connecting one or more items of external circuitry to the access contacts; applying electrical signals to the access contacts; monitoring the signal generated in response and thereby determining the likely quality and reliability of circuit elements in the integrated circuit.
The method of the second aspect, may incorporate any or all features of the test insert of the first aspect as desired or as appropriate.
According to a third aspect, there is provided a method of manufacturing an integrated circuit, the method comprising the steps of: providing a semiconductor wafer; forming an array of integrated circuits on said wafer; forming a test insert according to the first aspect at or within the boundary area of each integrated circuit; and testing each integrated circuit in accordance with the method of the second aspect.
The method of the third aspect may incorporate any or all features of the test insert of the first aspect or the method of the second aspect as desired or as appropriate.
According to a fourth aspect there is provided an integrated circuit incorporating a test insert according to the first aspect, tested according to the second aspect or manufactured according to the third aspect.
The integrated circuit of the fourth aspect may incorporate any or all features of the test insert of the first aspect or the methods of the second or third aspects as desired or as appropriate.
The interlayer contacts may be vias. Preferably the numbers of interlayer contacts of each type in the test insert are in proportion to the numbers of interlayer contacts of each type in the integrated circuit itself.
Preferably interlayer contacts of each type are connected in series to form short electrical paths. An access contact may be provided at each end of the short electrical path. There may be more than one such short electrical path. One or more such short electrical paths may be connected in series to form one or more longer electrical paths. In such cases, the access contacts at each end of the short electrical paths may enable intermediate measurements to be taken.
The access contacts and/or the interlayer contacts may be arranged to present a visual pattern upon the surface of the wafer. Preferably, the layout may be adapted such that the presented visual pattern is distinctive or unique for a particular integrated circuit or for a particular type of integrated circuit. Preferably, the presented visual pattern is adapted to resemble or represent one or more alphanumeric characters. The alphanumeric characters may be related to the integrated circuit part or identity number.
In a further embodiment, additional circuitry is also provided. The additional circuitry may be connected to said electrical paths directly or indirectly. Direct connections may be achieved via said access contacts. The additional circuitry may be arranged to generate electrical signals indicative of the conduction performance of said interface contacts in said electrical paths. The additional circuitry may comprise a plurality of transistor-resistor pairs, each transistor-resistor pair connected to a different point within an electrical path. This can provide an indication of where an electrical path a fault is located.
In order that the invention is more clearly understood one embodiment will now be described further below, by way of example only and with reference to the accompanying drawings, in which:
Turning now to
The electrical path 110 is comprised of a plurality of tracks 111, each track provided at a single layer of the integrated circuit and connected to the other tracks 111 by interconnecting vias 102. The vias 102 provide interlayer contacts and thus allow the tracks 111 to be connected into a single electrical track 110.
The number of tracks 111 in particular layers and the number of vias 102 in the path 110 is ideally in proportion to the numbers of such within the integrated circuit. This is so that testing the interface 100 should provide useful information in relation to the likely reliability of elements within the integrated circuit.
In the example shown, access contact 104 is connected to ground and contact 101 is connected to a reference voltage. Connected to various points in the electrical path 110 are transistor-resistor pairs 123, 124, 125. The transistor-resistor pairs 123, 124, 125 are in connected between earth and access contact 103. If the electrical path is intact at the track 111 connected to a transistor-resistor pair 123, 124, 125, a current can flow between contact 103 and the respective earth of the transistor-resistor pair 123, 124, 125. By analysing the current drawn from contact 103 it can be deduced whether the path 110 is operational as a whole and, if not, how far along the path 110 a fault lies. This can therefore isolate a particular interconnection between layers or a particular layer as being faulty.
In an alternative arrangement, 101 and 104 could be connected to the internal reference voltage and ground pins of the integrated circuit.
In practice, such a test insert 100 will be provided for each integrated circuit formed on a wafer (not shown). If a threshold number of the test inserts 100 show the same fault, the whole wafer may be determined to be faulty at an early stage of processing, thereby saving costs in separation and additional processing of potentially faulty individual integrated circuits.
Turning now to
Turning now to
In the present case, between Pin and TestOut1 there is a path comprising a plurality of connections Rca along and between metal layer 1 and the silicided poly and n+ active layers; between TestOut1 and TestOut2 is a path comprising a plurality of connections Rva, Rvb along and between metal layers 1-3; and between TestOut2 and ground is a path comprising a plurality of connections Rcb along and between metal layer 1 and the silicided poly and n+ active layers. It is possible to arrange multiple such paths in any suitable combinations for testing the particular integrated circuit of interest.
A further possibility is that the interface can be arranged to provide a particular visual pattern on the surface of the wafer. Typically this might primarily be down to the pattern of tracks and contacts provided in the uppermost metal layer, for instance in the example of
The access contacts may be provided in standard locations and/or spacings for each integrated circuit. This can allow a universal test head to be used to test may different types of integrated circuit. Alternatively, the access contacts may be provided at different locations and/or spacings for different types of integrated circuit. This may require a different test head for each different type of integrated circuit. Since different circuits have different combinations of elements, this may be the case even where the access contacts are provided in standard locations and/or spacings.
If the interface provides a visual pattern, this can be also be provided on the test head to enable a tester to readily tell whether a correct test head is being used.
It is or course to be understood that the invention is not to be restricted to the details of the above embodiments which are described by way of example only.
While the invention has been described by way of example and in terms of the specific embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
| Number | Date | Country | Kind |
|---|---|---|---|
| 0903286.3 | Feb 2009 | GB | national |
