Patent Grant
8084769
1. Field of the Invention
The present invention relates to a test pattern design. In particular, the present invention relates to an ideal test key design for gate oxide thickness extraction.
2. Description of the Prior Art
The gate oxide capacitance-voltage (CV) curve provides many essential fundamentals to oxide thickness extraction, mobility calculation, metallurgical channel length determination and interface trap characterization, which are the critical parameters of advanced CMOS technology development. However, as the critical dimension decreases, the oxide thickness is aggressively scaled down (˜2.0 nm) for advanced ultra-thin oxide process development so the measured CV curve is distorted due to exponentially increasing gate leakage current and series parasitic resistance.
The following equation predicts the error ratio of the measured capacitance and the real capacitance:
Cm=Cinv/{1+(Rs)/(Rp)}2
Cinv: real capacitance/ideal capacitance
Cm: measured capacitance
Rp: total resistance of gate oxide
Rs: R1(poly resistance)+R2 (gate channel resistance)+R3 (contact and metal resustance)
It is accordingly concluded that in order to render the Cm value approach to the Cinv value as much as possible, either increasing the Rp or decreasing the Rs will do. To solve this issue, several different solutions are known.
In “A Floating Well Method for Exact Capacitance-Voltage Measurement of Nano Technology,” Hung-Der Su et al., IEEE Trans. Electron Device, Vol. 50, No. 6, p.p. 1543-1544, 2003, it mentions a two-element approach with smaller test pattern (25 μm2 with 0.4 pF total capacitance). However, even a tiny 20 fF parasitic capacitance would cause undesirable error on oxide thickness extraction.
In “Extending Two-Element Capacitance Extraction Method Toward Ultraleaky Gate Oxides Using a Short-Channel Length,” Jung-Suk Goo et al., IEEE Electron Device Letters, Vol. 25, No. 12, p.p. 819-821, 2004, it proposes using gate length shorter than 0.2 μm in parallel model for a lower channel resistance. Nevertheless it is easily understood that in practice even a 10 nm gate length variation caused by any possible imperfection could still lead 5%, an unacceptable error on oxide thickness extraction.
Therefore, a better approach is still required to minimize the error of measured thickness from process-induced gate area variation and parasitic capacitance.
The present invention in one aspect provides a testkey design pattern to meet the above-mentioned demand. The testkey design pattern of the present invention includes a conductive contact, a plurality of parallel conductive lines of a first width vertically and electrically connected to the conductive contact, and a plurality pairs of sources and drains respectively directly connected to each side of the conductive line, each pair of source and drain and part of the conductive line of a first length directly connected to the source and drain form an electronic device, and the electronic devices form an n*m array. The n and m each represents the line number and the row number of the array.
Because the electronic devices form an n*m array, they are an ensemble to reduce the total resistance for the parallel effect and therefore increase the accuracy of the measurement.
The present invention in another aspect provides a testkey design pattern to meet the above-mentioned demand. The testkey design pattern of the present invention includes: a first conductive contact, at least one conductive line of a first width vertically and electrically connected to the first conductive contact, a second conductive contact vertically and electrically connected to the conductive line, and at least one pair of source and drain respectively directly connected to each side of the conductive line. The pair of source and drain and part of the conductive line of a first length directly connected to the source and drain form an electronic device.
Because the electronic device is simultaneously connected to both the first conductive contact and the second conductive contact, two conductive contacts together averagely decrease 50% of the total resistance, and therefore increase the accuracy of the measurement.
The present invention provides two different approaches, i.e. the array arrangement of the electronic devices and two conductive contacts for the electronic devices, to decrease the ratio of (Rs)/(Rp) so as to satisfy the requirement of less error in Cm measurement without scarifying precise calibration, equipment cost or other crucial factors and therefore increase the accuracy of the measured Cm values.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
The present invention provides better testkey design patterns for measuring Cm values with less error and for better gate oxide thickness extraction.
In the first preferred embodiment, the present invention provides a testkey design pattern of array type to meet the above-mentioned demand, as shown in
The conductive contact 110 is useful in providing conductive contact for Cm measurement. For the nature of conductivity, the conductive contact 110 may include a material such as silicon, poly-Si for example, and metal. Similarly, the conductive lines 120 may include a material such as silicon, poly-Si for example, or a metal.
The parallel conductive lines 120 are vertically and electrically connected to the conductive contact 110 and have a first width W1. The first width W1 is preferable between 0.2-7 μm. If the first width W1 is larger than 7 μm, it may increase the total resistance. On the other hand, if the first width W1 is smaller than 0.2 μm, it would tolerate less fabrication errors.
At least one pair of source and drain 130 is respectively and directly connected to each side of the conductive line 120. Each pair of source and drain 130 and part of the conductive line 120 of a first length L1 which is directly connected to the source and drain form an electronic device 140. Preferably, the sources and drains 130 are symmetrically connected to each side of the conductive line 120 as shown in
In one preferred embodiment of the present invention, the total gate area (W1*L1*n*m) may be larger than 100 μm2 for reducing the impact of the parasitic capacitance. In another preferred embodiment of the present invention, the ratio of L1/W1 may be less than 5 for minimizing the poly series resistance impact on CV curve.
Because the electronic devices 140 form an n*m array, they are an ensemble to reduce the total resistance for the parallel effect and therefore increase the accuracy of the measured values.
In the second preferred embodiment, the present invention provides a testkey design pattern of two-end-contact type to meet the above-mentioned demand, as shown in
The first conductive contact 210 and the second conductive contact 250 are advantageous in more accurate Cm measurement due to less resistance. Because the two-end-contact type provides two current paths instead of one as shown in the first embodiment, the two-end-contact type may averagely decrease the total resistance by about 50%, which allows less Rs value as explained before and results in more accurate Cm measurement. For the nature of conductivity, the first conductive contact 210 and the second conductive contact 250 may independently include a material such as silicon, or a metal. Silicon may be a poly-Si.
Similarly, the conductive line 220 may include a material such as silicon, poly-Si for example, or a metal. The conductive 220 line is vertically and electrically connected to both the first conductive contact 210 and the second conductive contact 250 and has a first width W1. The first width W1 is preferable between 0.2-7 μm. If the first width W1 is larger than 7 μm, it may negatively increase the total resistance. On the other hand, if the first width W1 is smaller than 0.2 μm, it would allow less fabrication errors. In one preferred embodiment, if there are more than one conductive lines present, conductive lines 220A and 220Z for example, they may be arranged to be parallel to each other, as shown in
At least one pair of source and drain 230 is respectively and directly connected to each side of the conductive line 220. Each pair of source and drain 230 and part of the conductive line of a first length L1 which is directly connected to the source and drain 230 form an electronic device 240. Preferably, the source and drain 230 are symmetrically connected to each side of the conductive line 220 as shown in
In still another preferred embodiment of the present invention, the total gate area (W1*L1*n*m) may be larger than 100 μm2 for reducing the impact of the parasitic capacitance. In yet another preferred embodiment of the present invention, the ratio of L1/W1 may be less than 5 for minimizing the poly series resistance impact on CV curve.
Based on the principle of the two-end-contact type, there may be other variations. For example, the testkey design pattern of the present invention may include two or more conductive contacts and the conductive lines are arranged between the conductive contacts, as shown in
Because the electronic device is simultaneously connected to both the first conductive contact and the second conductive contact, two conductive contacts together averagely decrease 50% of the total resistance, and therefore increase the accuracy of the measured values.
The present invention provides the following comparative example and the working examples for the illustration of the advantages of the present invention.
It is understood from the comparison of the above data that the more the devices, the less the total resistance. The testkey design patterns of the present invention provide better approaches for measuring Cm values with less error and for better gate oxide thickness extraction.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
| Number | Name | Date | Kind |
|---|---|---|---|
| 5304925 | Ebina | Apr 1994 | A |
| 5821766 | Kim et al. | Oct 1998 | A |
| 5977558 | Lee | Nov 1999 | A |
| 6521910 | Lin | Feb 2003 | B1 |
| 20030090285 | Sher et al. | May 2003 | A1 |
| 20060113533 | Tamaki et al. | Jun 2006 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20080197351 A1 | Aug 2008 | US |
