The present disclosure relates to a semiconductor memory device, and more particularly to a thermal code transmission circuit capable of outputting a thermal code generated from a thermal sensor through a TQ pad placed in an input pad unit, thereby reducing the size of a chip and an output driver.
Generally, a volatile semiconductor memory device such as a DRAM has been developed to a high-speed and high-integrated memory in order to mate with the high performance of an electronic system such as a personal computer or an electronic communication apparatus. In addition, since a low power consumption characteristic is important in the case of a mobile DRAM used for a cellular phone or a notebook computer, research and development have been actively performed to reduce operational current and stand-by current.
The data retention characteristic of a DRAM memory cell including a transistor and a storage capacitor is very sensitive to the temperature. Accordingly, the semiconductor memory device is adaptively controlled according to temperature characteristics, thereby greatly reducing power consumption. For example, there has been proposed a method of adjusting a refresh period based on temperature information detected by a thermal sensor installed in the semiconductor memory.
As shown in
The thermal sensor 10 generates thermal codes T0 to T5 including internal thermal information of the mobile DRAM and a high-temperature determination signal TQ85 enabled when the internal temperature of the mobile DRAM is 85□ or more. The high-temperature determination signal TQ85 is output through the TQ pad 14. The thermal code transmission circuit 12 receives the thermal codes T0 to T5 to generate output thermal codes T<0:5>, and the output thermal codes T<0:5> are output through a plurality of DQ pads 30 using the global metal line 20.
Generally, the thermal sensor is mounted on the input pad unit 1 having a spatial margin in the mobile DRAM. Accordingly, in order to output the thermal codes T0 to T5 generated from the thermal sensor 10 to the DQ pad 30, the output thermal codes T<0:5> must be delivered to the DQ pad 30 through the global metal line 20 formed in the peri-area 2. Since the global metal line 20 occupying an area of 8×8000 μm is typically required to transmit 6-bit output thermal codes T<0:5>, the global metal line 20 exerts a serious influence on the size of the mobile DRAM chip. In addition, since the output thermal codes T<0:5> must be delivered by using the global metal line 20 passing through the peri-area 2, the output driver must be enlarged.
In an aspect of the present disclosure, a thermal code transmission circuit and a semiconductor memory device using the same are provided that are capable of outputting thermal codes generated from a thermal sensor through a TQ pad placed in an input pad unit, thereby reducing the size of a chip and an output driver.
In an embodiment, a thermal code transmission circuit includes a select signal generator which generates a select signal in response to a first enable signal, a level signal generator which receives the first enable signal and generates a level signal, an update signal generator which receives the level signal and a first update signal and generates a second update signal, a latch unit which receives a thermal code in response to the second update signal and outputs the thermal code as an output thermal code, and a thermal code output unit which selectively outputs the output thermal code in response to the select signal.
The first enable signal is a pulse signal used to output the output thermal code.
The select signal generator can include a counter unit which receives the first enable signal and performs a counting operation to generate a counter signal, and a decoder which decodes the counter signal to generate the select signal.
The level signal generator can include a pull-down device which pull-down drives a predetermined node in response to the first enable signal, a pull-up device which pull-up drives the node in response to a reset signal, and a latch which latches a signal of the node.
The pull-down device can be an NMOS transistor, and the pull-up device can be a PMOS transistor.
The update signal generator can include a logic device which receives the first update signal and the level signal and performs a logical operation with respect to the first update signal and the level signal.
The logic device can generate the second update signal which is disabled in response to enable of the level signal.
The latch unit can include a transmission device which transmits the thermal code in response to the second update signal, and a latch which latches an output signal of the transmission device.
The thermal code output unit can include a high-temperature determination signal transmission unit which transmits a high-temperature determination signal in response to a second enable signal and the level signal; and a first buffer which buffers the output thermal code in response to the select signal.
The high-temperature determination signal transmission unit can include a logic module which receives the second enable signal and a buffering signal of the level signal and performs a logical operation with respect to the second enable signal and the buffering signal of the level signal, and a second buffer which buffers the high-temperature determination signal and outputs the high-temperature determination signal in response to an output signal of the logic module.
The thermal code transmission circuit can further include a latch connected between an output terminal of the first and second buffers and an output pad.
The output pad is formed in an area identical to an area of a thermal sensor which generates the thermal code.
In another embodiment, a semiconductor memory device includes a thermal sensor which generates a plurality of thermal codes and a high-temperature determination signal, a thermal code transmission circuit which receives the thermal codes and the high-temperature determination signal and selectively outputs one of the thermal codes or the high-temperature determination signal, and an output pad which receives and outputs an output signal of the thermal code transmission circuit.
The above and other aspects, features and other advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
Hereinafter, examples and embodiments of the present disclosure will be described with reference to accompanying drawings. However, the examples and embodiments are for illustrative purposes only and are not intended to limit the scope of the invention.
As shown in
The thermal sensor 22 generates first to sixth thermal codes T0 to T5 and a high-temperature determination signal TQ85. The thermal sensor 22 generates the first to sixth thermal codes T0 to T5 by converting analog thermal signals, which have been generated using a bandgap reference circuit or a widlar circuit, into digital thermal signals through an analog to digital converter (AD converter). The high-temperature determination signal TQ85 is used to determine if the internal temperature of a semiconductor memory chip is 85□ or more, and may be generated based on the thermal signals.
The thermal code transmission circuit 24 includes the select signal generator 30, the level signal generator 32, the update signal generator 34, the latch unit 36, and the thermal code output unit 38.
The select signal generator 30 generates first to sixth select signals SEL0 to SEL5 in response to a first enable signal TM_P enabled in order to output the first to sixth thermal codes T0 to T5. The first enable signal TM_P is a pulse signal. In more detail, as shown in the example of
The level signal generator 32 receives the first enable signal TM_P to generate a level signal TM_L. In more detail, as shown in the example of
As shown in the example of
As shown in the example of
In more detail, referring to the example of
The thermal code output unit 38 includes a high-temperature determination signal transmission unit 600, which transmits the high-temperature determination signal TQ85 to the node nd60 in response to the level signal TM_L and the second enable signal TQ_EN enabled in order to output the high-temperature determination signal TQ85, a buffer unit 604, which buffers the first to sixth output thermal codes TN<0:5> and outputs the first to sixth output thermal codes TN<0:5> to the node nd60 in response to the first to sixth select signals SEL0 to SEL5, and a latch unit 670, which latches the signal of the node nd60 and transmits the signal of the node nd60 to the TQ pad 26.
The high-temperature determination signal transmission unit 600 includes a NAND gate ND60, which receives the second enable signal TQ_EN and the inverse signal of the level signal TM_L and performs a NAND operation with respect to the second enable signal TQ_EN and the inverse signal of the level signal TM_L to generate a signal TR, an inverter IV62, which inverts the output signal of the NAND gate ND60 to generate an inverse signal TRB, and an inverter IV64, which buffers the high-temperature determination signal TQ85 and outputs the high-temperature determination signal TQ85 to the node nd60 in response to the signal TR and the inverse signal TRB.
The buffer unit 604 includes first to sixth buffers 610 to 660. The first buffer 610 buffers the first output thermal code TN<0> and outputs the first output thermal code TN<0> to the node nd60 in response to the first select signal SEL0. The second buffer 620 buffers the second output thermal code TN<1> and outputs the second output thermal code TN<1> to the node nd60 in response to the second select signal SEL1. The third buffer 630 buffers the third output thermal code TN<2> and outputs the third output thermal code TN<2> to the node nd60 in response to the third select signal SEL2. The fourth buffer 640 buffers the fourth output thermal code TN<3> and outputs the fourth output thermal code TN<3> to the node nd60 in response to the fourth select signal SEL3. The fifth buffer 650 buffers the fifth output thermal code TN<4> and outputs the fifth output thermal code TN<4> to the node nd60 in response to the fifth select signal SEL4. The sixth buffer 660 buffers the sixth output thermal code TN<5> and outputs the sixth output thermal code TN<5> to the node nd60 in response to the sixth select signal SEL5.
Hereinafter, the operation of the semiconductor memory device having the above structure will be described.
The thermal sensor 22 shown in the example of
Then, the thermal code transmission circuit 24 receives the first to sixth thermal codes T0 to T5 and the high-temperature determination signal TQ85 and outputs the first to sixth thermal codes T0 to T5 and the high-temperature determination signal TQ85 through the TQ pad 26. The thermal code transmission circuit 24 according to the present embodiment receives and latches the first to sixth thermal codes T0 to T5 to generate the first to sixth output thermal codes TN<0:5> and selectively outputs the first to sixth output thermal codes TN<0:5> through the TQ pad 25 according to the first to sixth select signals SEL0 to SEL5. Since the thermal code transmission circuit 24 according to the present embodiment outputs the first to sixth output thermal codes TN<0:5>, which are generated in an input pad unit, through the TQ pad 26 placed in the input pad unit, it is unnecessary to install a global metal line used to transmit the first to sixth output thermal codes TN<0:5> to a DQ pad. Accordingly, a mobile DRAM chip including the semiconductor memory device according to the present embodiment and an output driver which outputs the first to sixth output thermal codes TN<0:5> can be realized with a small size. Hereinafter, the operation of the thermal code transmission circuit 24 will be described in more detail.
First, the select signal generator 30 shown in the example of
Next, the level signal generator 32 shown in the example of
Thereafter, the update signal generator 34 shown in the is example of
Subsequently, the latch unit 36 shown in the example of
The thermal code output unit 38 shown in the example of
Meanwhile, in the case in which the first to sixth output thermal codes TN<0:5> are selectively output through the TQ pad 26, the second enable signal TQ-EN is disabled at a low level, and the level signal TM_L is enabled at a high level. Accordingly, the inverter IV64 does not deliver the high-temperature determination signal TQ85 to the node nd60. At this time, since one of the first to sixth select signals SEL0 to SEL5 is selectively enabled at a high level according to the number of pulses of the first enable signal TM_P which has been enabled, one of the first to sixth output thermal codes TN<0:5> is selectively delivered to the node nd60 through one of the first to sixth buffers 610 to 660 and then output to the TQ pad 26 through the latch 670.
As described above, the semiconductor memory device according to the present embodiment includes the thermal code transmission circuit 24 to select the high-temperature determination signal TQ85, or one of the first to sixth output thermal codes TN<0:5>, which have been generated from the thermal sensor 22, and output the selected signal through the TQ pad 26. Accordingly, in contrast to a conventional technology, it is unnecessary to install a global metal line 20 in a peri-area 2 in order to output the first to sixth output thermal codes TN<0:5> through a DQ pad 30. Therefore, the size of a chip and an output driver can be reduced. In addition, power consumption for the transmission of the first to sixth output thermal codes TN<0:5> can be reduced.
Although examples and embodiments of the present invention have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.
The present disclosure claims priority to Korean application 10-2007-0141035, filed on Dec. 28, 2007, the entire contents of which are incorporated herein by reference.
Number | Date | Country | Kind |
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10-2007-0141035 | Dec 2007 | KR | national |
Number | Name | Date | Kind |
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7443754 | Sako | Oct 2008 | B2 |
20080106451 | Jeong et al. | May 2008 | A1 |
Number | Date | Country |
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10-2005-0033123 | Apr 2005 | KR |
10-2005-0041600 | May 2005 | KR |
10-2005-0063880 | Jun 2005 | KR |
10-2006-01079 19 | Nov 2006 | KR |
10-2007-0117735 | Dec 2007 | KR |
Number | Date | Country | |
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20090168589 A1 | Jul 2009 | US |