Claims
- 1. A method of fabricating a thermal ink-jet printhead substructure comprising the steps of:
- providing a substrate;
- forming at least one layer of each of a conductive material and a resistive material on the substrate;
- covering at least part of the resistive material with passivation material; and
- masking and removing predetermined areas of the conductive and resistive material to define a resistor member, conductive traces and conductive bonding pads utilizing no more than two lithographic masks.
- 2. The method of claim 1 wherein the forming step comprises depositing on the substrate the conductive material and thereafter depositing the resistive material.
- 3. The method of claim 1 wherein the covering step includes covering at least part of the resistive material with a passivation layer having a thickness of about 0.2 .mu.m.
- 4. The method of claim 1 wherein the forming step comprises depositing on the substrate the resistive material and thereafter depositing the conductive material and wherein the covering step includes depositing the passivation material in two layers, a first passivation layer being deposited before a second passivation layer and the first passivation layer comprising silicon carbide.
- 5. The method of claim 1 including the step of depositing a metal barrier layer between the conductive material and resistive material.
- 6. A method of fabricating a thermal ink-jet printhead substructure comprising the steps of:
- providing a substrate
- forming at least one layer of each of a conductive material and a resistive material on the substrate;
- covering at least part of the resistive material with passivation material; and
- masking and removing predetermined areas of the conductive and resistive material to define a resistor member, conductive traces and conductive bonding pads utilizing two lithographic masks; and
- wherein the forming step comprises depositing on the substrate the conductive material and thereafter depositing the resistive material.
- 7. The method of claim 6 wherein the covering step includes covering at least part of the resistive material with a passivation layer having a thickness of about 0.2 .mu.m.
- 8. The method of claim 6 wherein the forming step comprises depositing on the substrate the resistive material and thereafter depositing the conductive material and wherein the covering step includes depositing the passivation material in two layers, a first passivation layer being deposited before a second passivation layer and the first passivation layer comprising silicon carbide.
- 9. The method of claim 6 including the step of depositing a metal barrier layer between the conductive material and resistive material.
- 10. The method of claim 6 wherein the forming step includes depositing titanium nitride as the resistive material.
- 11. The method of claim 6 wherein the forming step includes depositing a tantalum nitride as the resistive material.
- 12. The method of claim 1 including the step of covering at least part of the passivation material with a cavitation layer.
CROSS REFERENCE TO RELATED APPLICATION(S)
This is a divisional of application Ser. No. 08/568,208 filed on Dec. 6, 1995 now U.S. Pat. No. 5,883,650.
US Referenced Citations (30)
Non-Patent Literature Citations (1)
Entry |
Ameen et al., IBM Technical Disclosure Bulletin, vol. 21, No. 3, Aug. 1978, pp. 953-954. |
Divisions (1)
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Number |
Date |
Country |
Parent |
568208 |
Dec 1995 |
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