Patent Application
20100257871
1. Field of the Invention
This invention relates to thermoelectric devices for power conversion and cooling which utilize thin film thermoelectric materials.
2. Background of the Invention
A thermoelectric device can produce electrical energy when a heat flux lows through opposite conductivity types of a thermoelectric material. Furthermore, a thermoelectric device can cool an attached object when a current is flown in an appropriate direction through the thermoelectric material. In a thermoelectric generator, for example, a Seebeck voltage generated across a thermoelectric device can be used to drive a current in a connected load circuit. Indeed, thermoelectric generators can generate power from a variety of heat sources. For example, a thermoelectric power device can be connected to a wall of a combustion chamber and therefore generate power from the heat flux flowing from the combustion wall. In this example, a fuel is burnt to produce the heat flux for thermoelectric power generation; however, other heat sources applicable for thermoelectric generators include solar-heated sources, radioisotope-heated sources, and nuclear reactor waste heat sources. Thermoelectric generators typically include external electronic circuitry such as a DC-DC conversion circuits or DC-AC converters for receiving power from the thermoelectric elements at a low voltage and for delivering power at higher voltages.
In conventional thermoelectric devices, the efficiency of thermoelectric conversion is at about 6 to 8%. Accordingly, there is a drawback that thermoelectric conversion efficiency is low as compared with the other direct energy conversion systems such as for example a fuel cell device. If thermoelectric devices had higher conversion efficiencies, then thermoelectric thermoelectric power conversion devices could be effectively employed even in automobiles to increase the total fuel efficiency of the automobile by converting waste heat spent from the combustion process into electrical power.
Low efficiencies have also limited the application of thermoelectric devices in cooling and refrigeration applications. Chen et al. in U.S. Pat. No. 5,713,208, the entire contents of which are incorporated by reference, describe a thermoelectric cooling apparatus which includes a plurality of thermoelectric coolers each having a hot side connected to a heat sink and a cold side coupled to an object to be cooled. While Chen et al. describe that thermoelectric coolers may be any suitable thermoelectric coolers such as those supplied by Melcor under catalog number CP 2-127-06L, the efficiency of these coolers, like those of the afore-mentioned power conversion thermoelectric devices, are limited.
The dimensionless thermoelectric figure of merit (ZT) is a measure of the effectiveness of the material for both cooling and power conversion applications. The Seebeck coefficient (S) is a measure of how readily electrons (or holes) convert thermal to electrical energy as the electrons move across a temperature gradient. At a given temperature, the thermoelectric figure of merit ZT for a given material is maximized at an optimum doping level. In most materials, the thermoelectric figure of merit ZT is maximized at doping levels of approximately 1019 cm−3. Currently, the best non-superlattice thermoelectric materials have a maximum ZT of approximately 1. Today, bulk thermoelectric materials based on p-BixSb2-xTe3 and n-Bi2Te3-xSex do not have a sufficient figure-of-merit (ZT) to allow economical application in many power conversion situations.
In contrast to bulk materials, the thermal properties of superlattice structures can be improved over that of the thermal properties of bulk materials. Superlattice structures in thermoelectric materials have been investigated as structures whose engineered properties can lead to better semiconductor and thermoelectric properties. The fabrication of a superlattice by molecular beam epitaxy (MBE), or other known epitaxial growth techniques, is generally known. The choice of materials and the relative amounts of the materials which make up the superlattice are factors in determining the characteristics of the superlattice. For use as a thermoelectric material, it is desirable to choose the materials, and their relative amounts, so that the thermoelectric figure of merit (ZT) and Seebeck coefficient (S) are maximized. Thus, superlattice materials are expected to have higher ZT values than bulk-materials. Despite the higher ZT of superlattice thin-film materials, thin film thermoelectric devices are presently limited by thermal mismatch and temperature gradient issues and also are practically limited by the high cost of thin-film superlattice materials.
One object of some embodiments of the present invention is to provide a thermoelectric device structure utilizing high ZT thermoelectric materials.
Another object of some embodiments of the present invention is to utilize a thermoelectric device structure in which the thermoelectric properties of the device are not contravened by inadvertent heat flux around the active thermoelectric elements in the device.
A further object of some embodiments of the present invention is to provide a thermoelectric device structure for cooling power-dissipating devices.
Still another object of some embodiments of the present invention is to provide a thermoelectric device which can convert power from a wide variety of moderate to high temperature heat sources, including but not limited to fuel sources.
Accordingly, one object of some embodiments of the present invention is to provide a multi-stage thermoelectric device for power conversion from heat sources at temperatures of 600 to 850 K.
Still another object of some embodiments of the present invention is to provide a thermoelectric device which can be converted from a power conversion device to a heat pump device should coolant to a heat sink of the thermoelectric device be interrupted.
Yet another object of some embodiments of the present invention is to provide a thermoelectric device which utilizes both bulk thermoelectrics and superlattice thermoelectric films to exploit for each respective thermoelectric material those thermoelectric properties in operational temperature ranges most suitable for each.
Accordingly, one object of some embodiments of the present invention is to provide a thermoelectric device in which there is a high internal heat-flux within an individual thermoelectric stage and a low external heat-flux across the entirety of the thermoelectric device.
Various of these and other objects of some embodiments of the present invention are accomplished in several embodiments of the present invention.
One exemplary embodiment includes a novel thermoelectric device having at least one thermoelectric unit including a thermoelectric pair of n-type and p-type thermoelements, a first header coupled to one side of the thermoelectric pair, a second header coupled to a second side of the thermoelectric pair, and a thermal impedance increasing device disposed between the thermoelectric pair and one of the first and second headers.
A more complete appreciation of the present invention and many attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
Referring now to the drawings, wherein like reference numerals designate identical, or corresponding parts throughout the several views, and more particularly to
In some embodiments of the present invention, due to the different thermoelectric properties of the n and p-type materials of the thermoelements 2a and 2b, electrons and holes in these materials diffuse at different rates across the respective n and p-type thermoelements, thereby creating a voltage difference across the pair of n and p-type thermoelements. In this embodiment, a cooling device (not shown) is coupled to the lower side header 4 to permit dissipation of heat. Otherwise, the upper side header 3, the pair of n and p-type thermoelements 2a and 2b, and the lower side header 4 would all come to nearly equivalent temperatures. As a consequence, the electrons and holes in the n and p-type thermoelements 2a and 2b would stop diffusing to the lower-side header.
In other embodiments of the present invention, electron and hole current can driven through the n and p-type thermoelements 2a and 2b by an applied voltage to thereby cool the upper side header 3. Owing to electrical barriers existing between electrical connection 6 and the pair of n and p-type thermoelements 2a and 2b, the electron and hole current will preferentially transport those electrons and holes having a higher thermal energy, thereby cooling the upper side header 3. A heat dissipation device (not shown) coupled to the lower side header 4 permits dissipation of heat from the device, else the lower side header 4 would come to a temperature such that heat, via diffusion of phonons, would flow back to the upper-side header 3 at a rate equal to the heat being carried from the upper-side header 3 by the electron and hole current, thereby eliminating the cooling.
The optional heat pipe 5 represents a mechanism to increase the thermal impedance (through the gaps) between the upper side header 3 and the lower side header 4 to a value significantly larger (by a factor of 100 or more) than the thermal impedance across the thermoelectric pair 2a and 2b. As shown in
Regardless of the heat pipe, the thermoelectric devices of some embodiments of the present invention conduct a high active heat flux, while maintaining a much lower flux through the surfaces 1 and 4, through the pair of thermoelements which permits some embodiments of the present invention to realize ultra-high specific power in the pair of n and p-type thermoelements 2a and 2b. Thus, some embodiments of the present invention operates with a high active flux through each of the thermoelements while having a low input/output flux across the entirety of the thermoelectric device. As described herein, this aspect of some embodiments of the present invention is referred as High Active Flux-Low Input-Output Flux (HAF-LIOF). This aspect is illustrated pictorially in
The packing fraction of thermoelements (i.e., the fraction of area occupied by the pair of n and p-type thermoelements 2a and 2b relative to a unit area of for example the upper-side header 3) in some embodiments of the present invention is less than 50%, less than 20%, and can be significantly lower, 0.5-1% for example. A unit area for the heat spreader is defined as that fraction of the total area of the heat spreader which principally conducts heat into one of the associated pairs of n and p-type thermoelements attached to the heat spreader. For the single pair of n and p-type thermoelements shown in
The preferred packing fraction is a function of the heat flux available at the heat-source, the required ΔT needed across the thermoelement to achieve the maximum efficiency, and the heat-flux that can be dissipated at the heat-sink. For example, if the required heat-flux through the device element is 2500 W/cm2 to generate a requisite ΔT, and the heat-flux that can be efficiently dissipated at the heat-sink is 25 W/cm2, then a packing fraction of 1% will be used (i.e. 25/2500×100%). However, if the heat-flux that can efficiently be dissipated at the sink is only 2.5 W/cm2, then a packing fraction needed would be 0.1% for the same heat-flux of 2500 W/cm2 through each thermoelectric pair. A smaller packing fraction, however, can result in increased parasitic thermal transfer losses through any medium (such as air, Nitrogen, Helium) between the hot and cold-sides of the thermoelectric module.
Therefore, in thermoelectric devices of some embodiments of the present invention, besides using a heat pipe, other thermal impedance increasing devices can be employed. For example, a partial vacuum (i.e. 1 Torr) as a low thermal impedance medium can be used in a module (e.g. the module 10 encapsulating the thermoelectric devices shown in
The headers and heat pipes of some embodiments of the present invention have thermally conducting properties. Examples of suitable materials for the headers and heat pipes include for example AlN, SiC, and diamond. These materials have relatively high thermal conductivities (e.g. 5-20 W/cm-K) and offer the advantage of being electrically insulating. Alternatively, metallic or other semiconductor materials can be used for the headers and heat pipes of some embodiments of the present invention provided a suitable electrical insulating layer 8 is added to the surface of those materials. The thermal conductance through the electrical insulating layer preferably presents no substantial impediment to vertical heat flow through the pair of n and p-type thermoelements 2a and 2b.
For example, the headers of some embodiments of the present invention can be made from a Si substrate of a thermal conductivity of ˜1.2 to 1.6 W/cm-K having a thin (i.e. ˜10 nm to 1000 nm) SiO2 or SixNy layer of a thermal conductivity of ˜0.015 W/cm-K deposited thereon. For example, the headers of some embodiments of the present invention can also be made from a Cu substrate of a thermal conductivity of ˜4 W/cm-K having a thin (i.e. ˜100 to 1000 nm) SiO2 or SixNy layer of a thermal conductivity of ˜0.015 W/cm-K deposited thereon. If a SiC header or heat pipe is used that is electrically conducting (e.g. a doped SiC material), a similar insulating layer can be applied as well.
Since the thermoelements are low voltage, high current devices, the electrical connections are preferably highly conductive having a low resistance (preferably 1/10th or less than that of the Ohmic resistance of the thermoelements). A low conductance for the electrical connections will undermine the efficiency of the thermoelectric stage by resistive losses in current flow through the thermoelectric device.
Accordingly, in general, some embodiments of the present invention may include a thermoelectric device having a first header (e.g. the upper side header 3) coupled to a heat source, a pair of n-type and p-type thermoelements (e.g. the pair of n and p-type thermoelements 2a and 2b) coupled to the first header and configured to conduct heat from the first header, a second header (e.g. the lower side header 4) coupled to the pair of n-type and p-type thermoelements and configured to conduct heat from the thermoelectric pair, and a heat pipe coupled to the pair of n-type and p-type thermoelements (e.g. the heat pipe 5 connected to the thermoelectric pair 2a and 2b) and elongated in a transverse direction across the thermoelectric device to separate the first header from the second header.
In some embodiments of the present invention, the thermoelectric devices cool the first header (and thus can cool heat dissipating devices coupled thereto) by the flow of an electrical current through electrical connections 6 and 7 through the thermoelements 2a and 2b, thus transporting heat in the electrical carriers (i.e., the electrons and holes) and thereby cooling the first header. In other embodiments of the present invention, the thermoelectric devices generate electrical power by the development of a voltage on the electrical connections 6 and 7 as heat flows from the first header (coupled to a heat source) through the thermoelements 2a and 2b to the second header (coupled to a heat sink).
Further, some embodiments of the present invention may not be limited to single stage and/or single pair thermoelement devices but can utilize multiple stages and/or multiple pairs of thermoelements in a single stage.
As shown in
In the multi-stage thermoelectric device depicted in
More specifically, the multi-stage thermoelectric device as illustrated in
The three-stage thermoelectric device depicted in
While the concepts of some embodiments of the present invention are not restricted to any particular family of thermoelectric materials, the use of superlattice materials improves thermoelectric device efficiency of the multi-stage thermoelectric device of some embodiments of the present invention. Conventional bulk Bi2Te3 thermoelectric devices offered by Hi-Z Inc. (San Diego, Calif.) exhibits a power density of 0.34 W/cm2 at a ΔT of 200 K for a specific power of about 0.165 W/gm. Yet, even unoptimized thin-film Bi2Te3-superlattice mini-module devices fabricated by the HAF-LIOF aspect of some embodiments of the present invention, even without the mid and high temperature thermoelectric power conversion stages discussed above, have demonstrated a power density of 0.7 W/cm2, with a ΔT of 77 K, and a specific power of 16.7 W/gm. Specific power is defined as the power produced per unit weight of the thermoelectric device. Both the specific power and the power density levels would increase with the addition of mid and high-temperature stages and further optimization of the low-temperature superlattice stage. Accordingly, thermoelectric devices of some embodiments of the present invention may realize a specific power greater than 1 W/gm and a power density greater than 0.5 W/cm2.
On the other hand, specific powers in a range of less than 0.0001 W/gm, 0.001 W/gm, and 0.01 W/gm, are possible with some embodiments of the present invention and are applicable to applications such as for example bio-medical devices. In these applications, the HAF-LIOF devices could be used for heat gathering from low temperature sources in a range of about 30-40° C. such as the human body for the powering of pacemakers or neuro-stimulators used to alleviate symptoms of Parkinson's disease or other neurological disorders.
The relevant properties, the lattice-mismatch and the bandgaps, of the PbTe/PbSe superlattice system are shown in Table 1.
Both materials PbTe and PbSe have similar thermal expansion coefficients; so that lattice mismatch at higher temperatures would be similar to that at 300 K. Also, kT at the temperatures of 500 to 650 K is about 0.05 eV, comparable to or larger than the bandgap difference between PbTe and PbSe. Thus, no barriers or quantum confinement effects will be present within the material, but a significant thermal conductivity reduction is expected in these superlattice materials.
Regarding the SiGe materials family, Si/Ge superlattice materials, according to some embodiments of the present invention, are attractive for high temperature applications (i.e., 650 K to 850 K). For example, Si/Ge superlattice materials deposited at about ˜1000 K have shown a dramatic reduction in thermal conductivity and concomitantly an enhancement in ZT. Although Si/Ge superlattices may only offer a ZT of only about ˜0.8 at 300 K, significantly below that of a Bi2Te3/Sb2Te3 superlattice or a Bi2Te3/Bi2Te3-xSex superlattice, the Si/Ge superlattices are likely to offer a much higher ZT at the higher temperatures employed in the upper thermoelectric stages depicted in
In addition to superlattices, other quantum-confined structures and structures can be utilized according to some embodiments of the present invention in which a strong thermal conductivity reduction is obtained while at the same time maintaining electrical conduction across the thermoelectric stages. For example, PbTe-based quantum-dot superlattices (QDSL) are suitable materials for the n and p-type thermoelements according to some embodiments of the present invention. ZT values for these materials are achievable in a range of 1.5 to 2, in the temperature range of 450 K-550 K.
Furthermore, even ZnSb and skutterrudites, (i.e., materials with a known ZT >1 over a temperature range suitable for power conversion) are also applicable according to some embodiments of the present invention provided these materials are in thin substrate form (i.e., in a thickness of 1.00 to 200 μm) and are used in a temperature range of 500 K to 900 K. Thus, the HAF-LIOF, high-power density, multi-stage power conversion device concept according to some embodiments of the present invention is not limited to Bi2Te3-superlattice/PbTe/SiGe material combinations. Indeed, superlattices of Si/Ge, PbTe/PbSe, ZnSb/CdSb, InAs/InSb, CdTe/HgCdTe, GaxIn1-xAs/GayIn1-yAs can be used in the high-temperature and mid-temperature thermoelectric conversion stages, discussed above, thus providing a cascade thermoelectric device utilizing all superlattice materials.
For the lower temperature thermoelectric conversion stages according to some embodiments of the present invention and for single stage cooling devices operating near room temperature, superlattice stages of Bi2Te3—Sb2Te3 can be used.
In some embodiments of the present invention, the advances in ZT for the p and n-type superlattice materials have been incorporated into fabricated p-n thermoelement couples. By flipping the fabricated p-n couples onto a split semi-infinite Cu-plate as opposed to flipping the fabricated p-n couples onto a header with a limited-thickness metallization, a more accurate measure of the thermoelectric properties of the fabricated p-n thermoelement couples is possible. For instance, each one of the p-n thermoelement couples potentially carries a high-current (i.e., several Amps of current) and is a low-voltage thermoelectric device. Parasitic lead resistances can therefore affect the measured device efficiencies. Properties of the p-n thermoelement couples have been developed by fabrication and analysis of the p-n thermoelement couples on a split semi-infinite Cu-plate. In the fabricated thermoelectric devices, electrical contact resistances in the thermoelectric devices may be reduced and/or minimized between the metallizations and the p-n thermoelement couples, providing adequate electrical interfacing.
In addition to managing electrical contact resistances, thermal interface resistances may be reduced in the metal-to-dielectric interfaces according to some embodiments of the present invention by deep-annealing of a metal into the dielectric bulk or by utilizing an AIN-diffused Al—Cu interface.
Further, high aspect-ratio thermoelectric devices (either with thicker superlattice films or smaller-area devices) are provided by appropriate patterning and etching of the p-n couples (e.g., the thermoelectric pair 2a and 2b). An aspect ratio of the element is defined as the ratio of thickness/area of element in units of cm−1. Typical thickness of thermoelectric elements in the low-temperature stage can be about 5 μm to 20 μm (microns), while the mid and high temperature stages can have thicknesses ranging from 50 μm to 250 μm (microns). The aspect ratio, hence the area of each element of the various stages, are based on the thermal conductivity of the materials (noting that the thermal conductivities of the p and n-type elements within a stage can be different and so their aspect ratios to allow same ΔT (temperature differential) across both p and n-type elements of each stage can be different) of the various stages and the required ΔT (temperature differential) for each stage for increasing and/or maximizing the efficiency of the overall set of stages. The ΔT (temperature differential) of each stage is inversely proportional to thermal conductivity of the material and directly proportional to the aspect ratio. Hence, according to some embodiments of the present invention, the total heat flux through each stage is same; thus the aspect ratio (and the associated packing fraction) in each stage is adjusted with this criterion to meet the design ΔT for each stage.
Power conversion efficiencies achievable in, for example, the three-stage thermoelectric devices according to some embodiments of the present invention are calculable based on known equations. The maximum efficiency is obtained when the load ratio r, defined as RL/RG with RL being the load resistance and RG being the thermoelectric device internal resistance, is optimized for average ZT over the entire temperature range, ZTm. See, for example, H. J. Goldsmid, Electronic Refrigeration, Pion Limited, (1986).
Once r is known as per eqn. (1) shown below, the device efficiency it can be obtained by eqn. (2), shown below for a given ΔT (temperature differential), and mean operating temperature Tm.
r=(1+ZTm)1/2 (1)
ψ=ΔT/{[(r+1)/(r−1)]*Tm+ΔT/2} (2)
Power conversion efficiency estimates are shown in Table 2 of
Indeed, Table 2 illustrates the performance of various stages of a three-stage thermoelectric device according to some embodiments of the present invention as a function of ZT and the efficacy of thermal management at the heat-sink. The calculations in Table 2 are based on a module size of approximately ˜33 cm2. For these examples, a heat flux of ˜30 W/cm2 is assumed to flow from the heat-source (i.e., the upper-most header) to the heat sink (i.e., the lower-most header), yielding a heat-flux dissipation range of about ˜24.7 to 22.7 W/cm2 at the heat-sink. The power densities are calculated assuming a 5 μm thick superlattice element in the low-temperature Bi2Te3-super lattice stage and assuming a 100 μm thin-substrate for bulk thermoelements in the mid and high temperature stages. Table 2 indicates that higher ZT materials for both the mid-stage (460 K to 660 K) and high-stage (670 K to 890 K) may be advantageous.
For a given heat flow Q, in Watts, the aspect ratio determines the ΔT. The efficiency is a function of ΔT (temperature differential) and ZT. The power generated P, in Watts, is a product of Q times efficiency. Thus, power density, Pd, is a function of both area, thickness, ZT and Q. Hence, according to some embodiments of the present invention, one approach to achieve power densities of greater than 20 W/cm2 is to use thinner sections of thermoelement materials (e.g., preferably less than 300 μm).
Calculations of thermal-to-electrical conversion efficiency, corrected for lead resistances, versus internal ΔT across the flipped inverted p-n couple, and the ZT obtained from the efficiency equations indicate that about 85% of the external ΔT (and consequently the heat flux) is applied across the device. The 15% loss is primarily due to the thermal interface resistance between the metallization and the MN header. According to some embodiments of the present invention, the thermal interface resistance can be reduced in the metal-to-dielectric interface by deep-annealing of the metal into the dielectric bulk or by utilizing an AIN-diffused Al—Cu interface, as discussed above.
Calculated ZT values of the inverted couples utilized for demonstration of power conversion concepts of some embodiments of the present invention were about a ZT value of 1.1 at 300 K. The average ZT of the p-n couple of some embodiments of the present invention (e.g., the thermoelectric pair 2a and 2b) increases with temperature, consistent with the general trend of ZT shown in
One p-n couple of some embodiments of the present invention was tested up to a ΔT of nearly 85 K, corresponding to an active device heat flux within the thermoelement of ˜1800 W/cm2. For this tested p-n couple, the external heat flux was about 28 W/cm2 with a temperature rise of about 28 K at the heat-sink. Application of improved thermal management practices to operate even this test device with a ΔT of 150 K, even with the present ZT of ˜1.5, will permit an efficiency of ˜8.6% to be realized. Improvements in ZT values from 1.5 to ˜2 may realize in some embodiments of the present invention efficiencies of ˜11% for a ΔT of 150 K.
Accordingly some embodiments of the present invention may include a system for thermoelectric power conversion. The system includes a thermoelectric pair of n-type and p-type thermoelements, a first header coupled to one side of the thermoelectric pair, a second header coupled to a second side of the thermoelectric pair, a thermal impedance increasing device disposed between the thermoelectric pair and one of the first and second headers, and a heat sink coupled to the second header which dissipates heat at a rate which maintains a temperature of the second header below a temperature of the first header. Further, a coupling member can be used to couple the first header to a heat source. The heat source can be a combustion source, a radioactive source, a solar-heated source, and an electrical power device. The coupling member in some embodiments of the present invention can be a thermally conducting member having a thermal conductance of at least Al and extending between said first header and said heat source. Alternatively, the coupling member can be a steam pipe or a combustion exhaust pipe transporting heat flux by a convective medium such as, for example, steam or combustion gases.
Both p-type and n-type thin-film superlattice thermoelements of some embodiments of the present invention have been stable. Exposures to temperatures of about ˜450 K and times of up to 60 hours have showed no marked deterioration in the device ZT of these elements, as shown in Table 3, below.
Besides superlattices, the device fabrication methodologies and HAF-LIOF aspect of some embodiments of the present invention are applicable to thin substrates from two non-superlattice material systems, GaSb and InAs, corresponding to the bandgaps of the n-SiGe/p-TAGS and n-PbTe/p-TAGS systems. Open-circuit voltage as a function of ΔT in a 100 element GaSb and InAs thin-substrate module of some embodiments of the present invention are capable of Voc values of ˜4.5 Volts to ˜3.5 Volts and are capable to generate AT in excess of 100 K, corresponding to active heat fluxes of ˜300 W/cm2, needed for achieving high electrical power densities.
Various methods are available for the manufacturing of the devices and the device components of some embodiments of the present invention. Given below for purposes of illustration are steps and methods involved in fabricating the individual p and n-type thermoelectric pairs of some embodiments of the present invention and are steps and methods for integration of the thermoelectric pairs into modules. The steps and method described below are illustrative and are not given to imply any limitations of some embodiments of the present invention.
The thermoelectric materials utilized as the p and n-type thermoelements of some embodiments of the present invention are typically overgrown films on commercial substrates, the overgrown films having a thickness of, for example, 5 to 20 μm. Substrates for the growth of, for example, the thin-film superlattices or other thin film thermoelectric structures, may have the same conductivity type as the overgrown films or may permit the overgrowth of opposite conductivity type films. The overgrown films can be metallized to provide a low-resistance contact, such as a low-resistance Peltier contact.
In one fabrication method of some embodiments of the present invention, fabrication of the thermoelectric devices of some embodiments of the present invention is facilitated by inverted-couple processing. Table 4 shown in
Alternatively, films of a specific type can be formed on a common substrate and then selectively converting (e.g. by selective ion implantation) different regions of the formed thermoelectric material into n-type and p-type regions. For example, the thermoelements could be formed intrinsic (or specifically doped) and then type-converted to another (i.e., a p-type to n-type conversion or an n-type to p-type conversion) by for example impurity-diffusion. Type-conversion would then be performed at a convenient stage in the manufacturing process. Regardless of the specific details, a set of p and n-type materials having a pre-arranged pattern are attached to a common header like SiC, AIN, low-resistivity silicon, and silicon with a thin insulating layer.
In one fabrication method of some embodiments of the present invention, substrates including the individual n-type and p-type thermoelements are separated, for example, by scribing or laser dicing, into individual segments. The individual segments are then bonded onto a header such that alternating n-type and p-type conductivity materials exist between each adjacent thermoelement. The surfaces of the header that come in contact with the n- and p-type segments are preferably metallized prior to assembly to provide low-resistance electrical connection between adjacent n- and p-type segments where necessary to electrically interconnect adjacent thermoelements. Likewise, the surfaces of the individual n-type and p-type thermoelements that come in contact with the header are preferably metallized prior to assembly to provide the necessary low-resistance electrical connection to the n-type and p-type thermoelements, else a high electrical contact resistance can limit the efficiency of the thermoelectric stage and the resultant thermoelectric device.
Following bonding of n- and p-type segments, the substrates from each of the p- and n-segments are selectively removed, for example, by using selective etchants. The thermoelements are then patterned using photolithographic patterning followed, for example, by etching, or by laser ablation, to produce a desired cross-sectional thermal conduction area for some embodiments of the present invention (i.e., to set the aspect ratio and ultimately determine the packing fraction). Low resistivity contact metallizations are then evaporated on an upper surface of the n- and p-type thermoelements. In this step, either the same metallization can be used for both of the n- and p-type section, or different metallizations can be used (i.e., separate evaporations), depending on the contact resistance requirements. Sheet resistances, or conductances as specified above, associated with the metallizations are designed not to restrict the performance of the thermoelectric devices:
A top, pre-patterned metallization header can, in some embodiments of the present invention, be attached to the metallized sections to function as the aforementioned heat pipe. Alternatively, the header itself prior to metallization can be patterned to provide the aforementioned heat pipe. The formed pair of thermoelements (i.e., the n-thermoelement and the p-thermoelement) including the attached header can then be flipped and bonded to a second header. The second header, referred to for the purpose of illustration as a bottom header, thermally connects the n thermoelement to the p-thermoelement, but contains patterned electrical connections such that electrically the n thermoelement and the p-thermoelement are individually connected, as shown in
One illustrative example of inverted couple processing is given below:
P-type and n-type superlattice thermoelectric films are deposited on GaAs substrates. The deposited superlattice films are patterned with Cr/Au/Ni/Au metallizations. The deposited superlattice films and/or the GaAs substrates are etched in preparation for dicing. Diced strips of the p-type and n-type superlattice films attached to the GaAs substrates are then bonded in an alternating conductivity type pattern to a header. The header includes an AIN substrate having Ti/Au metallization (annealed) and having a subsequent Cu/No/Au topmost metallization. A Sn preform bonds the diced strips to the AIN substrate (functioning as a first header). The GaAs substrate is then etch removed, and Cr/Au/Ni/Au contacts are evaporated through shadow masks or evaporated and patterned to form electrical contacts to the superlattice thin films. Thick metal pads are then formed on the evaporated contacts to define, for example, a heat pipe structure. Dies containing the superlattice thin films and the attached AIN header are placed and bonded to a separate split metallized header (functioning as a second header) allowing for individual electrical connection to each of the n- and p-type thin film thermoelements.
By way of example, Table 5 depicts various bonding steps used to fabricate the three stage device shown in
As depicted in Table 5 in stage 3 of the thermoelectric device (i.e., the uppermost header), a preferred heat spreader is AIN or Si. In this stage, a AgCu eutectic is used as a solder material for bonding the heat spreader to the metallization layers on the afore-mentioned N—SiGe/P-TAGS thermoelements. Metallization layers on the N—SiGe/P-TAGS thermoelement pair include silver having a typical diffusion barrier layer of W or Mo or Ni or similar refractory metal to prevent diffusion of Ag into the N—SiGe and P-TAGS materials.
As depicted in Table 5, in stage 2 of the thermoelectric device, a preferred heat spreader is A1N. In this stage, a AgAuGe eutectic is used as a solder material for bonding the heat spreader to the metallization layers on the afore-mentioned N—PbTe/P-TAGS thermoelement pair. Metallization layers on the N—PbTe/P-TAGS thermoelement pair include silver having a typical diffusion barrier layers of Ni or W or Mo to prevent diffusion of Ag into the N—PbTe and P-TAGS materials.
As depicted in Table 5, in stage 3 of the thermoelectric device, a preferred heat spreader is SiC. In this stage, a Sn eutectic is used as a solder material for bonding the heat spreader to the metallization layers on the afore-mentioned n- and p-type Bi2Te3-superlattice-thin-film pair. Metallization layers on the n-type and p-type Bi2Te3-superlattice-thin-film pair include Cu having a diffusion barrier layer of Ni or a similar metal to prevent diffusion of Cu into the N-Bi2Te3 SL and/or P-type Bi2Te3 SL materials.
As depicted in Table 5, the uppermost stage (i.e., stage 3) can be bonded to the heat-source header (e.g., a Cu plate) using a AgCuP eutectic bond. Stages 2 and 3 can be eutectic bonded together using a AuIn eutectic. Stages 1 and 2 can be eutectic bonded together using a SnAu eutectic. Stage 1 can be bonded to the heat-sink header (e.g., an Al plate) using an InSn eutectic bond. Hence, in some embodiments of the present invention, successively-lower-melting-point eutectics may bond the successive stages so that the previously-bonded stages are in tact. Such measures serve to match or reduce the mismatch in the coefficients of thermal expansion between the various stages as successive bonding can cause thermal stress.
An example of stacking of the various stages to obtain efficient thermal interfaces between each of the adjacent stacks by using eutectic metal bonding is described by R. Venkatasubramanian et al in Appl. Phys. Lett., Vol. 60, 886 (1992), the entire contents of which are incorporated herein by reference.
A thermoelectric device according to some embodiments of the present invention can be attached to an integrated circuit die or wafer element (preferably to the backside) with or without an intervening layer of thermal grease or plastic adhesive. For direct attachment without intervening layers of thermal grease or plastic adhesive, a thin electrically insulating layer or a series of back-side p-n isolation junctions can be utilized to permit electrical isolation of the integrated circuit on the die from the currents flowing in the thermoelectric devices. In this approach, the “top” header joining the thermoelectric device of some embodiments of the present invention to the integrated circuit die is made of thick metallizations which form the electrical contact and the heat pipe to the p-n thermoelements. Suitable thermoelectric materials deposition/attachment/formation, type conversion, and patterning form the p-n thermoelements and the heat pipe structures. Subsequent metallizations complete a “bottom” header and provide in some embodiments of the present invention a place for attachment to a heat sink device (e.g., an air-cooled plate or a heat-pipe)
In the simplified process depicted in
Accordingly, various approaches of some embodiments of the present invention may include:
For attachment, several attachment methods can be used including: (1) soldering, (2) brazing, (3) friction bonding, and (4) insulator-insulator bonding similar to wafer bonding. Furthermore, in a preferred embodiment, a hybrid “reactive” bonding process is utilized in which insulator surfaces, having a thin reactive metal layer, are placed opposed to one another and then contacted and heated to react the metal layer with the insulator surfaces and thereby bond the opposed components together. Such a metal include, for example, Ti, W, Cr, Mo, etc., or alloys thereof. These metals readily oxidize and form in a preferred embodiment silicides which melt at temperatures of 300° C. or less. The hybrid reactive bonding process of some embodiments of the present invention relies on the reactivity of the thin metal layer with the respective insulators to achieve a bond. In some embodiments of the present invention, the metal layer is preferably thin (e.g., less than 500 Å) such that all of the reactive layer is consumed, or reacts with, the insulating layers. In hybrid reactive bonding, bonding is achieved when the surfaces are brought into contact and then heated such that the metal reacts with one or both insulating surfaces.
Furthermore, friction bonding according some embodiments of the present invention can be used to bond thermoelectric materials and/or superlattice layers to other layers on the thermoelectric device and provide a mechanism for direct attachment of the thermoelectric devices of some embodiments of the present invention to an integrated circuit die or wafer element. Friction bonding can, in some embodiments of the present invention, be implemented with intervening reactive layers. In friction bonding, linear motion over a short distance using an ultrasonic transducer provides the friction necessary to produce heating at the surface that will produce the bond. Heating to a high fraction of the melting temperature and then using a friction bonding technique to produce local heating and thereby for instance melting or plastic deformation at the contact surfaces can produce a suitable bond. Heating from one direction and cooling from another side can be used to locally heat to a small area near the contact surfaces. Small amounts of material or thin sheets of material in a perform cut to die or strip size to match the thermoelectric component parts.
Materials in thin sheets or thin film form may be used, according to some embodiments of the present invention, to provide for a buffer that protects the thermoelectric superlattice materials during the friction bonding. Materials in thin sheets may reduce and/or avoid mechanical damage to the top layers of the thermoelectric materials. The thin layer is selected to form a eutectic that allows friction bonding. In friction bonding, the surfaces of the materials to be bonded can be roughened if necessary to improve the friction and thus the efficacy of forming a friction bond.
Further, diffusion bonding or thermal annealing can be used to bond the thermoelectric devices to a semiconductor device chip.
Bonding can occur between a top header of a thermoelectric devices and a semiconductor device chip by any number of the processes described herein, and can utilize a bonding material to facilitate coupling of the semiconductor device chip to the semiconductor device chip. Regardless of approach, a thermally conductive and mechanically stable connection or bond is preferred between the top header and the semiconductor device chip. Bonding to the semiconductor device chip to the thermoelectric devices of some embodiments of the present invention can be accomplished in the following non-limiting examples by:
Heat flux from the semiconductor device chip can be dissipated from the thermoelectric devices of some embodiments of the present invention by a heat sink operating at a temperature above that of the semiconductor device chip. Moreover, once bonded, the attached thermoelectric devices of some embodiments of the present invention, when not cooling, can sense a heat flux from the chip and thus can provide active sensing of the device chip performance. A template of such thermoelectric devices can therefore, in some embodiments of the present invention, provide a mapping of device component utilization (i.e., those device components having higher utilizations will produce higher amounts of heat flux into the proximate thermoelectric devices).
Thus, as illustrated above, some embodiments of the present invention can utilize a number of approaches using bonding to facilitate thermal transfer by thermal conduction from one thermoelectric power conversion stage to another. Such techniques and other techniques known in the art can be used to appropriately bond the various stages together. These approaches, according to some embodiments of the present invention, realize high-quality thermal interfacing.
Another alternative approach according to some embodiments of the present invention for integrating the various thermoelectric conversion stages utilizes radiant thermal energy transfer using Purcell-enhancement cavity transmitter/receiver structures such as those described in the afore-mentioned U.S. Provisional Application No. 60/253,743, the entire contents of which are incorporated herein by reference, entitled “Spontaneous emission enhanced heat transport method and structures for cooling, sensing, and power generation” for heat transfer from one thermoelectric power conversion stage to another. In this approach, the radiant portion, if not the dominant process, plays a substantial role in managing thermal stress by providing less-rigidly-bonded interfaces.
As shown in
Further, some embodiments of the present invention can utilize Purcell enhancement from an enhanced density of radiative modes in small-scale structures (similar to enhanced electronic density of states in quantum-confined systems) for enhanced spontaneous emission using patterned/μm-size-range, appropriately-spaced, structures for specific temperatures, on the heat spreader. Thus, engineered micro-fins can also potentially enhance spontaneous radiative heat transport. These μm-size geometries are achievable with photolithography and large-area wafers for a cost-effective implementation.
Spontaneous emission enhanced heat transport (SEEHT) may additionally enhance emission at infra-red wavelengths near 300 K. The incorporation of micron or sub-micron size Purcell cavities, will provide for the theoretical maximum radiative emission at peak wavelengths of 10 μm which will enhance heat transport by as much as a factor of 1000 at 300 K, leading to a radiative dissipative flux of φSEEHT of 44 W/cm2. Such micron size particles incorporated by impregnation or self-assembly, followed by overgrowth, permit the scope for radiative heat transfer mechanisms to be considerably enhanced. Such particles can further be incorporated in high-thermal conductivity heat spreader such as SiC, AIN, Si, diamond, etc. Enhancement of such intensities, even compared to highly-emissive (Ti) surfaces, showing both structure dependence and wavelength dependence, is shown in
While not limited to the following theory, some embodiments of the present invention recognize that of enhanced emission with these Purcell cavity structures can be further enhanced/realized if there is matching of “increased density of states” in emitters with “increased density of states” with receivers/absorbers, i.e., resonant thermal energy transfer. In addition to “resonant thermal energy transfer” by Purcell-cavity effects, other “proximity coupling of radiative infrared modes” can be exploited as well, in some embodiments of the present invention. Utilization of radiation coupling will, according to some embodiments of the present invention, reduce thermal stress, by removing (strong) physical interfacial contacts between various stages. Further, the mechanical alignment of the resonant structures may not be a significant issue, given that the typical size of the inverted couple headers are ˜300 μm×300 μm.
For automatic assembly of the modules described above a dicer and pick-and-place tools (standard to the IC industry) can be used. A wafer dicer and robotic pick-and-place tool, provide not only cost-effective but also reliable fabrication of both mini-modules and large-scale modules. The tool is used to dice p-n couple dies from a processed wafer and to assemble these inverted couple dies into a range of devices, from mini-modules to large-array of mini-modules. The dicer and pick-and-place tools, described above can also be used according to some embodiments of the present invention to assemble thin-substrate (i.e., 100 μm to 250 μm thick) bulk modules as well as substrate die containing the afore-mentioned superlattice thin-film structures.
In some embodiments of the present invention, large-scale headers are used, on which a large array of mini-modules are assembled to produce large-scale modules and proportionally larger powers.
An electrical configuration for permitting reduction and/or avoidance of a catastrophic failure is depicted in
Further, the controller 108 being connected to the separate stages can switch the stages from the above-noted power conversion mode and heat pump (i.e., a cooling mode) to a heat flux sensing mode. In a heat sensing mode, the current through the thermoelements are measured as an indicator of the heat flux through the thermoelements coming from a heat source. Such information can be used as a measure of the heat being dissipated from the heat source. The controller can thus process a signal indicative of heat flux from the thermoelectric pair of n-type and p-type thermoelements.
Thus, the controller of some embodiments of the present invention connected electrically to the thermoelectric devices of some embodiments of the present invention can be configured to switch the thermoelectric devices between at least one of a cooling mode, a heat pump mode, a power conversion mode, and a heat flux sensing mode.
Accordingly, integration of thermoelectric devices and thermoelectric device modules of some embodiments of the present invention to electronic devices such as semiconductor chip packages can be accomplished through a number of mechanisms. Thermoelectric devices can be coupled to such devices for the purposes of “hot spot” cooling those parts of the device most susceptible to exceeding operational temperature limits.
Integrated semiconductor devices requiring hot spot cooling include, for example, microprocessors, graphic processors and other power dissipating devices fabricated in silicon, germanium, silicon-germanium, gallium arsenide, or any such semiconductor material. The integration can occur, for example, via recesses in the semiconductor chip and/or in the headers. In this approach, vertical and lateral vias or recesses are fabricated in the semiconductor chip and/or the heat spreader. The above-noted bonding techniques join the semiconductor chip to the heat spreader.
Further, an electrically insulating interlayer 82 can be preferably interposed between the thermoelectric devices and the semiconductor material of the chip. As noted previously, the properties of the electrically insulating interlayer 82 are such to permit electrical isolation without impeding heat flux between the semiconductor device chip 74 and the thermoelectric devices. An electrically insulating material such as Si02 can be suitable for the electrically insulating interlayer 82, although other insulating materials known in the art are likewise applicable. The electrically insulating interlayer 82 is at least applied to the semiconductor chip in regions where the thermoelectric devices are to be attached. Following application, metallized contacts 83 can be made on the electrically insulating interlayer 82 to provide electrical connections to the thermoelectric devices. Metallized contacts can be made using one or more of known metallization techniques such as, for example, but not limited to evaporation, electroplating, or soldering. Following metallization, diffusion bonding, or thermal annealing can be used to bond the thermoelectric devices to the chip.
Bonding occurs between a top header 79 of the thermoelectric devices and the semiconductor device chip 74 by any number of the processes described above, and can utilize a bonding material 80 to facilitate coupling of the semiconductor device chip 74 to the semiconductor device chip 74. Regardless of approach, a thermally conductive and mechanically stable connection or bond is preferred between the top header 79 and the semiconductor device chip 74.
Heat flux from the semiconductor device chip 74 is dissipated from the thermoelectric devices 72 by a heat sink operating at a temperature above that of the semiconductor device chip 74. As such, heat flux from the power dissipating devices 76 is more efficiently dissipated to the outside environment due to the higher temperature differential existing between the temperature of the heat sink and the ambient than the temperature of the semiconductor device chip 74 and the ambient.
Thus, coupling of thermoelectric devices 72 to the semiconductor device chip 74 occurs with or without the utilization of recesses.
Numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, embodiments of the invention may be practiced otherwise than as specifically described therein.
The present application claims the benefit of priority as a continuation-in-part of U.S. application Ser. No. 11/406,100 filed on Apr. 18, 2006 which claims priority as a continuation-in-part of International Application No. PCT/US2004/041431 (designating the United States) filed on Dec. 13, 2004, which claims the benefit of priority from U.S. Provisional Application No. 60/528,479 filed Dec. 11, 2003. U.S. application Ser. No. 11/406,100 also claims the benefit of priority from U.S. Provisional Application No. 60/672,330 filed Apr. 18, 2005. The present application thus claims the benefit of priority from U.S. application Ser. No. 11/406,100; International Application No. PCT/US2004/041431; U.S. Provisional Application No. 60/528,479; and U.S. Provisional Application No. 60/672,330. The disclosures of each of the above referenced U.S. Utility, U.S. Provisional, and International PCT Applications are hereby incorporated herein in their entirety by reference. This application is related to U.S. Provisional Application No. 60/372,139 entitled “Thermoelectric device technology utilizing double-sided Peltier junctions” filed on Apr. 15, 2002, the entire contents of which is incorporated herein by reference. This application is related to U.S. Pat. No. 6,300,150 entitled “Thin-film thermoelectric device and fabrication method of same” issued Oct. 9, 2001, the entire contents of which is incorporated herein by reference. This application is related to U.S. Pat. No. 6,071,351 entitled “Low temperature chemical vapor depositor and etching apparatus and method” issued Jun. 6, 2002, the entire contents of which is incorporated herein by reference. This application is related to U.S. Pat. No. 6,505,468 entitled “Cascade cryogenic thermoelectric cooler for cryogenic and room temperature applications” issued Jan. 14, 2003, the entire contents of which is incorporated herein by reference. This application is also related to U.S. Provisional Application No. 60/253,743 entitled “Spontaneous emission enhanced heat transport method and structures for cooling, sensing, and power generation”, filed Nov. 29, 2000, the entire contents of which is incorporated herein by reference, and subsequently filed as PCT Application No. PCT/US01/44517 filed Nov. 29, 2001. This application is related to U.S. Provisional Application No. 60/428,753, “Three-Thermal-Terminal (T3) Trans-Thermoelectric Device”, filed Nov. 25, 2002, the entire contents of which is incorporated herein by reference.
The U.S. Government, by the following contracts, may have a paid-up license in this invention and the right in limited circumstances to require the patent owner to license others on reasonable terms, as provided for by the terms in High-Performance Thin-film Thermoelectric Devices for Cooling and Power Generation, DARPA/ONR Contract No. N00014-97-C-0211, Thin-film Thermoelectric Palm Power Technologies, DARPA/ARO Contract No. DAAD 19-01-C-0070, and Meta-Material Structures for Super-Radiant Structures, DARPAJAFOSR Contract No. F49620-01-C-0038.
| Number | Date | Country | |
|---|---|---|---|
| 60528479 | Dec 2003 | US | |
| 60672330 | Apr 2005 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 11406100 | Apr 2006 | US |
| Child | 11641563 | US | |
| Parent | PCT/US04/41431 | Dec 2004 | US |
| Child | 11406100 | US |
