Patent Application
20140362059
The present application claims priority from Japanese application JP2013-121494 filed on Jun. 10, 2013, the content of which is hereby incorporated by reference into this application.
1. Field of the Invention
The present invention relates to a thin film transistor and a display device using the same, and more particularly to a thin film transistor using oxide semiconductor for a semiconductor layer in which a channel region is formed.
2. Description of the Related Art
In thin film transistors using oxide semiconductor for a semiconductor layer (hereinafter referred to as oxide thin film transistors), it has been known that a favorable thin film transistor with high mobility can be formed by a process substantially equal to that of a thin film transistor using amorphous silicon or the like for a semiconductor layer. Especially in the oxide thin film transistors in which a semiconductor layer is formed of oxide semiconductor, a so-called bottom-gate type thin film transistor is common in which an oxide semiconductor layer is formed above a gate electrode layer formed on a top surface of an insulating substrate and a source electrode layer and a drain electrode layer (source/drain electrode layer) are formed on a top surface of the oxide semiconductor layer. In the oxide thin film transistor having this configuration, it has been known that an oxide thin film transistor with high mobility and high reliability is formed by forming an insulating film serving as a channel protective layer on the top surface of the oxide semiconductor layer, that is, on a surface thereof on the side where the source/drain electrode layer is formed.
In the formation of a related-art oxide thin film transistor, an oxide semiconductor layer is formed, and then, an insulating film covering a top surface of an insulating substrate is formed so as to also cover the oxide semiconductor layer. Next, through-holes (contact holes) are formed in the insulating film, so that source/drain electrode layer formed on the top surface of the insulating film is electrically connected with the oxide semiconductor layer via the through-holes. In this case, the insulating film formed in a region between the source electrode layer and the drain electrode layer serves as a channel protective layer. Moreover, the length of the through-hole in a channel width direction via which the source electrode layer and the oxide semiconductor layer are connected and the through-hole via which the drain electrode layer and the oxide semiconductor layer are connected, that is, the opening width of the pair of through-holes in the channel width direction is a substantial channel width.
The present inventors have formed a gate scanning circuit of a liquid crystal display device using oxide thin film transistors on a glass substrate. On the other hand, for the individual oxide thin film transistors constituting the gate scanning circuit, a channel width needs to be changed according to an operating capability needed for each of the oxide thin film transistors. However, the present inventors have found a problem in the related-art oxide thin film transistor having the structure described above that when the channel width of the oxide thin film transistor, that is, the opening width of the through-hole in the channel.0 width direction is changed according to an operating capability, the threshold voltage is shifted in the negative direction as the channel width is increased. That is, the present inventors have found a problem that when a gate scanning circuit, a selector circuit, or the like configured using oxide thin film transistors having different channel widths is to be prepared, the circuit does not normally operate because the oxide thin film transistors having different channel widths have different threshold voltages.
On the other hand, JP 2008-034819 A (Patent Document 1) discloses a semiconductor device in which contact holes whose diameters are different between a source region and a drain region are formed in each thin film transistor (TFT) forming a memory cell in a ROM. In the semiconductor device disclosed in Patent Document 1, the contact holes are formed such that the sum of bottom areas of the contact holes formed on the source region side is the same as that of the contact holes formed on the drain region side, and a gate electrode layer and a drain electrode layer are electrically connected with a semiconductor layer (island-like semiconductor film) via the contact holes.
Moreover, JP 2000-357735 A (Patent Document 2) discloses a semiconductor device in which a semiconductor layer made of polysilicon (p-Si) is formed on a substrate composed of an amorphous silicon (a-Si) film and the number of contact holes is reduced to provide a closest packing arrangement. In the semiconductor device disclosed in Patent Document 2, one edge of a gate electrode is extended to the source electrode side of the semiconductor layer, a contact hole through which the surfaces of the gate electrode and the semiconductor layer are exposed is formed, and a source electrode connected to both the semiconductor layer and the gate electrode via the contact hole is formed.
However, even when the structure disclosed in FIG. 7 of Patent Document 1 is applied to an oxide thin film transistor, the sums of bottom areas of the contact holes different in diameter between the source region and the drain region need to be the same. That is, even when a gate scanning circuit is configured using the technique disclosed in Patent Document 1, the channel width of thin film transistors constituting the gate scanning circuit needs to be changed according to an operating capability needed for each of the thin film transistors. Accordingly, even when the technique disclosed in Patent Document 1 is used, the sum of bottom areas of the contact holes needs to be set to a bottom area suitable for a needed drive capability of the thin film transistor. Therefore, a gate scanning circuit needs to be formed of thin film transistors having different channel widths, that is, thin film transistors having different threshold voltages, giving rise to a fear that the circuit does not normally operate.
On the other hand, Patent Document 2 discloses a technique in which a data-side driver circuit and a scanning-side driver circuit are formed in a region outside the display area, a so-called picture-frame region. However, it is a technique of reducing the number of contact holes to provide a closest packing arrangement, in which no consideration is taken to a change in threshold voltage associated with the difference in the channel width of the thin film transistor.
The invention has been made in view of the problems, and it is an object of the invention to provide a technique by which it is possible to suppress fluctuations in threshold voltage in oxide thin film transistors having different channel widths and formed on the same insulating substrate.
(1) To solve the problems, a thin film transistor according to an aspect of the invention includes: an oxide semiconductor layer that is formed above a gate electrode layer via a first insulating film; and a drain electrode layer and a source electrode layer that are formed above the oxide semiconductor layer via a second insulating film, wherein the drain electrode layer and the source electrode layer are electrically connected with the oxide semiconductor layer via through-holes formed in the second insulating film arranged between the drain and source electrode layers and the oxide semiconductor layer, the drain electrode layer and the source electrode layer are formed over opposite edge portions of the oxide semiconductor layer, a channel region is formed in a region of the oxide semiconductor layer between the drain electrode layer and the source electrode layer that are electrically connected with the oxide semiconductor layer via the through-holes, a first through-hole that electrically connects the drain electrode layer with the oxide semiconductor layer and a second through-hole that electrically connects the source electrode layer with the oxide semiconductor layer each include two or more through-holes that are arranged in parallel in a channel width direction of the thin film transistor, and a total width of opening widths of the first through-holes or the second through-holes in the channel width direction is a channel width of the thin film transistor.
(2) To solve the problems, a display device according to an aspect of the invention includes a first substrate, the first substrate including, formed thereon, scanning signal lines that extend in an X-direction and are arranged in parallel in a Y-direction and to which a scanning signal is input, video signal lines that extend in the Y-direction and are arranged in parallel in the X-direction and to which a video signal is input, switching thin film transistors each of which is arranged in the vicinity of an intersection between the scanning signal line and the video signal line and controls reading of the video signal in synchronization with the scanning signal, and a driver circuit that generates the scanning signal or/and the video signal, wherein at least the driver circuit is formed of the thin film transistor according to (1), and the thin film transistor includes two or more thin film transistors in which at least the numbers of the first through-holes are different from each other and whose drive capabilities are different from each other.
According to the invention, it is possible to suppress fluctuations in threshold voltage in oxide thin film transistors having different channel widths and formed on the same insulating substrate.
Other advantageous effects of the invention will be apparent from the description of the entire specification.
Hereinafter, embodiments to which the invention is applied will be described with reference to the drawings. In the following description, the same constituent elements are denoted by the same reference and numeral signs, and the repetitive description thereof is omitted. Moreover, X, Y, and Z shown in the drawings indicate an X-axis, a Y-axis, and a Z-axis, respectively.
As shown in
The oxide semiconductor layer OS, which is island-like, is formed on a top surface of the gate insulating film GI so as to overlap the gate electrode layer GT. The oxide semiconductor layer OS is an In—Ga—Zn—O-based oxide semiconductor including, as main components, elements of indium, gallium, zinc, and oxygen, which is referred to also as IGZO film. In addition to the In—Ga—Zn—O-based oxide semiconductor, In—Al—Zn—O-based, In—Sn—Zn—O-based, In—Zn—O-based, In—Sn—O-based, Zn—O-based, or Sn—O-based oxide semiconductor may be used. It is preferred that the oxide semiconductor layer OS has a film thickness within a range of from 30 nm to 500 nm. However, the film thickness is appropriately adjusted in accordance with purposes such as increasing the film thickness when used for a device that needs a large amount of current.
A channel protective layer (second insulating film) CH that is composed of a silicon oxide film as a well-known insulating film material and covers a top surface of the insulating substrate (not shown), that is, the top surface of the gate insulating film GI is formed on a top surface of the oxide semiconductor layer OS so as to also cover the oxide semiconductor layer OS. A pair of through-holes (contact holes or holes) TH1 and TH2 that reach the surface of the oxide semiconductor layer OS are formed in the channel protective layer CH at portions arranged on the oxide semiconductor layer OS (an overlapped region portion where the channel protective layer CH overlaps the oxide semiconductor layer OS). The pair of through-holes TH1 and TH2 are formed along a side portion of the overlapped region.
In the first through-hole TH1 as one of the through-holes (through-hole on the left side in
In this case, some oxide semiconductors provide an ohmic contact even when a conductive film such as a metal thin film is formed on the surface of the oxide semiconductor, while others need a well-known contact layer for realizing an ohmic contact similarly to silicon semiconductor. Accordingly, when the oxide semiconductor layer OS is formed of the oxide semiconductor that does not need a contact layer, the oxide semiconductor layer OS exposed through the first and second through-holes TH1 and TH2 serves as contact regions relative to the drain electrode layer DT and the source electrode layer ST. On the other hand, when the oxide semiconductor layer OS is formed of the oxide semiconductor that needs a contact layer, the contact layer is formed using a well-known technique. Due to this, similarly to the case where the oxide semiconductor layer OS is formed of the oxide semiconductor that does not need a contact layer, the regions of the oxide semiconductor layer OS exposed through the first and second through-holes TH1 and TH2 serve as the contact regions relative to the drain electrode layer DT and the source electrode layer ST. By adopting the configuration described above, the contact regions (not shown) corresponding to the first and second through-holes TH1 and TH2 are formed in the oxide semiconductor layer OS. With this configuration, the drain electrode layer DT and the source electrode layer ST are electrically connected with the oxide semiconductor layer OS via the first through-hole TH1 and the second through-hole TH2, respectively. The drain electrode layer DT, the source electrode layer ST, and the gate electrode layer GT of the oxide thin film transistor TFT of Embodiment 1 are formed of an element selected from aluminum, molybdenum, chromium, copper, tungsten, titanium, zirconium, tantalum, silver, and manganese, or an alloy combining these elements. Moreover, a stacked structure obtained by stacking aluminum on titanium or interposing aluminum between upper and lower titanium layers may be adopted.
A protecting insulating film serving as a passivation layer PAS and composed of a well-known inorganic material is formed on the drain electrode layer DT and the source electrode layer ST so as to cover the insulating substrate (not shown), that is, the channel protective layer CH and also cover the drain electrode layer DT and the source electrode layer ST. The passivation layer PAS is formed of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The passivation layer PAS may have a stacked structure, which may be obtained by combining any of the insulating films described above with one another.
Especially in the oxide thin film transistor of Embodiment 1, as is apparent from
In this case, the same oxide semiconductor layer OS is exposed through the three first through-holes TH1 and the three second through-holes TH2, and the same drain electrode layer DT is electrically connected to the same oxide semiconductor layer OS via each of the three first through-holes TH1. Similarly, the source electrode layer ST is electrically connected to the same oxide semiconductor layer OS via each of the three second through-holes TH2. Further, the gate electrode layer GT formed below the oxide semiconductor layer OS and the oxide semiconductor layer OS are formed so as to overlap each other in a plan view via the gate insulating layer GI.
Accordingly, in the configuration of Embodiment 1, an oxide thin film transistor (unit thin film transistor) TU1 is formed in which the drain electrode layer DT and the source electrode layer ST that are connected to the oxide semiconductor layer OS via the first through-hole TH1 and the second through-hole TH2 on the upper stage in
In the three unit thin film transistors TU1 to TU3, in this case, since the drain electrode layer DT, the source electrode layer ST, and the gate electrode layer GT are formed of the same conductive thin film, the first to third unit thin film transistors TU1 to TU3 are connected in parallel. That is, one oxide thin film transistor TFT of Embodiment 1 is formed of the three unit thin film transistors TU1 to TU3 connected in parallel. In this case, the unit thin film transistors TU1 to TU3 are configured using, as a basic unit, the first through-hole TH1 and the second through-hole TH2 as a pair of through-holes that are formed in the channel protective layer CH for electrically connecting the drain electrode layer DT and the source electrode layer ST to the oxide semiconductor layer OS. Therefore, a channel region of each of the unit thin film transistors TU1 to TU3 is formed in the oxide semiconductor layer OS in a region between the pair of first through-hole TH1 and second through-hole TH2 indicated by the dash-dotted lines in
As described above, in the configuration of the oxide thin film transistor TFT of Embodiment 1, one oxide thin film transistor TFT is formed of the three unit thin film transistors TU1 to TU3 arranged in parallel in the Y-direction and indicated by the dashed lines in
With the configuration described above, the unit thin film transistors TU1 to TU3 constituting the oxide thin film transistor TFT of Embodiment 1 have substantially the same channel length and the same channel width, and the unit thin film transistors TU1 to TU3 also have substantially the same electrical characteristics. In the configuration of the oxide thin film transistor TFT of Embodiment 1, a direction connecting the pair of first through-hole TH1 and second through-hole TH2 together (a channel length direction or the X-direction) is orthogonal to a direction in which the first through-holes TH1 and the second through-holes TH2 are arranged in parallel (a channel width direction or the Y-direction) so that the unit thin film transistors TU1 to TU3 have substantially the same characteristics. However, the invention is not limited to this configuration.
In
The oxide thin film transistor TFT shown in
Therefore, in the oxide thin film transistor TFT of Embodiment 1 shown in
Accordingly, as is apparent from the line G1 shown in
In the above-described configuration of the oxide thin film transistor shown in
As described above, the unit thin film transistors TU are combined in parallel, so that even when a gate scanning circuit, a selector circuit, or the like is formed using a plurality of oxide thin film transistors TFT having different drive capabilities and different sizes on the same insulating substrate as that of a pixel electrode or the like, fluctuations in threshold voltage can be suppressed to realize favorable switching.
However, for the opening widths W1 to Wn of the first through-holes TH1 and the second through-holes TH2 of the unit thin film transistors TU1 to TUn, there is, for example, the following method. The opening width W1 is determined according to the minimum operating capability (drive capability) for the oxide thin film transistor TFT when constituting a gate scanning circuit, a selector circuit, or the like. Next, for the oxide thin film transistor TFT that needs the minimum operating capability, the oxide thin film transistor TFT is formed of a single unit thin film transistor TU. Other oxide thin film transistors TFT that need a greater drive capability is appropriately formed of a plurality of unit thin film transistors TU according to the needed drive capability. In this case, in addition to the advantageous effect described above, it is possible to suppress an increase in the occupied area of the oxide thin film transistor TFT associated with configuring a driver circuit such as a gate scanning circuit or a selector circuit using the oxide thin film transistor TFT of Embodiment 1.
Moreover, the oxide thin film transistor TFT that needs the minimum operating capability may be formed of two or more plurality of unit thin film transistors TU. With this configuration, the number of unit thin film transistors TU that determine the drive capability of the oxide thin film transistor TFT, that is, an increment or decrement of the channel width W can be made small. As a result, when the other oxide thin film transistors TFT are formed, it is possible to obtain a special advantageous effect that the oxide thin film transistor TFT having a drive capability closer to the needed drive capability can be formed. The reason is as follows. Especially in the configuration of Embodiment 1, since one thin film transistor TFT is formed of the n unit thin film transistors TU1 to TUn connected in parallel, the opening width of the oxide thin film transistor TFT has a discrete value corresponding to the number of unit thin film transistors TU. Accordingly, in the configuration of Embodiment 1, the drive capabilities of a plurality of oxide thin film transistors TFT formed on the same insulating substrate are properly grasped, and the unit thin film transistors TU are formed corresponding to the drive capabilities. Therefore, it is possible to suppress an increase in the occupied area of the transistor element associated with the use of the oxide thin film transistor TFT of Embodiment 1.
Moreover, in the oxide thin film transistor TFT of Embodiment 1, the oxide semiconductor layer OS can be used for a semiconductor layer. Therefore, it becomes easy to improve reliability and realize high mobility as the characteristics of the oxide thin film transistor TFT. That is, it is possible to form a thin film transistor having a great drive capability even with the same occupied area as that of an amorphous silicon thin film transistor. Moreover, when a circuit is formed using the oxide thin film transistor TFT of Embodiment 1, it is also possible to obtain an advantageous effect that a circuit area can be made smaller than that of an amorphous silicon thin film transistor.
The oxide thin film transistor TFT of Embodiment 1 has a bottom-gate type transistor structure, but the invention is not limited to a bottom-gate type oxide thin film transistor. The invention can also be applied to an oxide thin film transistor having another structure such as a top-gate type. Further, the invention can also be applied to an oxide thin film transistor having a structure in which the source electrode layer ST and the drain electrode layer DT are arranged on the side below the oxide semiconductor layer OS, that is, on the insulating substrate side.
The curves G2 in
As is apparent from
In contrast to this, as is apparent from
As is especially apparent from the line G4 shown in
On the other hand, as is apparent from the line G5 shown in
As is apparent from the description and the like described above, the on-current Ion apparently increases in proportion to the number of unit thin film transistors TU, that is, to the channel width W in the following cases: where the oxide thin film transistor TFT is formed of only one unit thin film transistor TU1 having the channel width W1=3 μm (when W=3 μm); where one oxide thin film transistor TFT is formed of two unit thin film transistors TU1 and TU2 having the channel width W1=W2=3 μm (when W=6 μm); and where one oxide thin film transistor TFT is formed of three unit thin film transistors TU1, TU2, and TU3 having the channel width W1=W2=W3=3 μm (when W=9 μm).
In this case, as shown in
From the facts described above, it is found that the first and second through-holes TH1 and TH2 adjacent to each other need to be formed with a certain gap on both sides (in the adjacent direction of the unit thin film transistors TU1 to TU3) of the first and second through-holes TH1 and TH2. That is, the contact region as a region where the drain electrode layer DT or the source electrode layer ST is connected with the oxide semiconductor layer OS needs to be arranged with a certain gap.
As a result of investigation of the size of this gap, it is found that when each gap (adjacent gap) H1 between the adjacent first through-holes TH 1 and between the adjacent second through-holes TH2 shown in
Accordingly, when the length (opening width) W1 of the first through-hole TH1 and the second through-hole TH2 in the channel width direction is 3 μm, it is preferable to form a gap of 1 μm or more on both sides of each of the unit thin film transistors TU1 to TU3 (both sides of each of the first through-holes TH1 arranged adjacent to each other and each of the second through-holes TH2 arranged adjacent to each other), that is, to set the adjacent gap H1 in the Y-direction (channel width direction) to be 2 μm or more.
First, a metal conductive film such as a molybdenum film or an aluminum film is deposited on the surface of the first substrate SUB1 as a glass substrate by, for example, a well-known sputtering method or the like. Subsequently, a photosensitive resin film (not shown) is applied on the metal conductive film, and then, the photosensitive resin film is developed and patterned to form a resist pattern. Thereafter, the metal conductive film exposed through the resist pattern is removed by wet etching or dry etching, and then, the resist pattern is peeled off, so that a gate electrode GT is formed. The gate electrode GT is directly formed on the surface of the first substrate SUB1 composed of a glass substrate. However, for preventing the mixing of alkali ions or the like from the first substrate SUB1, a so-called under film composed of a well-known silicon nitride film or the like may be formed on the first substrate SUB1, and the gate electrode GT may be formed on a surface (upper layer) of the under film. Moreover, instead of a glass substrate, a well-known flexible substrate capable of withstanding a heating step of the oxide thin film transistor TFT may be used as the first substrate SUB1.
Next, the gate insulating film GI composed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like is deposited on the first substrate SUB1 on which the gate electrode GT is formed, so as to cover the surface of the first substrate SUB1 and the gate electrode layer GT by a well-known plasma CVD (Chemical Vapor Deposition) method or the like.
An oxide semiconductor thin film such as an In—Ga—Zn—O-based, In—Al—Zn—O-based, In—Sn—Zn—O-based, In—Zn—O-based, In—Sn—O-based, Zn—O-based, or Sn—O-based oxide semiconductor thin film is deposited above the first substrate SUB1 on which the gate insulating film GI is formed, that is, on a surface of the gate insulating film GI formed in the previous step, by a well-known sputtering method or the like. Subsequently, a well-known photosensitive resin film is applied on the oxide semiconductor thin film, and then, the photosensitive resin film is developed and patterned to form a resist pattern. Thereafter, the oxide semiconductor exposed through the resist pattern is removed by well-known wet etching or the like, and then, the resist pattern is peeled off, so that the island-like oxide semiconductor layer OS is formed. Moreover, by subjecting the oxide semiconductor layer OS to well-known plasma treatment using oxygen or nitrous oxide, the oxide semiconductor layer OS with few oxygen defects can be formed.
First, a silicon oxide film is deposited above the first substrate SUB1 above which the oxide semiconductor layer OS is formed, so as to cover the surface of the gate insulating film GI and the oxide semiconductor layer OS by a well-known plasma CVD method or the like to form the channel protective layer CH (
Next, a well-known photosensitive resin film is applied on the channel protective layer CH, and then, the photosensitive resin film is developed and patterned to form a resist pattern. Thereafter, the channel protective layer CH exposed through the resist pattern is removed by well-known dry etching, so that the surface of the oxide semiconductor layer OS is exposed. In this step, the first and second through-holes (contact holes) TH1 and TH2 that electrically connect the oxide semiconductor layer OS with the source electrode layer ST and the drain electrode layer DT (provide contact between the oxide semiconductor layer OS and the source and drain electrode layers ST and DT) via the channel protective layer CH are formed in the channel protective layer CH (
A metal conductive film such as a molybdenum film or an aluminum film is deposited above the first substrate SUB1 by a well-known sputtering method. Due to this, the metal conductive film is formed so as to cover the surface of the channel protective layer CH, the first and second through-holes TH1 and TH2 formed in the channel protective layer CH, and the oxide semiconductor layer OS. Subsequently, a well-known photosensitive resin film is applied on the metal conductive film, and then, the photosensitive resin film is developed and patterned to form a resist pattern. Thereafter, the metal conductive film exposed through the resist pattern is removed by well-known wet etching or dry etching, and then, the resist pattern is peeled off, so that the source electrode layer ST and the drain electrode layer DT are formed. The conductive film for forming the source electrode layer ST and the drain electrode layer DT is not limited to a metal conductive film. Other conductive thin films such as a transparent conductive film may be used.
An insulating film such as a well-known silicon oxide film, silicon nitride film, or silicon oxynitride film is deposited above the first substrate SUB1 above which the source electrode layer ST and the drain electrode layer DT are formed, so as to cover the surface of the channel protective layer CH, the source electrode layer ST, and the drain electrode layer DT by a well-known plasma CVD method or the like to form the passivation layer PAS. Thereafter, although not shown in the drawing, through-holes (contact holes) to the source electrode and the drain electrode are formed in the passivation layer PAS. Due to this, the oxide thin film transistor TFT of Embodiment 1 is formed.
As described above, in the method for manufacturing the oxide thin film transistor TFT of Embodiment 1, the oxide thin film transistor TFT can be manufactured by manufacturing steps similar to those of a related-art thin film transistor in which a semiconductor layer is formed of amorphous silicon (amorphous silicon thin film transistor). Accordingly, the oxide thin film transistor TFT can be manufactured at a production efficiency similar to that of the related-art amorphous silicon thin film transistor, so that it is possible to suppress an increase in production cost associated with the formation of the oxide thin film transistor TFT.
As has been described above, the oxide thin film transistor TFT of Embodiment 1 is formed as follows. The channel protective layer CH is formed on one oxide semiconductor layer OS that overlaps one gate electrode layer GT, and the plurality of first and second through-holes TH1 and TH2 that reach the oxide semiconductor layer OS are formed in the channel protective layer CH. With the use of one first electrode layer (the drain electrode layer DT) that is connected to the oxide semiconductor layer OS via the plurality of first through-holes TH1 and one second electrode layer (the source electrode layer ST) that is connected to the oxide semiconductor layer OS via the second through-holes TH2, one oxide thin film transistor TFT that is formed of the plurality of unit thin film transistors TU connected in parallel and whose channel width is the opening widths of the first and second through-holes TH1 and TH2 in the parallel arrangement direction thereof is formed.
Accordingly, the channel width W that is needed when forming the oxide thin film transistor TFT having a needed drive capability can by formed using the total channel width W of the plurality of unit thin film transistors TU that form one oxide thin film transistor TFT. Therefore, it is possible to suppress fluctuations in the threshold voltage Vth in the oxide thin film transistor TFT caused by the size of the channel width W, so that even when a circuit is configured using a plurality of oxide thin film transistors TFT having different channel widths, the circuit can normally operate.
That is, as has been described above in the section of “advantageous effect”, the total width W=W1+W2+ . . . +Wn, which is the sum of the channel widths W1, W2, . . . , and Wn of the unit thin film transistors TU that form one thin film transistor TFT, is the substantial channel width W of the oxide thin film transistor TFT of Embodiment 1. Accordingly, in the oxide thin film transistor TFT of Embodiment 1 having the channel width W, a drive capability corresponding to the channel width W is provided, and one oxide thin film transistor is formed of the n unit thin film transistors TU. As a result, even when a circuit is configured using a mix of an oxide thin film transistor TFT that needs a great drive capability and a thin film transistor TFT of a relatively low drive capability, the threshold voltage Vth of each of the oxide thin film transistors TFT can be made substantially constant, and therefore, a circuit can normally operate.
In the oxide thin film transistor TFT of Embodiment 1, a case has been described in which the first and second through-holes TH1 and TH2 are square. However, as shown in
As is apparent from
That is, in the configuration of the unit thin film transistors TU1 to TUn of Embodiment 2, the opening width of the first through-hole TH1 and the second through-hole TH2 that are formed in the channel protective layer CH is different in size between the Y-direction (channel width direction) and the X-direction (channel length direction). Also in the oxide thin film transistor TFT of Embodiment 2 having this configuration, as is apparent from
Further, the oxide thin film transistor TFT of Embodiment 2 is formed of the unit thin film transistors TU1 to TUn in which the opening widths (corresponding to the channel widths) W1 to Wn of the first through-holes TH1 and the second through-holes TH2 are larger than those of the unit thin film transistors TU that form the oxide thin film transistor of Embodiment 1. Accordingly, the amount of current that one unit thin film transistor TU can flow can be increased, so that the oxide thin film transistor TFT having the same drive capability can be formed of a smaller number of unit thin film transistors TU than the number of those in Embodiment 1. As a result, a region formed between adjacent unit thin film transistors TU can be reduced. Especially when, for example, a larger amount of current needs to be obtained, it is possible to obtain a special advantageous effect that the size of the oxide thin film transistor TFT can be reduced.
However, as shown in the section of “advantageous effect” of Embodiment 1 described above, when the channel width of an oxide thin film transistor is increased, the threshold voltage Vth is shifted in the negative direction. On the other hand, for enhancing the drive capability to obtain a large amount of current and making the transistor size of the oxide thin film transistor TFT as small as possible, the channel widths W1 to Wn of the unit thin film transistors TU1 to TUn are preferably formed large. As to the effect of preventing the shift of the threshold voltage Vth in the negative direction, the configuration shown in Embodiment 1 described above exhibits a greater effect.
Accordingly, in the following description, the opening width of the first through-hole TH1 and the second through-hole TH2 in the Y-direction (channel width direction) within a range that the shift of the threshold voltage Vth can be allowed will be described in detail.
First, a case will be described in which in the oxide thin film transistor TFT of Embodiment 2 shown in
The adjacent gap H1 in the Y-direction between the adjacent first through-holes TH1 and between the adjacent second through-holes TH2 is 3 μm. A length H2 from an opening edge (upper opening edge in
As is apparent from
As is apparent from
Each of the adjacent gaps between the first through-holes TH1 and between the second through-holes TH2 described above or the minimum length from the first through-hole TH1 and the second through-hole TH2 to the electrode edge is set to be 3 μm. However, even when the gap or length is 4 μm, the tendency of the result does not change. Moreover, the sum W of opening widths of the first through-holes TH1 and the second through-holes TH2 in the channel width direction is not limited to 50 μm. Even when W=100 μm, 200 μm, or the like, the tendency of the result does not change.
On the other hand, the adjacent gap H1 between the unit thin film transistors TU, which causes the shift of the threshold voltage Vth in the negative direction, depends also on the opening widths W1 to Wn of the first and second through-holes TH1 and TH2. That is, for obtaining a favorable threshold voltage Vth when each of the opening widths W1 to Wn of the first and second through-holes TH1 and TH2 is as large (long) as 10 μm, the gap needs to be provided such that the adjacent gap H1 is at least 3 μm or more. That is, a gap of 1.5 μm or more is preferably provided on both sides of each of the first through-hole TH1 and the second through-hole TH2 in the adjacent direction.
However, when the gap between the adjacent unit thin film transistors TU is widened, the transistor size of the oxide thin film transistor TFT is increased. Accordingly, it is sufficient that each of the adjacent gaps H1 between the first through-holes TH1 and between the second through-holes TH2 that form the adjacent unit thin film transistors TU is 4 μm at most.
As a result, as shown in
H1=W1/7+1.57 μm Expression 1
H1=4 μm Expression 2
W1=10 μm Expression 3
W1=4 μm Expression 4
In the oxide thin film transistor TFT of Embodiment 2, a case has been described in which the first and second through-holes TH1 and TH2 are rectangular. However, as shown in
As is apparent from
In the oxide thin film transistor TFT of Embodiment 3 having this configuration, as shown in
In this case, in the configuration of Embodiment 3, a group of the unit thin film transistors TU1 to TU3 that are arranged in parallel in the channel width direction of the oxide thin film transistor TFT and a group of the unit thin film transistors TU4 to TU6 that are arranged in parallel in the channel width direction are arranged in parallel in the channel length direction. That is, the plurality of unit thin film transistors TU1 to TU6 that form one oxide thin film transistor TFT are arranged in an in-plane direction (the X-direction and the Y-direction) of the insulating substrate (not shown). Accordingly, it is possible to obtain a special advantageous effect that the outer shape of the oxide thin film transistor TFT can be easily conformed to the shape of a forming region.
Especially in the configuration of the oxide thin film transistor TFT of Embodiment 3, the first through-hole TH1 (contact region) for electrically connecting the drain electrode layer DT with the oxide semiconductor layer OS is commonly used between the unit thin film transistor TU1 and the unit thin film transistor TU4 that are arranged in parallel in the channel length direction, between the unit thin film transistor TU2 and the unit thin film transistor TU5 that are arranged in parallel in the channel length direction, and between the unit thin film transistor TU3 and the unit thin film transistor TU6 that are arranged in parallel in the channel length direction. As a result, even when the unit thin film transistors TU are arranged in parallel in the channel length direction, an increase in transistor size can be minimized in the channel length direction.
In the configuration of the oxide thin film transistor TFT of Embodiment 3, three unit thin film transistors TU are arranged in parallel in the Y-direction. However, it is sufficient that one or more unit thin film transistors are provided. Moreover, the number of unit thin film transistors TU arranged in parallel in the X-direction is not limited to two shown in
Also in the oxide thin film transistor TFT of Embodiment 3, even when corners of the first to third through-holes TH1 to TH3 are rounded, the advantageous effects described above can be obtained similarly to Embodiment 1 and Embodiment 2.
In the following description, a case will be described in which the thin film transistor of the invention is applied to an IPS type liquid crystal display device. However, the thin film transistor of the invention can also be applied in the same manner to a liquid crystal display device of other types such as a TN type or a VA type.
As shown in
Scanning signal lines (gate lines) (not shown) extending in the X-direction and arranged in parallel in the Y-direction and video signal lines (drain lines) (not shown) extending in the Y-direction and arranged in parallel in the X-direction are formed on a liquid crystal surface side of the first substrate SUB1. A pixel region is formed in each of regions surrounded by the scanning signal lines and the video signal lines. Pixels are arranged in a matrix in a display area AR. In each of the pixels, the above-described oxide thin film transistor for switching and a pixel electrode (not shown) are formed on the first substrate SUB1. Similarly to a related-art liquid crystal display device, the switching oxide thin film transistor is turned on or off in synchronization with a scanning signal input from the gate line, while a video signal from the drain line DL is output to the pixel electrode.
In the display device of Embodiment 4, a scanning signal line driver circuit (gate line driver circuit) GDR and a video signal line driver circuit (drain line driver circuit) DDR are formed in a so-called picture-frame region as a region between the edge of the first substrate SUB1 and the display area AR. The gate line driver circuit GDR generates a scanning signal based on an external control signal and outputs the scanning signal to the gate line. The drain line driver circuit DDR generates a video signal and outputs the video signal to the drain line. In this case, in the display device of Embodiment 4, the gate line driver circuit GDR and the drain line driver circuit DDR are composed of the above-described oxide thin film transistors formed on the first substrate SUB1 as a transparent insulating substrate.
Accordingly, it becomes possible to prevent fluctuations in threshold voltage in the oxide thin film transistors constituting the gate line driver circuit GDR and the drain line driver circuit DDR, which eliminates the need for a circuit or the like for compensating the fluctuations in the threshold voltage. Therefore, the picture-frame region can be narrowed. That is, even when the glass substrate having the same outer shape is used, the display area AR can be widened. Moreover, since the management of the threshold voltage of the thin film transistors constituting the gate line driver circuit GDR and the drain line driver circuit DDR can be made easy or unnecessary, product variations in display device can be suppressed low. Therefore, the reliability of the display device of Embodiment 4 can be improved.
As described above, the method for manufacturing the oxide thin film transistor of the invention is similar to that of a related-art amorphous silicon thin film transistor. Accordingly, the display device of Embodiment 4, which is a display device using the oxide thin film transistor of the invention, can be manufactured by a manufacturing method similar to that of a related-art display device using an amorphous silicon thin film transistor. Therefore, it is possible to obtain a special advantageous effect that the display device using the oxide thin film transistor can be manufactured without greatly changing the manufacturing steps of the display device. Moreover, since the display device of Embodiment 4 can be manufactured by the manufacturing method similar to that of the related-art display device using an amorphous silicon thin film transistor, it is possible to obtain a special advantageous effect that the display device using the oxide thin film transistor can be manufactured at a production efficiency similar to that of the related-art display device using an amorphous silicon thin film transistor.
Further, since the switching thin film transistor for a pixel is formed of an oxide thin film transistor with high mobility, the occupied area of the oxide thin film transistor occupying the pixel region can be reduced, and also the aperture ratio can be improved.
Still further, since the gate line driver circuit GDR and the drain line driver circuit DDR are also formed of oxide thin film transistors, it become easy to improve the reliability of the liquid crystal display device and realize high mobility. That is, a thin film transistor having a great drive capability can be formed even with the same occupied area as that of an amorphous silicon thin film transistor. Accordingly, when a driver circuit or the like is formed using the oxide thin film transistor TFT of Embodiment 1, it is possible to obtain an advantageous effect that the area for forming the driver circuit can be reduced.
Further, a circuit for compensating the shift of the threshold voltage Vth, which is needed when using a related-art oxide thin film transistor, can be made unnecessary. Accordingly, it is possible to obtain a special advantageous effect that the driver circuit area can be reduced and power consumption can also be reduced.
In the display device of Embodiment 4, the gate line driver circuit GDR and the drain line driver circuit DDR are formed in different side portions of the first substrate SUB1. However, the gate line driver circuit GDR and the drain line driver circuit DDR may be formed in the same side portion.
While there have been described what are at present considered to be certain embodiments of the invention, it will be understood that various modifications may be made thereto, and it is intended that the appended claim cover all such modifications as fall within the true spirit and scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2013-121494 | Jun 2013 | JP | national |
