Claims
- 1. A process for manufacturing a thin film transistor comprising the steps of:depositing a semiconductor layer on a substrate by using a plasma CVD method; depositing a first gate dielectric layer consecutively to the step of depositing said semiconductor layer by using the plasma CVD method; patterning said semiconductor layer together with said first gate dielectric layer into an island shape; depositing a second gate dielectric layer to cover said first gate dielectric layer patterned into the island shape; depositing a conductive layer over said second gate dielectric layer; and patterning said conductive layer to form a gate electrode.
- 2. The process according to claim 1, further comprising:etching said second gate dielectric layer using said gate electrode as a mask.
- 3. The process according to claim 1, further comprising:doping said semiconductor layer with an impurity ion using said gate electrode as a mask.
- 4. The process according to claim 2, further comprising:doping said semiconductor layer with an impurity ion using said gate electrode as a mask, after etching said second gate dielectric layer.
- 5. The process according to claim 1, further comprising:etching said second gate dielectric layer and said first gate dielectric layer using said gate electrode as a mask.
- 6. The process according to claim 5, further comprising:doping said semiconductor layer with an impurity ion using said gate electrode as a mask, after etching said second gate dielectric layer and said first gate dielectric layer.
Priority Claims (1)
Number |
Date |
Country |
Kind |
8-159682 |
Jun 1996 |
JP |
|
Parent Case Info
This is a division of application Ser. No. 08/879,515, filed Jun. 20, 1997 now abandoned.
US Referenced Citations (33)