Patent Application
20220020864
The present disclosure claims priority to Chinese Patent Application No. 202010683733.5 filed with the China National Intellectual Property Administration on Jul. 16, 2020, the entire contents of which are incorporated herein by its reference.
The present disclosure relates to the technical field of semiconductors, in particular to a thin film transistor, a method for manufacturing thereof, an array substrate and a display device.
The silicon nanowire has good ductility and elasticity, and can be applied in the field of flexible/stretchable electronics, such as wearable electronics, flexible displays, bionic electronics, artificial skin and other new applications.
However, there is the problem that a nanowire active layer is prone to being influenced by a dry etching process and is prone to being damaged when a via hole for conducting a source-drain and the nanowire active layer is formed through the dry etching process in the related art.
The present disclosure provides a thin film transistor, a method for manufacturing thereof, an array substrate and a display device.
An embodiment of the present disclosure provides a method for manufacturing a thin film transistor, including:
forming a nanowire active layer on one side of a base substrate; forming a conductive protective layer on one side of the nanowire active layer away from the base substrate;
forming an insulating layer on one side of the protective layer away from the nanowire active layer;
forming a first via hole exposing a first region of the protective layer and a second via hole exposing a second region of the protective layer by etching the insulating layer using a dry etching process, wherein the first region and the second region are not overlapped with each other
forming a source-drain layer on one side of the insulating layer away from the protective layer, wherein the source-drain layer includes a first electrode and a second electrode, the first electrode is electrically conducted with the nanowire active layer through the first via hole, and the second electrode is electrically conducted with the nanowire active layer through the second via hole.
In a possible implementation, after etching the insulating layer using the dry etching process, and before forming the source-drain layer on the side of the insulating layer away from the protective layer, the method further includes: removing the protective layer in the first region, and removing the protective layer in the second region by etching the protective layer using a wet etching process.
In a possible implementation, the forming the nanowire active layer on the side of the base substrate includes:
forming a patterned first film layer with at least one guide groove on one side of the base substrate;
forming metal guide particles at one end of the guide groove;
forming an amorphous silicon thin film on one side of the metal guide particles away from the first film layer, and annealing the amorphous silicon thin film to form a silicon nanowire in the guide groove; and
forming the nanowire active layer by patterning the annealed amorphous silicon thin film, wherein a pattern of the nanowire active layer is complementary to that of the first film layer.
In a possible implementation, the forming the metal guide particles at the end of the guide groove includes:
forming a second thin film on one side of the first film layer away from the base substrate; removing the second thin film in other regions except the region where one end of the groove is located; and
forming the metal guide particles by performing hydrogen plasma treatment on the retained second thin film.
In a possible implementation, the forming the second thin film on one side of the first film layer away from the base substrate includes:
forming indium tin oxide on the side of the first film layer away from the base substrate.
In a possible implementation, the forming the conductive protective layer on the side of the nanowire active layer away from the base substrate includes:
forming molybdenum, copper, aluminum or indium tin oxide on one side of the nanowire active layer away from the base substrate.
In a possible implementation, the forming the insulating layer on one side of the protective layer away from the nanowire active layer includes:
forming a gate insulating layer on one side of the protective layer away from the nanowire active layer; and
forming an interlayer dielectric layer on one side of the gate insulating layer away from the nanowire active layer.
In a possible implementation, after the forming the gate insulating layer on the side of the protective layer away from the nanowire active layer, and before the forming the interlayer dielectric layer on the side of the gate insulating layer away from the nanowire active layer, the method further includes:
forming a gate on one side of the gate insulating layer away from the nanowire active layer.
An embodiment of the present disclosure further provides a thin film transistor, including:
a base substrate;
a nanowire active layer on one side of the base substrate;
a conductive protective layer on one side of the nanowire active layer away from the base substrate;
an insulating layer on one side of the protective layer away from the nanowire active layer, wherein the insulating layer has a first via hole exposing a first region of the protective layer and a second via hole exposing a second region of the protective layer, and the first region and the second region are not overlapped with each other; and
a source-drain layer on one side of the insulating layer away from the protective layer, wherein the source-drain layer includes a first electrode and a second electrode, the first electrode is electrically conducted with the nanowire active layer through the first via hole, and the second electrode is electrically conducted with the nanowire active layer through the second via hole.
In a possible implementation, the protective layer has a first hollowed-out structure in the first region, and the protective layer has a second hollowed-out structure in the second region; an orthographic projection of the first hollowed-out structure on the base substrate is coincided with an orthographic projection of the first via hole on the base substrate, and an orthographic projection of the second hollowed-out structure on the base substrate is coincided with an orthographic projection of the second via hole on the base substrate.
In a possible implementation, the thin film transistor further includes: a patterned first film layer between the base substrate and the nanowire active layer, wherein the first film layer has at least one guide groove, and a pattern of the first film layer is complementary to that of the nanowire active layer.
In a possible implementation, metal guide particles are formed in one end of the guide groove by hydrogen plasma treatment on a second thin film.
In a possible implementation, a material of the second thin film is indium tin oxide;
and the nanowire active layer includes the metal guide particles of indium.
In a possible implementation, a material of the protective layer is molybdenum, copper, aluminum or indium tin oxide.
In a possible implementation, the insulating layer includes a gate insulating layer and an interlayer dielectric layer on one side of the gate insulating layer away from the nanowire active layer; and
a gate is further arranged between the gate insulating layer and the interlayer dielectric layer.
An embodiment of the present disclosure further provides an array substrate, including the thin film transistor provided by an embodiment of the present disclosure.
An embodiment of the present disclosure further provides a display device, including the array substrate provided by an embodiment of the present disclosure.
In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described clearly and completely in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, but not all the embodiments. On the basis of the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without inventive efforts fall within the protection scope of the present disclosure.
Unless otherwise defined, the technical or scientific terms used in the present disclosure shall have the usual meanings understood by a person of ordinary skill in the art to which the present disclosure belongs. The words “first”, “second” and the like used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. The word “including” or “comprising” and the like, means that an element or item preceding the word comprises an element or item listed after the word and the equivalent thereof, without excluding other elements or items. The word “connection” or “coupling” and the like is not restricted to physical or mechanical connection, but may include electrical connection, whether direct or indirect. The words “up”, “down”, “left”, “right” and the like are only used to indicate the relative positional relationship. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
In order to keep the following descriptions of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.
Amorphous silicon (a-Si) thin film transistors have failed to meet 8K technical requirements due to too small mobility (<1 cm2V−1S−1). A Low Temperature Poly-Silicon (LTPS) technique is limited by laser beam size and process cost, and thus is limited in use. A planar silicon nanowire has high mobility (>100 cm2V−1S−1), large-area preparation and low cost, and thus becomes a potential application technique for upgrading an a-Si production line. In addition, the silicon nanowire has good ductility and elasticity, and can be applied in the field of flexible/stretchable electronics, such as wearable electronics, flexible displays, bionic electronics, artificial skin and other new applications.
An In-Plane Solid-Liquid-Solid (IP-SLS) growth technique is a new type of planar silicon nanowire growth technique, which is a method for growing nanowires with metal catalysis. Unlike Vapor-Liquid-Solid (VLS) growth, which requires a gaseous precursor (SiH4), a precursor (a-Si:H) in this technique is solid. Growth mechanism: an Indium Tin Oxide (ITO) substrate is processed by hydrogen plasma (H plasma) to form In nano particles on the surface, and then a layer of solid a-Si:H is covered as a precursor source. Then, the substrate is heated, and when the temperature of the substrate is heated to be higher than that of an In/Si alloy, metal catalytic particles start to absorb surrounding a-Si:H, and crystalline silicon nanowire crystal nuclei are precipitated on one side of metal catalytic liquid drops after the concentration of Si atoms in the catalytic liquid drops reaches a supersaturated state. Then, on the basis of the nanocrystal nuclei, the metal catalytic liquid drops continuously absorb a-Si:H to form the silicon nanowire.
Referring to
Step S100, forming a nanowire active layer on one side of a base substrate, wherein the base substrate may specifically be a glass base substrate, and the nanowire active layer may specifically be a silicon nanowire active layer.
Step S200, forming a conductive protective layer on one side of the nanowire active layer away from the base substrate. In some embodiments, step S200 may be: molybdenum, copper, aluminum or indium tin oxide are formed on the side of the nanowire active layer away from the base substrate, that is, a material of the protective layer may specifically be molybdenum, copper, aluminum or indium tin oxide; and the molybdenum, copper, aluminum or indium tin oxide can block gas for dry etching, protect the silicon-based nanowire from being damaged and conduct current.
Step S300, forming an insulating layer on one side of the protective layer away from the nanowire active layer.
Step S400, forming a first via hole exposing a first region of the protective layer and a second via hole exposing a second region of the protective layer by etching the insulating layer using a dry etching process, wherein the first region and the second region are not overlapped with each other.
Step S500, forming a source-drain layer on one side of the insulating layer away from the protective layer, wherein the source-drain layer includes a first electrode and a second electrode, the first electrode is electrically conducted with the nanowire active layer through the first via hole, and the second electrode is electrically conducted with the nanowire active layer through the second via hole. In some embodiments, the first electrode may be a source, and the second electrode may be a drain.
In the method for manufacturing the thin film transistor provided by the embodiments of the present disclosure, before the via hole for electrically conducting the source-drain layer and the nanowire active layer is formed on the insulating layer by the dry etching process, the conductive protective layer is manufactured first; during the formation of the via hole, the protective layer can block gas used in the dry etching process, protect the nanowire active layer from being damaged and conduct current, and further solve the problem that the nanowire active layer is prone to being influenced by the dry etching process to cause damage to the nanowire active layer when the via hole for conducting the source-drain and the nanowire active layer is formed through the dry etching process in the related art.
In specific implementation, as shown in
In specific implementation, the IP-SLS growth technique can be adopted to form the nanowire active layer. In some embodiments, referring to
Step S101, forming a patterned first film layer with at least one guide groove on one side of the base substrate. In some embodiments, the first film layer may be formed by depositing a layer of a first thin film, and then patterning the first thin film; a material of the first film layer may specifically be silicon dioxide (SiO2); for a single thin film transistor, as shown in
Step S102, forming metal guide particles at one end of the guide groove. For example, as shown in
Step S103, forming an amorphous silicon thin film 300 on one side of the metal guide particles 31 away from the first film layer 2, and annealing the amorphous silicon thin film 300 to form a silicon nanowire (also the nanowire active layer 3) in the guide groove 20, as shown in
Step S104, forming the nanowire active layer by patterning the annealed amorphous silicon thin film, wherein a pattern of the nanowire active layer is complementary to that of the first film layer. The patterning of the nanowire active layer in this step can remove the silicon nanowire grown in the region outside the guide groove, and further regularize the pattern of the nanowire active layer.
In specific implementation, the thin film transistor in an embodiment of the present disclosure may be a top gate thin film transistor. The insulating layer in step S100 specifically may include a gate insulating layer and an interlayer dielectric layer on one side of the gate insulating layer away from the protective layer. That is, specifically, regarding step S300, forming the insulating layer on one side of the protective layer away from the nanowire active layer includes: forming the gate insulating layer on one side of the protective layer away from the nanowire active layer; and forming the interlayer dielectric layer on one side of the gate insulating layer away from the nanowire active layer. In some embodiments, after forming the gate insulating layer on one side of the protective layer away from the nanowire active layer, and before forming the interlayer dielectric layer on one side of the gate insulating layer away from the nanowire active layer, the method further includes: forming a gate on one side of the gate insulating layer away from the nanowire active layer.
In order to more clearly understand the method for manufacturing the thin film transistor provided by an embodiment of the present disclosure, the thin film transistor provided by the embodiment of the present disclosure is further described in detail below with reference to the drawings as follows.
In a possible implementation, the method for manufacturing the thin film transistor by removing a protective layer in a first region and a second region may specifically be as follows.
Step 1, forming a patterned first film layer 2 with at least one guide groove 20 (i.e., a guide step) on one side of a base substrate 1. In some embodiments, a silicon dioxide thin film can be deposited first and patterned to form the guide groove 20, as shown in
Step 2, forming a second thin film 30 (specifically, it may be indium tin oxide (ITO) thin film) on one side of the first film layer 2 away from the base substrate 1, wherein a material of the second thin film 30 may specifically be indium tin oxide; removing the second thin film 30 in other regions except a region where one end of the guide groove 20 is located; and forming metal guide particles 31 by performing hydrogen plasma treatment (H2 plasma) on the retained second thin film 30, as shown in
Step 3, forming an amorphous silicon thin film 300 on one side of the metal guide particles 31 away from the first film layer, and annealing the amorphous silicon thin film 300 to form a silicon nanowire (also a nanowire active layer 3) in the guide groove 20, as shown in
Step 4, forming a conductive protective layer 4 on one side of the nanowire active layer 3 away from the base substrate 1. In some embodiments, a metal layer (wet-etchable metals and alloys and metal oxides, such as Mo, ITO, Cu, Al) can be deposited, wet-etched, and patterned, as shown in
Step 5, depositing a gate insulating layer 52, as shown in
Step 6, depositing and patterning a gate metal thin film to form a gate 7, as shown in
Step 7, depositing an interlayer dielectric layer 51, as shown in FIGS.10A and 10B.
Step 8, forming a first via hole 610 and a second via hole 620 by dry-etching the interlayer dielectric layer 51 and by trepanning the interlayer dielectric layer 51 to the protective layer 4, as shown in
Step 9, removing the protective layer 4 in the first region (i.e., the region where the first via hole 610 is located) and the protective layer 4 in the second region (i.e., the region where the second via hole 620 is located),by etching the protective layer 4 using a wet etching process, as shown in
Step 10, forming a source-drain layer (the specific material may be Ti/Al/Ti) on one side of the interlayer dielectric layer 51 away from the gate 7, and dry etching and patterning the same, wherein the source-drain layer includes a first electrode 61 and a second electrode 62, the first electrode 61 is electrically conducted with the nanowire active layer 3 through the first via hole 610, and the second electrode 62 is electrically conducted with the nanowire active layer 3 through the second via hole 620. In some embodiments, the first electrode 61 may be electrically conducted with the nanowire active layer 3 through the plurality of first via holes 610, and the second electrode 62 may be electrically conducted with the nanowire active layer 3 through the plurality of second via holes 620, as shown in
In another possible implementation, the method for manufacturing the thin film transistor by retaining the protective layer 3 in the first region and the second region may specifically be as follows.
Step 1, forming a patterned first film layer 2 with at least one guide groove 20 (a guide step) on one side of a base substrate 1. In some embodiments a silicon dioxide thin film can be deposited first and patterned to form the guide groove 20, as shown in
Step 2, forming a second thin film 30 (specifically, it may be indium tin oxide (ITO) thin film) on one side of the first film layer 2 away from the base substrate 1, wherein a material of the second thin film 30 may specifically be indium tin oxide; removing the second thin film 30 in other regions except the region where one end of the guide groove 20 is located; and forming metal guide particles 31 by performing hydrogen plasma treatment (H2 plasma) on the retained second thin film 30, as shown in
Step 3, forming an amorphous silicon thin film 300 on one side of the metal guide particles 31 away from the first film layer, and annealing the amorphous silicon thin film 300 to form a silicon nanowire (also a nanowire active layer 3) in the guide groove 20, as shown in
Step 4, forming a conductive protective layer 4 on one side of the nanowire active layer 3 away from the base substrate 1. In some embodiments, a metal layer (wet-etchable metals and alloys and metal oxides such as Mo, ITO, Cu, Al) can be deposited, wet-etched, and patterned, as shown in
Step 5, depositing a gate insulating layer 52, as shown in
Step 6, depositing and patterning a gate metal thin film to form a gate 7, as shown in
Step 7, depositing an interlayer dielectric layer 51, as shown in FIGS.10A and 10B.
Step 8, forming a first via hole 610 and a second via hole 620 by dry-etching the interlayer dielectric layer 51 and by trepanning the interlayer dielectric layer 51 to the protective layer 4, as shown in
Step 9, forming a source-drain layer (the specific material may be Ti/Al/Ti) on one side of the interlayer dielectric layer 51 away from the gate 7, and dry etching and patterning the same, wherein the source-drain layer includes a first electrode 61 and a second electrode 62, the first electrode 61 is electrically conducted with the nanowire active layer 3 through the first via hole 610, and the second electrode 62 is electrically conducted with the nanowire active layer 3 through the second via hole 620. As shown in
On the basis of the same inventive concept, an embodiment of the present disclosure further provides a thin film transistor. As shown in
a base substrate 1, wherein a material of the base substrate 1 may specifically be glass;
a nanowire active layer 3 on one side of the base substrate 1, wherein a material of the nanowire active layer 3 may specifically be a silicon nanowire active layer;
a conductive protective layer 4 on one side of the nanowire active layer 3 away from the base substrate 1;
an insulating layer 5 on one side of the protective layer 4 away from the nanowire active layer 3, wherein the insulating layer 5 has a first via hole 610 exposing a first region of the protective layer 4 and a second via hole 620 exposing a second region of the protective layer 4, and the first region and the second region are not overlapped with each other; and
a source-drain layer on one side of the insulating layer 5 away from the protective layer 4, wherein the source-drain layer includes a first electrode 61 and a second electrode 62, the first electrode 61 is electrically conducted with the nanowire active layer 3 through the first via hole 610 and specifically may be electrically conducted with the nanowire active layer 3 through the protective layer 4, and the second electrode 62 is electrically conducted with the nanowire active layer 3 through the second via hole 620 and specifically may be electrically conducted with the nanowire active layer 3 through the protective layer 4.
The thin film transistor provided by an embodiment of the present disclosure includes: the nanowire active layer 3 on one side of the base substrate 1; the conductive protective layer 4 on one side of the nanowire active layer 3 away from the base substrate 1; and the source-drain layer on one side of the insulating layer 5 away from the protective layer 4, wherein the source-drain layer includes a first electrode 61 and a second electrode 62, the first electrode 61 is electrically conducted with the nanowire active layer 3 through the first via hole 610, and the second electrode 62 is electrically conducted with the nanowire active layer 3 through the second via hole 620. In other words, when manufacturing the thin film transistor, before the via hole for electrically conducting the source-drain layer and the nanowire active layer is formed on the insulating layer by a dry etching process, the conductive protective layer is manufactured first; during the formation of the via hole, the protective layer can block gas used in the dry etching process, protect the nanowire active layer from being damaged and conduct current, and further solve the problem that the nanowire active layer is prone to being influenced by the dry etching process to cause damage to the nanowire active layer when the via hole for conducting a source-drain and the nanowire active layer is formed through the dry etching process in the related art.
In specific implementation, since the protective layer 4 is a conductive film layer, the protective layer 4 can be retained when manufacturing the thin film transistor to simplify a process for manufacturing the thin film transistor. The structural view of the formed thin film transistor may be as shown in
In specific implementation, as shown in
In specific implementation, as shown in
In specific implementation, a material of the protective layer 4 is molybdenum, copper, aluminum or indium tin oxide. In an embodiment of the present disclosure, the molybdenum, copper, aluminum or indium tin oxide block gas for dry etching, has a good effect of protecting the silicon-based nanowire from being damaged and can conduct current.
In specific implementation, the thin film transistor provided by an embodiment of the present disclosure may be a top gate thin film transistor, as shown in
An embodiment of the present disclosure further provides an array substrate, including the thin film transistors provided by the embodiments of the present disclosure. In some embodiments, since the array substrate is generally provided with a plurality of thin film transistors at the same time, respective film layers of the plurality of thin film transistors are formed synchronously, and then a film layer shared by the plurality of transistors is formed on the array substrate, for example, a shared patterned first film layer 2, as shown in
An embodiment of the present disclosure further provides a display device, including the array substrate provided by the embodiment of the present disclosure.
The embodiments of the present disclosure have the following beneficial effects: in the method of the thin film transistor provided by the embodiments of the present disclosure, before the via hole for electrically conducting the source-drain layer and the nanowire active layer is formed on the insulating layer by the dry etching process, the conductive protective layer is manufactured first; during the formation of the via hole, the protective layer can block gas used in the dry etching process, protect the nanowire active layer from being damaged and conduct current, and further solve the problem that the nanowire active layer is prone to being influenced by the dry etching process to cause damage to the nanowire active layer when the via hole for conducting a source-drain and the nanowire active layer is formed through the dry etching process in the related art.
Obviously, those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. In this way, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent art, the present disclosure also intends to include these modifications and variations.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202010683733.5 | Jul 2020 | CN | national |
