Claims
- 1. In a dynamic random access memory (DRAM) device, a process for forming a DRAM cell comprising a transistor having a sub-groundrule gate above a capacitor, the process comprises:
- providing a semiconductor substrate having a capacitor formed in a capacitor region defined therein, wherein the capacitor comprises polycrystalline material;
- removing a top portion of the capacitor to form a recess below a top surface of the semiconductor substrate;
- growing a silicon layer in the recess by epitaxial growth to substantially fill the recess, wherein a top surface of the silicon layer is substantially single crystalline on which the transistor is fabricated;
- depositing a wordline conductor layer over the surface of the semiconductor substrate;
- depositing a mandrel layer over the conductor layer and patterning the mandrel layer to form a mandrel such that a side edge of the mandrel overlaps a portion of the capacitor region of the DRAM cell;
- forming a spacer on the side edge of the mandrel wherein the spacer defines a gate region over the capacitor region and non-gate regions adjacent to the gate region removing said mandrel;
- forming the sub-groundrule gate in the defined gate region by selectively removing portions of said wordline layer from the non-gate regions, wherein the sub-groundrule gate enables the transistor to be formed over the capacitor region of a capacitor; and removing said spacer.
Parent Case Info
This application is a continuation-in-part of a U.S. Ser. No. 08/667,541; now U.S. Pat. No. 5,792,685 (attorney docket number 96-P-7406-US01) filed on Jun. 21, 1996, titled "Three-dimensional Device Layout", which is a continuation-in-part of U.S. Ser. No. 08/605,622; now U.S. Pat. No. 5,827,765, filed on Feb. 22, 1996, titled "Buried-Strap Formation A DRAM Trench Capacitor", all herein incorporated by reference for all purposes.
US Referenced Citations (9)
Continuation in Parts (2)
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Number |
Date |
Country |
Parent |
667541 |
Jun 1996 |
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Parent |
605622 |
Feb 1996 |
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