Three-dimensional integrated C-MOS circuit and method for producing same

Abstract

The three-dimensional integrated CMOS circuit is formed in a hybrid substrate. n-MOS type transistors are formed, at a bottom level, in a first semi-conducting layer of silicon having a (100) orientation, which layer may be tension strained. p-MOS transistors are formed, at a top level, in a preferably monocrystalline and compression strained second semi-conducting layer of germanium having a (110) orientation. The second semi-conducting layer is transferred onto a first block in which the n-MOS transistors were previously formed, and the p-MOS transistors are then formed.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Other advantages and features will become more clearly apparent from the following description of particular embodiments of the invention given as non-restrictive examples only and represented in the accompanying drawings, in which:

FIGS. 1 to 3 illustrate production of a hybrid substrate according to the prior art by heteroepitaxy.

FIG. 4 illustrates formation of a hybrid substrate according to the prior art by layer transfer.

FIG. 5 represents the conventional wiring diagram of an inverter formed by p-MOS and n-MOS transistors.

FIGS. 6 to 8 illustrate a particular embodiment of a circuit according to the invention respectively in perspective, in top view and in cross-section along A-A.

FIG. 9 illustrates a particular embodiment of a circuit according to the invention.

FIG. 10 schematically illustrates a particular embodiment of a multiple via of a circuit according to the invention.

Claims

1. A three-dimensional integrated CMOS circuit formed in a hybrid substrate with superposed bottom and top levels and comprising n-MOS transistors formed, at the bottom level, in a silicon semi-conducting layer having a (100) orientation and p-MOS transistors formed, at the top level, in a germanium semi-conducting layer having a (110) orientation.

2. Circuit according to claim 1, wherein at least one of the semi-conducting layers is strained in a suitable manner for fabrication of the corresponding transistors.

3. Circuit according to claim 2, wherein the silicon semi-conducting layer is made of tension strained silicon.

4. Circuit according to claim 2, wherein the germanium semi-conducting layer is made of compression strained germanium.

5. Circuit according to claim 4, wherein the germanium semi-conducting layer is made of biaxially strained germanium.

6. Circuit according to claim 1, wherein the germanium is monocrystalline.

7. Circuit according to claim 1, wherein the longitudinal axes of an n-MOS transistor and of an associated p-MOS transistor are perpendicular so as to form at least one overlapping zone in which an interconnection of said associated transistors is formed.

8. Circuit according to claim 7, wherein the drain or source of an n-MOS transistor being designed to be connected to the source or drain of an associated n-MOS transistor, they are longitudinally extended so as to form a first overlapping zone in which a first interconnection of the transistors is formed.

9. Circuit according to claim 8, comprising vertical connections formed at the ends of the transistors opposite the first overlapping zone.

10. Circuit according to claim 7, wherein the gates of the transistors are extended perpendicularly to their respective longitudinal axes so as to form, at one end thereof, a second overlapping zone in which a second interconnection of the transistors is formed.

11. A method for producing a three-dimensional CMOS integrated circuit in a hybrid substrate and comprising transistors of different conductivity types respectively formed in superposed first and second semi-conducting layers, method successively comprising: fabrication of a first block comprising n-MOS transistors formed in a semi-conducting layer, made of silicon having a suitable orientation for fabrication of n-MOS transistors,transfer onto the first block of a semi-conducting layer of germanium having a suitable orientation for fabrication of p-MOS transistors andfabrication of p-MOS transistors in the germanium semi-conducting layer at a temperature not affecting the transistors formed in the silicon semi-conducting layer.

12. Method according to claim 11, wherein the fabrication temperature of the p-MOS transistors in the germanium semi-conducting layer is about 400 to 600° C.

13. Method according to claim 11, wherein transfer of the germanium semi-conducting layer to the first block is performed by molecular bonding and thinning.

14. Method according to claim 11, wherein transfer of the germanium semi-conducting layer to the first block is performed by hydrogen implantation, bonding and detachment.

15. Method according to claim 11, wherein transfer of the germanium semi-conducting layer to the first block is performed by liquid phase epitaxy after a cavity has been opened out onto the substrate having a (110) orientation in order to obtain an oriented crystallization seed.

16. Method according to claim 11, comprising formation of vertical multiple vias constituting the interconnections between the associated n-MOS and p-MOS transistors of different levels.

17. Method according to claim 11, comprising formation of vertical single vias constituting various connections of the circuit.

18. Method according to claim 11, comprising formation of vias before the germanium semi-conducting layer is produced.

19. Method according to claim, 11, wherein the silicon of the first semi-conducting layer has a (100) orientation and the germanium of the second semi-conducting layer has a (110) orientation.