Patent Grant
12150300
The present disclosure relates generally to the field of semiconductor devices, and particularly to a three-dimensional memory device including contact via structures for multi-level stepped surfaces and methods of manufacturing the same.
Three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh et al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36.
According to an aspect of the present disclosure, a three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing a terrace region having a plurality of steps, memory stack structures extending through the alternating stack, a retro-stepped dielectric material portion overlying the terrace region, first laterally isolated contact structures including a respective first contact via structure and a respective first dielectric spacer, and second laterally isolated contact structures including a respective second contact via structure and a respective second dielectric spacer. The respective first contact via structure contacts a top surface of a respective first electrically conductive layer in the respective step of the plurality of steps. The respective second contact via structure extends through the respective first electrically conductive layer in the respective step and contacts a top surface of a respective second electrically conductive layer which underlies the first electrically conductive layer in the respective step.
According to another aspect of the present disclosure, a method of forming a three-dimensional memory device is provided. The method comprises: forming a combination of an alternating stack of insulating layers and electrically conductive layers, memory stack structures, and a retro-stepped dielectric material portion over a substrate, wherein the memory stack structures vertically extend through the alternating stack, the alternating stack comprises stepped surfaces that continuously extend from a bottommost layer of the alternating stack to a topmost layer of the alternating stack, and the retro-stepped dielectric material portion overlies the stepped surfaces of the alternating stack; forming first via cavities and second via cavities through the retro-stepped dielectric material portion, wherein each of the first via cavities and the second via cavities vertically extends through the retro-stepped dielectric material portion and has a bottom surface that coincides with a top surface segment of a respective one of the electrically conductive layers; vertically extending the second via cavities through a respective pair of an electrically conductive layer and an insulating layer while masking the first via cavities, whereby a top surface of a respective underlying electrically conductive layer is physically exposed underneath each of the second via cavities; and forming first laterally-isolated contact structure in the first via cavities and second laterally-isolated contact structure in the second via cavities, wherein each of the first laterally-isolated contact structures includes a respective first contact via structure and a respective first dielectric spacer, and each of the second contact via structures comprises a respective second contact via structure and a respective second dielectric spacer.
According to an aspect of the present disclosure, a three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing a terrace region comprising a plurality of steps, memory stack structures extending through the alternating stack, a retro-stepped dielectric material portion overlying terrace region of the alternating stack, first laterally-isolated contact structures each including a respective first contact via structure and a respective first dielectric spacer, wherein the respective first contact via structure contacts a top surface of a respective upper electrically conductive layer of the electrically conductive layers in the respective step, and the respective first dielectric spacer extends through the retro-stepped dielectric material portion and does not contact any of the electrically conductive layers other than the respective upper electrically conductive layer in the respective step, and second laterally-isolated contact structures including a respective second contact via structure and a respective second dielectric spacer, wherein the respective second contact via structure contacts a top surface of a respective lower electrically conductive layer of the electrically conductive layers in the respective step, and the respective second dielectric spacer extends through the retro-stepped dielectric material portion and through the respective upper electrically conductive layer, and contacts the respective lower electrically conductive layer.
According to another aspect of the present disclosure, a method of forming a three-dimensional memory device comprises forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers comprise, or are subsequently replaced with, electrically conductive layers, forming a plurality of steps by patterning the alternating stack, forming a retro-stepped dielectric material portion over the plurality of steps, forming a first via cavity and a second via cavity that vertically extend through the retro-stepped dielectric material portion down to a top surface of an upper electrically conductive layer of the electrically conductive layers in a first step of the plurality of steps by performing a first anisotropic etch process, vertically extending the second via cavity through the upper electrically conductive layer and one of the insulating layers down to a top surface of a lower electrically conductive layer of the electrically conductive layers in the first step by performing a second anisotropic etch process without vertically extending the first via cavity, and forming a first laterally-isolated contact structure in the first via cavity and a second laterally-isolated contact structure in the second via cavity, wherein the first laterally-isolated contact structure includes a first contact via structure and a first dielectric spacer, and the second contact via structure comprises a second contact via structure and a second dielectric spacer.
As discussed above, the present disclosure is directed to three-dimensional memory devices including a vertical stack of multilevel memory arrays and methods of making thereof, the various aspects of which are described below. The embodiments of the disclosure can be employed to form various structures including a multilevel memory structure, non-limiting examples of which include semiconductor devices such as three-dimensional memory array devices comprising a plurality of NAND memory strings.
The drawings are not drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure. The term “at least one” element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.
The same reference numerals refer to the same element or similar element. Unless otherwise indicated, elements having the same reference numerals are presumed to have the same composition and the same function. Unless otherwise indicated, a “contact” between elements refers to a direct contact between elements that provides an edge or a surface shared by the elements. If two or more elements are not in direct contact with each other or among one another, the two elements are “disjoined from” each other or “disjoined among” one another. As used herein, a first element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, a first element is located “directly on” a second element if there exist a physical contact between a surface of the first element and a surface of the second element. As used herein, a first element is “electrically connected to” a second element if there exists a conductive path consisting of at least one conductive material between the first element and the second element. As used herein, a “prototype” structure or an “in-process” structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein.
As used herein, a “layer” refers to a material portion including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer may be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer may extend horizontally, vertically, and/or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layer thereupon, thereabove, and/or therebelow.
As used herein, a first surface and a second surface are “vertically coincident” with each other if the second surface overlies or underlies the first surface and there exists a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from a vertical direction by an angle less than 5 degrees. A vertical plane or a substantially vertical plane is straight along a vertical direction or a substantially vertical direction, and may, or may not, include a curvature along a direction that is perpendicular to the vertical direction or the substantially vertical direction.
Generally, a semiconductor package (or a “package”) refers to a unit semiconductor device that can be attached to a circuit board through a set of pins or solder balls. A semiconductor package may include a semiconductor chip (or a “chip”) or a plurality of semiconductor chips that are bonded thereamongst, for example, by flip-chip bonding or another chip-to-chip bonding. A package or a chip may include a single semiconductor die (or a “die”) or a plurality of semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or a chip with multiple dies is capable of simultaneously executing as many number of external commands as the total number of planes therein. Each die includes one or more planes. Identical concurrent operations can be executed in each plane within a same die, although there may be some restrictions. In case a die is a memory die, i.e., a die including memory elements, concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within a same memory die. In a memory die, each plane contains a number of memory blocks (or “blocks”), which are the smallest unit that can be erased by in a single erase operation. Each memory block contains a number of pages, which are the smallest units that can be selected for programming A page is also the smallest unit that can be selected to a read operation.
Referring to
As used herein, a “semiconducting material” refers to a material having electrical conductivity in the range from 1.0×10−5 S/m to 1.0×105 S/m. As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1.0×10−5 S/m to 1.0 S/m in the absence of electrical dopants therein, and is capable of producing a doped material having electrical conductivity in a range from 1.0 S/m to 1.0×105 S/m upon suitable doping with an electrical dopant. As used herein, an “electrical dopant” refers to a p-type dopant that adds a hole to a valence band within a band structure, or an n-type dopant that adds an electron to a conduction band within a band structure. As used herein, a “conductive material” refers to a material having electrical conductivity greater than 1.0×105 S/m. As used herein, an “insulator material” or a “dielectric material” refers to a material having electrical conductivity less than 1.0×10−5 S/m. As used herein, a “heavily doped semiconductor material” refers to a semiconductor material that is doped with electrical dopant at a sufficiently high atomic concentration to become a conductive material either as formed as a crystalline material or if converted into a crystalline material through an anneal process (for example, from an initial amorphous state), i.e., to have electrical conductivity greater than 1.0×105 S/m. A “doped semiconductor material” may be a heavily doped semiconductor material, or may be a semiconductor material that includes electrical dopants (i.e., p-type dopants and/or n-type dopants) at a concentration that provides electrical conductivity in the range from 1.0×10−5 S/m to 1.0×105 S/m. An “intrinsic semiconductor material” refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material may be semiconducting or conductive, and may be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive depending on the atomic concentration of electrical dopants therein. As used herein, a “metallic material” refers to a conductive material including at least one metallic element therein. All measurements for electrical conductivities are made at the standard condition.
At least one semiconductor device 700 for a peripheral circuitry can be formed on a portion of the substrate semiconductor layer 9. The at least one semiconductor device can include, for example, field effect transistors. For example, at least one shallow trench isolation structure 720 can be formed by etching portions of the substrate semiconductor layer 9 and depositing a dielectric material therein. A gate dielectric layer, at least one gate conductor layer, and a gate cap dielectric layer can be formed over the substrate semiconductor layer 9, and can be subsequently patterned to form at least one gate structure (750, 752, 754, 758), each of which can include a gate dielectric 750, a gate electrode (752, 754), and a gate cap dielectric 758. The gate electrode (752, 754) may include a stack of a first gate electrode portion 752 and a second gate electrode portion 754. At least one gate spacer 756 can be formed around the at least one gate structure (750, 752, 754, 758) by depositing and anisotropically etching a dielectric liner. Active regions 730 can be formed in upper portions of the substrate semiconductor layer 9, for example, by introducing electrical dopants employing the at least one gate structure (750, 752, 754, 758) as masking structures. Additional masks may be employed as needed. The active region 730 can include source regions and drain regions of field effect transistors.
A first dielectric liner 761 and a second dielectric liner 762 can be optionally formed. Each of the first and second dielectric liners (761, 762) can comprise a silicon oxide layer, a silicon nitride layer, and/or a dielectric metal oxide layer. As used herein, silicon oxide includes silicon dioxide as well as non-stoichiometric silicon oxides having more or less than two oxygen atoms for each silicon atoms. Silicon dioxide is preferred. In an illustrative example, the first dielectric liner 761 can be a silicon oxide layer, and the second dielectric liner 762 can be a silicon nitride layer. The least one semiconductor device for the peripheral circuitry can contain a driver circuit for memory devices to be subsequently formed, which can include at least one NAND device. A dielectric material such as silicon oxide can be deposited over the at least one semiconductor device, and can be subsequently planarized to form a planarization dielectric layer 770. In one embodiment the planarized top surface of the planarization dielectric layer 770 can be coplanar with a top surface of the dielectric liners (761, 762). Subsequently, the planarization dielectric layer 770 and the dielectric liners (761, 762) can be removed from an area to physically expose a top surface of the substrate semiconductor layer 9. As used herein, a surface is “physically exposed” if the surface is in physical contact with vacuum, or a gas phase material (such as air).
The optional semiconductor material layer 10, if present, can be formed on the top surface of the substrate semiconductor layer 9 prior to, or after, formation of the at least one semiconductor device 700 by deposition of a single crystalline semiconductor material, for example, by selective epitaxy. The deposited semiconductor material can be the same as, or can be different from, the semiconductor material of the substrate semiconductor layer 9. The deposited semiconductor material can be any material that can be employed for the substrate semiconductor layer 9 as described above. The single crystalline semiconductor material of the semiconductor material layer 10 can be in epitaxial alignment with the single crystalline structure of the substrate semiconductor layer 9. Portions of the deposited semiconductor material located above the top surface of the planarization dielectric layer 770 can be removed, for example, by chemical mechanical planarization (CMP). In this case, the semiconductor material layer 10 can have a top surface that is coplanar with the top surface of the planarization dielectric layer 770.
The region (i.e., area) of the at least one semiconductor device 700 is herein referred to as a peripheral device region 200. The region in which a memory array is subsequently formed is herein referred to as a memory array region 100. A staircase region 300 for subsequently forming stepped terraces of electrically conductive layers can be provided between the memory array region 100 and the peripheral device region 200. In one alternative embodiment, the peripheral device region 200 containing the at least one semiconductor device 700 for a peripheral circuitry may be located under the memory array region 100 in a CMOS under array configuration. In another alternative embodiment, the peripheral device region 200 may be located on a separate substrate which is subsequently bonded to the memory array region 100.
Referring to
Each first material layer includes a first material, and each second material layer includes a second material that is different from the first material. In one embodiment, each first material layer can be an insulating layer 32, and each second material layer can be a sacrificial material layer. In this case, the stack can include an alternating plurality of insulating layers 32 and sacrificial material layers 42, and constitutes a prototype stack of alternating layers comprising insulating layers 32 and sacrificial material layers 42.
The stack of the alternating plurality is herein referred to as an alternating stack (32, 42). In one embodiment, the alternating stack (32, 42) can include insulating layers 32 composed of the first material, and sacrificial material layers 42 composed of a second material different from that of insulating layers 32. The first material of the insulating layers 32 can be at least one insulating material. As such, each insulating layer 32 can be an insulating material layer. Insulating materials that can be employed for the insulating layers 32 include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides that are commonly known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the insulating layers 32 can be silicon oxide. In one embodiment, the insulating layers 32 can include, and/or can consist essentially of, undoped silicate glass or a doped silicate glass.
The second material of the sacrificial material layers 42 is a sacrificial material that can be removed selective to the first material of the insulating layers 32. As used herein, a removal of a first material is “selective to” a second material if the removal process removes the first material at a rate that is at least twice the rate of removal of the second material. The ratio of the rate of removal of the first material to the rate of removal of the second material is herein referred to as a “selectivity” of the removal process for the first material with respect to the second material.
The sacrificial material layers 42 may comprise an insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layers 42 can be subsequently replaced with electrically conductive electrodes which can function, for example, as control gate electrodes of a vertical NAND device. Non-limiting examples of the second material include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polysilicon). In one embodiment, the sacrificial material layers 42 can be spacer material layers that comprise silicon nitride or a semiconductor material including at least one of silicon and germanium.
In one embodiment, the insulating layers 32 can include silicon oxide, and sacrificial material layers can include silicon nitride sacrificial material layers. The first material of the insulating layers 32 can be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is employed for the insulating layers 32, tetraethyl orthosilicate (TEOS) can be employed as the precursor material for the CVD process. The second material of the sacrificial material layers 42 can be formed, for example, CVD or atomic layer deposition (ALD).
The sacrificial material layers 42 can be suitably patterned so that conductive material portions to be subsequently formed by replacement of the sacrificial material layers 42 can function as electrically conductive electrodes, such as the control gate electrodes of the monolithic three-dimensional NAND string memory devices to be subsequently formed. The sacrificial material layers 42 may comprise a portion having a strip shape extending substantially parallel to the major surface 7 of the substrate.
The thicknesses of the insulating layers 32 and the sacrificial material layers 42 can be in a range from 20 nm to 50 nm, although lesser and greater thicknesses can be employed for each insulating layer 32 and for each sacrificial material layer 42. The number of repetitions of the pairs of an insulating layer 32 and a sacrificial material layer (e.g., a control gate electrode or a sacrificial material layer) 42 can be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions can also be employed. The top and bottom gate electrodes in the stack may function as the select gate electrodes. In one embodiment, each sacrificial material layer 42 in the alternating stack (32, 42) can have a uniform thickness that is substantially invariant within each respective sacrificial material layer 42.
While the present disclosure is described employing an embodiment in which the spacer material layers are sacrificial material layers 42 that are subsequently replaced with electrically conductive layers, embodiments are expressly contemplated herein in which the sacrificial material layers are formed as electrically conductive layers. In this case, steps for replacing the spacer material layers with electrically conductive layers can be omitted.
In one embodiment, the topmost layer of the alternating stack (32, 42) may be an insulating layer 32. The topmost insulating layer 32 may have a greater thickness than each of the insulating layers 32.
Referring to
The terrace region is formed in the staircase region 300, which is located between the memory array region 100 and the peripheral device region 200 containing the at least one semiconductor device for the peripheral circuitry. The stepped cavity can have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes in steps as a function of the vertical distance from the top surface of the substrate (9, 10). In one embodiment, the stepped cavity can be formed by repetitively performing a set of processing steps. The set of processing steps can include, for example, an etch process of a first type that vertically increases the depth of a cavity by one or more levels, and an etch process of a second type that laterally expands the area to be vertically etched in a subsequent etch process of the first type. As used herein, a “level” of a structure including alternating plurality is defined as the relative position of a pair of a first material layer and a second material layer within the structure.
Each sacrificial material layer 42 other than a topmost sacrificial material layer 42 within the alternating stack (32, 42) laterally extends farther than any overlying sacrificial material layer 42 within the alternating stack (32, 42) in the terrace region. The terrace region includes stepped surfaces of the alternating stack (32, 42) that continuously extend from a bottommost layer within the alternating stack (32, 42) to a topmost layer within the alternating stack (32, 42).
In one embodiment, the layers within the alternating stack (32, 42) may have a vertical periodicity. The vertical periodicity of the alternating stack (32, 42) is the same as the vertical periodicity of the insulating layers 32, which is the same as the vertical periodicity of the sacrificial material layers 42. The vertical periodicity can be the same as the sum of a thickness of an insulating layer 32 and the thickness of a sacrificial material layer 42. The vertical periodicity can be the same as the vertical separation distance between top surfaces of a vertically neighboring pair of insulating layers 32 within the alternating stack (32, 42). Further, the vertical periodicity can be the same as the vertical separation distance between top surfaces of a vertically neighboring pair of sacrificial material layers 42 within the alternating stack (32, 42).
According to an aspect of the present disclosure, the stepped surfaces of the alternating stack (32, 42) can be vertically offset from each other by integer multiples of the vertical periodicity of the alternating stack (32, 42). For example, physically exposed horizontal surfaces of the alternating stack (32, 42) can be vertically spaced apart from each other by multiples of K times the vertical periodicity, where K is an integer greater than 1, i.e., an integer such as 2, 3, 4, 5, 6, 7, 8, etc. In one embodiment, K is an integer in a range from 2 to 2N, and wherein N is an integer in a range from 2 to 6. Thus, each vertical step in the stepped surfaces of the alternating stack (32, 42) can have a respective straight sidewall that vertically extends over at least two (e.g., two to four) insulating layers 32 and at least two (e.g., two to four) sacrificial material layers 42. Each vertical step of the stepped surfaces can have the height of multiple pairs of an insulating layer 32 and a sacrificial material layer 42.
A retro-stepped dielectric material portion 65 (i.e., an insulating fill material portion) can be formed in the stepped cavity by deposition of a dielectric material therein. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed from above the top surface of the topmost insulating layer 32, for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the retro-stepped dielectric material portion 65. As used herein, a “retro-stepped” element refers to an element that has stepped surfaces and a horizontal cross-sectional area that increases monotonically as a function of a vertical distance from a top surface of a substrate on which the element is present. If silicon oxide is employed for the retro-stepped dielectric material portion 65, the silicon oxide of the retro-stepped dielectric material portion 65 may, or may not, be doped with dopants such as B, P, and/or F.
Generally, the retro-stepped dielectric material portion 65 comprises a contiguous set of surfaces that includes horizontal bottom surface segments and vertical surface segments. The retro-stepped dielectric material portion 65 includes a set of horizontal bottom surface segments and vertical surface segments. The horizontal bottom surface segments are vertically spaced apart from each other and are laterally spaced apart from each other. Each of the horizontal bottom surface segments other than the bottommost one of the horizontal bottom surface segments can be adjoined to a respective pair of vertical surfaces segments among the vertical surface segments of the retro-stepped dielectric material portion 65.
Optionally, drain-select-level isolation structures 72 can be formed through the topmost insulating layer 32 and a subset of the sacrificial material layers 42 located at drain select levels. The drain-select-level isolation structures 72 can be formed, for example, by forming drain-select-level isolation trenches and filling the drain-select-level isolation trenches with a dielectric material such as silicon oxide. Excess portions of the dielectric material can be removed from above the top surface of the topmost insulating layer 32.
Referring to
The memory openings 49 extend through the entirety of the alternating stack (32, 42). The support openings 19 extend through a subset of layers within the alternating stack (32, 42). The chemistry of the anisotropic etch process employed to etch through the materials of the alternating stack (32, 42) can alternate to optimize etching of the first and second materials in the alternating stack (32, 42). The anisotropic etch can be, for example, a series of reactive ion etches. The sidewalls of the memory openings 49 and the support openings 19 can be substantially vertical, or can be tapered. The patterned lithographic material stack can be subsequently removed, for example, by ashing.
The memory openings 49 and the support openings 19 can extend from the top surface of the alternating stack (32, 42) to at least the horizontal plane including the topmost surface of the semiconductor material layer 10. In one embodiment, an overetch into the semiconductor material layer 10 may be optionally performed after the top surface of the semiconductor material layer 10 is physically exposed at a bottom of each memory opening 49 and each support opening 19. The overetch may be performed prior to, or after, removal of the lithographic material stack. In other words, the recessed surfaces of the semiconductor material layer 10 may be vertically offset from the un-recessed top surfaces of the semiconductor material layer 10 by a recess depth. The recess depth can be, for example, in a range from 1 nm to 50 nm, although lesser and greater recess depths can also be employed. The overetch is optional, and may be omitted. If the overetch is not performed, the bottom surfaces of the memory openings 49 and the support openings 19 can be coplanar with the topmost surface of the semiconductor material layer 10.
Each of the memory openings 49 and the support openings 19 may include a sidewall (or a plurality of sidewalls) that extends substantially perpendicular to the topmost surface of the substrate. A two-dimensional array of memory openings 49 can be formed in the memory array region 100. A two-dimensional array of support openings 19 can be formed in the staircase region 300. The substrate semiconductor layer 9 and the semiconductor material layer 10 collectively constitutes a substrate (9, 10), which can be a semiconductor substrate. Alternatively, the semiconductor material layer 10 may be omitted, and the memory openings 49 and the support openings 19 can be extend to a top surface of the substrate semiconductor layer 9.
Referring to
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The blocking dielectric layer 52 can include a single dielectric material layer or a stack of a plurality of dielectric material layers. In one embodiment, the blocking dielectric layer can include a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material that includes at least one metallic element and at least oxygen. The dielectric metal oxide may consist essentially of the at least one metallic element and oxygen, or may consist essentially of the at least one metallic element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer 52 can include a dielectric metal oxide having a dielectric constant greater than 7.9, i.e., having a dielectric constant greater than the dielectric constant of silicon nitride.
Non-limiting examples of dielectric metal oxides include aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), silicates thereof, nitrogen-doped compounds thereof, alloys thereof, and stacks thereof. The dielectric metal oxide layer can be deposited, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), liquid source misted chemical deposition, or a combination thereof. The thickness of the dielectric metal oxide layer can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed. The dielectric metal oxide layer can subsequently function as a dielectric material portion that blocks leakage of stored electrical charges to control gate electrodes. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide. In one embodiment, the blocking dielectric layer 52 can include multiple dielectric metal oxide layers having different material compositions.
Alternatively or additionally, the blocking dielectric layer 52 can include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the blocking dielectric layer 52 can include silicon oxide. In this case, the dielectric semiconductor compound of the blocking dielectric layer 52 can be formed by a conformal deposition method such as low pressure chemical vapor deposition, atomic layer deposition, or a combination thereof. The thickness of the dielectric semiconductor compound can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed. Alternatively, the blocking dielectric layer 52 can be omitted, and a backside blocking dielectric layer can be formed after formation of backside recesses on surfaces of memory films to be subsequently formed.
Subsequently, the charge storage layer 54 can be formed. In one embodiment, the charge storage layer 54 can be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material, which can be, for example, silicon nitride. Alternatively, the charge storage layer 54 can include a continuous layer or patterned discrete portions of a conductive material such as doped polysilicon or a metallic material that is patterned into multiple electrically isolated portions (e.g., floating gates), for example, by being formed within lateral recesses into sacrificial material layers 42. In one embodiment, the charge storage layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layers 42 and the insulating layers 32 can have vertically coincident sidewalls, and the charge storage layer 54 can be formed as a single continuous layer.
In another embodiment, the sacrificial material layers 42 can be laterally recessed with respect to the sidewalls of the insulating layers 32, and a combination of a deposition process and an anisotropic etch process can be employed to form the charge storage layer 54 as a plurality of memory material portions that are vertically spaced apart. While the present disclosure is described employing an embodiment in which the charge storage layer 54 is a single continuous layer, embodiments are expressly contemplated herein in which the charge storage layer 54 is replaced with a plurality of memory material portions (which can be charge trapping material portions or electrically isolated conductive material portions) that are vertically spaced apart.
The charge storage layer 54 can be formed as a single charge storage layer of homogeneous composition, or can include a stack of multiple charge storage layers. The multiple charge storage layers, if employed, can comprise a plurality of spaced-apart floating gate material layers that contain conductive materials (e.g., metal such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof, or a metal silicide such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or a combination thereof) and/or semiconductor materials (e.g., polycrystalline or amorphous semiconductor material including at least one elemental semiconductor element or at least one compound semiconductor material). Alternatively or additionally, the charge storage layer 54 may comprise an insulating charge trapping material, such as one or more silicon nitride segments. Alternatively, the charge storage layer 54 may comprise conductive nanoparticles such as metal nanoparticles, which can be, for example, ruthenium nanoparticles. The charge storage layer 54 can be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing electrical charges therein. The thickness of the charge storage layer 54 can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.
The tunneling dielectric layer 56 includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. The charge tunneling may be performed through hot-carrier injection or by Fowler-Nordheim tunneling induced charge transfer depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, the tunneling dielectric layer 56 can include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly known as an ONO stack. In one embodiment, the tunneling dielectric layer 56 can include a silicon oxide layer that is substantially free of carbon or a silicon oxynitride layer that is substantially free of carbon. The thickness of the tunneling dielectric layer 56 can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.
The optional first semiconductor channel layer 601 includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the first semiconductor channel layer 601 includes amorphous silicon or polysilicon. The first semiconductor channel layer 601 can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the first semiconductor channel layer 601 can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. A memory cavity 49′ is formed in the volume of each memory opening 49 that is not filled with the deposited material layers (52, 54, 56, 601).
Referring to
Each remaining portion of the first semiconductor channel layer 601 can have a tubular configuration. The charge storage layer 54 can comprise a charge trapping material or a floating gate material. In one embodiment, each charge storage layer 54 can include a vertical stack of charge storage regions that store electrical charges upon programming. In one embodiment, the charge storage layer 54 can be a charge storage layer in which each portion adjacent to the sacrificial material layers 42 constitutes a charge storage region.
A surface of the pedestal channel portion 11 (or a surface of the semiconductor material layer 10 in case the pedestal channel portions 11 are not employed) can be physically exposed underneath the opening through the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity 49′ can be vertically recessed so that the recessed semiconductor surface underneath the memory cavity 49′ is vertically offset from the topmost surface of the pedestal channel portion 11 (or of the semiconductor material layer 10 in case pedestal channel portions 11 are not employed) by a recess distance. A tunneling dielectric layer 56 is located over the charge storage layer 54. A set of a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56 in a memory opening 49 constitutes a memory film 50, which includes a plurality of charge storage regions (comprising portions of the charge storage layer 54) that are insulated from surrounding materials by the blocking dielectric layer 52 and the tunneling dielectric layer 56. In one embodiment, the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 can have vertically coincident sidewalls.
Referring to
The materials of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 are collectively referred to as a semiconductor channel material. In other words, the semiconductor channel material is a set of all semiconductor material in the first semiconductor channel layer 601 and the second semiconductor channel layer 602.
Referring to
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Referring to
Excess portions of the deposited semiconductor material can be removed from above the top surface of the topmost insulating layer 32, for example, by chemical mechanical planarization (CMP) or a recess etch. Each remaining portion of the semiconductor material having a doping of the second conductively type constitutes a drain region 63. The horizontal portion of the second semiconductor channel layer 602 located above the top surface of the topmost insulating layer 32 can be concurrently removed by a planarization process. Each remaining portion of the second semiconductor channel layer 602 can be located entirety within a memory opening 49 or entirely within a support opening 19.
Each remaining portion of the doped semiconductor material having a doping of the second conductivity type constitutes a drain region 63. Each adjoining pair of a first semiconductor channel layer 601 and a second semiconductor channel layer 602 can collectively form a vertical semiconductor channel 60 through which electrical current can flow when a vertical NAND device including the vertical semiconductor channel 60 is turned on. A tunneling dielectric layer 56 is surrounded by a charge storage layer 54, and laterally surrounds a portion of the vertical semiconductor channel 60. Each adjoining set of a tunneling dielectric layer 56, a charge storage layer 54, and a blocking dielectric layer 52 collectively constitute a memory film 50, which includes a vertical stack of memory elements that can store a respective data bit with a macroscopic retention time. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device such as a retention time in excess of 24 hours. In alternative embodiments, a blocking dielectric layer 52 may not be formed in each memory opening 49, and may be subsequently formed in backside recesses that are formed by removal of the sacrificial material layers 42 at a subsequent processing step.
Each combination of a memory film 50 and a vertical semiconductor channel 60 within a memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of a semiconductor channel 60, a tunneling dielectric layer 56, a plurality of memory elements comprising portions of the charge storage layer 54, and a blocking dielectric layer 52. Each combination of a pedestal channel portion 11 (if present), a memory stack structure 55, a dielectric core 62, and a drain region 63 within a memory opening 49 is herein referred to as a memory opening fill structure 58. Each combination of a pedestal channel portion 11 (if present), a memory film 50, a vertical semiconductor channel 60, a dielectric core 62, and a drain region 63 within each support opening 19 fills the respective support openings 19, and constitutes a support pillar structure.
Referring to
Each memory stack structure 55 includes a vertical semiconductor channel 60, which may comprise multiple semiconductor channel layers (601, 602), and a memory film 50. The memory film 50 may comprise a tunneling dielectric layer 56 laterally surrounding the vertical semiconductor channel 60, a vertical stack of charge storage regions (comprising portions of the charge storage layer 54) laterally surrounding the tunneling dielectric layer 56, and an optional blocking dielectric layer 52. While the present disclosure is described employing the illustrated configuration for the memory stack structure, the methods of the present disclosure can be applied to alternative memory stack structures including different layer stacks or structures for the memory film 50 and/or for the vertical semiconductor channel 60.
Referring to
A photoresist layer (not shown) can be applied over the contact-level dielectric layer 73, and is lithographically patterned to form openings in areas between clusters of memory stack structures 55. The pattern in the photoresist layer can be transferred through the contact-level dielectric layer 73, the alternating stack (32, 42) and/or the retro-stepped dielectric material portion 65 employing an anisotropic etch to form backside trenches 79, which vertically extend from the top surface of the contact-level dielectric layer 73 at least to the top surface of the substrate (9, 10), and laterally extend through the memory array region 100 and the staircase region 300.
In one embodiment, the backside trenches 79 can laterally extend along a first horizontal direction hd1 and can be laterally spaced apart among one another along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1. The memory stack structures 55 can be arranged in rows that extend along the first horizontal direction hd1. The drain-select-level isolation structures 72 can laterally extend along the first horizontal direction hd1. Each backside trench 79 can have a uniform width that is invariant along the lengthwise direction (i.e., along the first horizontal direction hd1). Each drain-select-level isolation structure 72 can have a uniform vertical cross-sectional profile along vertical planes that are perpendicular to the first horizontal direction hd1 that is invariant with translation along the first horizontal direction hd1. Multiple rows of memory stack structures 55 can be located between a neighboring pair of a backside trench 79 and a drain-select-level isolation structure 72, or between a neighboring pair of drain-select-level isolation structures 72. In one embodiment, the backside trenches 79 can include a source contact opening in which a source contact via structure can be subsequently formed. The photoresist layer can be removed, for example, by ashing.
Dopants of the second conductivity type can be implanted into portions of the semiconductor material layer 10 that underlie the backside trenches 79 to form source regions 61. The atomic concentration of the dopants of the second conductivity type in the source regions 61 can be in a range from 5.0×1018/cm3 to 2.0×1021/cm3, although lesser and greater atomic concentrations can also be employed. Surface portions of the semiconductor material layer 10 that extend between each source region 61 and adjacent memory opening fill structures 58 comprise horizontal semiconductor channels 59.
Referring to
The etch process that removes the second material selective to the first material and the outermost layer of the memory films 50 can be a wet etch process employing a wet etch solution, or can be a gas phase (dry) etch process in which the etchant is introduced in a vapor phase into the backside trenches 79. For example, if the sacrificial material layers 42 include silicon nitride, the etch process can be a wet etch process in which the first exemplary structure is immersed within a wet etch tank including phosphoric acid, which etches silicon nitride selective to silicon oxide, silicon, and various other materials employed in the art. The support pillar structures 20, the retro-stepped dielectric material portion 65, and the memory stack structures 55 provide structural support while the backside recesses 43 are present within volumes previously occupied by the sacrificial material layers 42.
Each backside recess 43 can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess 43 can be greater than the height of the backside recess 43. A plurality of backside recesses 43 can be formed in the volumes from which the second material of the sacrificial material layers 42 is removed. The memory openings in which the memory stack structures 55 are formed are herein referred to as front side openings or front side cavities in contrast with the backside recesses 43. In one embodiment, the memory array region 100 comprises an array of monolithic three-dimensional NAND strings having a plurality of device levels disposed above the substrate (9, 10). In this case, each backside recess 43 can define a space for receiving a respective word line of the array of monolithic three-dimensional NAND strings.
Each of the plurality of backside recesses 43 can extend substantially parallel to the top surface of the substrate (9, 10). A backside recess 43 can be vertically bounded by a top surface of an underlying insulating layer 32 and a bottom surface of an overlying insulating layer 32. In one embodiment, each backside recess 43 can have a uniform height throughout.
Physically exposed surface portions of the optional pedestal channel portions 11 and the semiconductor material layer 10 can be converted into dielectric material portions by thermal conversion and/or plasma conversion of the semiconductor materials into dielectric materials. For example, thermal conversion and/or plasma conversion can be employed to convert a surface portion of each pedestal channel portion 11 into a tubular dielectric spacer 116, and to convert each physically exposed surface portion of the semiconductor material layer 10 into a planar dielectric portion 616. In one embodiment, each tubular dielectric spacer 116 can be topologically homeomorphic to a torus, i.e., generally ring-shaped. As used herein, an element is topologically homeomorphic to a torus if the shape of the element can be continuously stretched without destroying a hole or forming a new hole into the shape of a torus. The tubular dielectric spacers 116 include a dielectric material that includes the same semiconductor element as the pedestal channel portions 11 and additionally includes at least one non-metallic element such as oxygen and/or nitrogen such that the material of the tubular dielectric spacers 116 is a dielectric material. In one embodiment, the tubular dielectric spacers 116 can include a dielectric oxide, a dielectric nitride, or a dielectric oxynitride of the semiconductor material of the pedestal channel portions 11. Likewise, each planar dielectric portion 616 includes a dielectric material that includes the same semiconductor element as the semiconductor material layer and additionally includes at least one non-metallic element such as oxygen and/or nitrogen such that the material of the planar dielectric portions 616 is a dielectric material. In one embodiment, the planar dielectric portions 616 can include a dielectric oxide, a dielectric nitride, or a dielectric oxynitride of the semiconductor material of the semiconductor material layer 10. Dopants in the drain regions 63, the source regions 61, and the semiconductor channels 60 can be activated during the anneal process that forms the planar dielectric portions 616 and the tubular dielectric spacers 116. Alternatively, an additional anneal process may be performed to active the electrical dopants in the drain regions 63, the source regions 61, and the semiconductor channels 60.
Referring to
The backside blocking dielectric layer 44 can be formed in the backside recesses 43 and on a sidewall of the backside trench 79. The backside blocking dielectric layer 44 can be formed directly on horizontal surfaces of the insulating layers 32 and sidewalls of the memory stack structures 55 within the backside recesses 43. If the backside blocking dielectric layer 44 is formed, formation of the tubular dielectric spacers 116 and the planar dielectric portion 616 prior to formation of the backside blocking dielectric layer 44 is optional. In one embodiment, the backside blocking dielectric layer 44 can be formed by a conformal deposition process such as atomic layer deposition (ALD). The backside blocking dielectric layer 44 can consist essentially of aluminum oxide. The thickness of the backside blocking dielectric layer 44 can be in a range from 1 nm to 15 nm, such as 2 to 6 nm, although lesser and greater thicknesses can also be employed.
The dielectric material of the backside blocking dielectric layer 44 can be a dielectric metal oxide such as aluminum oxide, a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one Lanthanide element, a dielectric oxide of a combination of aluminum, at least one transition metal element, and/or at least one Lanthanide element. Alternatively or additionally, the backside blocking dielectric layer 44 can include a silicon oxide layer. The backside blocking dielectric layer 44 can be deposited by a conformal deposition method such as chemical vapor deposition or atomic layer deposition. The backside blocking dielectric layer 44 is formed on the sidewalls of the backside trenches 79, horizontal surfaces and sidewalls of the insulating layers 32, the portions of the sidewall surfaces of the memory stack structures 55 that are physically exposed to the backside recesses 43, and a top surface of the planar dielectric portion 616. A backside cavity 79′ is present within the portion of each backside trench 79 that is not filled with the backside blocking dielectric layer 44.
Referring to
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A plurality of electrically conductive layers 46 can be formed in the plurality of backside recesses 43, and a continuous electrically conductive material layer 46L can be formed on the sidewalls of each backside trench 79 and over the contact-level dielectric layer 73. Each electrically conductive layer 46 includes a portion of the metallic barrier layer 46M and a portion of the metallic fill material layer 46F that are located between a vertically neighboring pair of dielectric material layers such as a pair of insulating layers 32. The continuous electrically conductive material layer 46L includes a continuous portion of the metallic barrier layer 46M and a continuous portion of the metallic fill material layer 46F that are located in the backside trenches 79 or above the contact-level dielectric layer 73.
Each sacrificial material layer 42 can be replaced with an electrically conductive layer 46. A backside cavity 79′ is present in the portion of each backside trench 79 that is not filled with the backside blocking dielectric layer 44 and the continuous electrically conductive material layer 46L. A tubular dielectric spacer 116 laterally surrounds a pedestal channel portion 11. A bottommost electrically conductive layer 46 laterally surrounds each tubular dielectric spacer 116 upon formation of the electrically conductive layers 46.
Referring to
Each electrically conductive layer 46 can function as a combination of a plurality of control gate electrodes located at a same level and a word line electrically interconnecting, i.e., electrically shorting, the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each electrically conductive layer 46 are the control gate electrodes for the vertical memory devices including the memory stack structures 55. In other words, each electrically conductive layer 46 can be a word line that functions as a common control gate electrode for the plurality of vertical memory devices.
In one embodiment, the removal of the continuous electrically conductive material layer 46L can be selective to the material of the backside blocking dielectric layer 44. In this case, a horizontal portion of the backside blocking dielectric layer 44 can be present at the bottom of each backside trench 79. In another embodiment, the removal of the continuous electrically conductive material layer 46L may not be selective to the material of the backside blocking dielectric layer 44 or, the backside blocking dielectric layer 44 may not be employed. The planar dielectric portions 616 can be removed during removal of the continuous electrically conductive material layer 46L. A backside cavity 79′ is present within each backside trench 79.
Referring to
If a backside blocking dielectric layer 44 is present, the insulating material layer can be formed directly on surfaces of the backside blocking dielectric layer 44 and directly on the sidewalls of the electrically conductive layers 46. If a backside blocking dielectric layer 44 is not employed, the insulating material layer can be formed directly on sidewalls of the insulating layers 32 and directly on sidewalls of the electrically conductive layers 46.
An anisotropic etch is performed to remove horizontal portions of the insulating material layer from above the contact-level dielectric layer 73 and at the bottom of each backside trench 79. Each remaining portion of the insulating material layer constitutes an insulating spacer 74. A backside cavity 79′ is present within a volume surrounded by each insulating spacer 74. A top surface of the semiconductor material layer 10 can be physically exposed at the bottom of each backside trench 79.
An upper portion of the semiconductor material layer 10 that extends between the source region 61 and the plurality of pedestal channel portions 11 constitutes a horizontal semiconductor channel 59 for a plurality of field effect transistors. The horizontal semiconductor channel 59 is connected to multiple vertical semiconductor channels 60 through respective pedestal channel portions 11. The horizontal semiconductor channel 59 contacts the source region 61 and the plurality of pedestal channel portions 11. A bottommost electrically conductive layer 46 provided upon formation of the electrically conductive layers 46 within the alternating stack (32, 46) can comprise a select gate electrode for the field effect transistors. Each source region 61 is formed in an upper portion of the substrate (9, 10). Semiconductor channels (59, 11, 60) extend between each source region 61 and a respective set of drain regions 63. The semiconductor channels (59, 11, 60) include the vertical semiconductor channels 60 of the memory stack structures 55.
A backside contact via structure 76 can be formed within each backside cavity 79′. Each contact via structure 76 can fill a respective backside cavity 79′. The contact via structures 76 can be formed by depositing at least one conductive material in the remaining unfilled volume (i.e., the backside cavity 79′) of the backside trench 79. For example, the at least one conductive material can include a conductive liner 76A and a conductive fill material portion 76B. The conductive liner 76A can include a conductive metallic liner such as TiN, TaN, WN, TiC, TaC, WC, an alloy thereof, or a stack thereof. The thickness of the conductive liner 76A can be in a range from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed. The conductive fill material portion 76B can include a metal or a metallic alloy. For example, the conductive fill material portion 76B can include W, Cu, Al, Co, Ru, Ni, an alloy thereof, or a stack thereof.
The at least one conductive material can be planarized employing the contact-level dielectric layer 73 overlying the alternating stack (32, 46) as a stopping layer. If chemical mechanical planarization (CMP) process is employed, the contact-level dielectric layer 73 can be employed as a CMP stopping layer. Each remaining continuous portion of the at least one conductive material in the backside trenches 79 constitutes a backside contact via structure 76. The backside contact via structure 76 extends through the alternating stack (32, 46), and contacts a top surface of the source region 61. If a backside blocking dielectric layer 44 is employed, the backside contact via structure 76 can contact a sidewall of the backside blocking dielectric layer 44.
Alternatively, at least one dielectric material, such as silicon oxide, may be conformally deposited in the backside trenches 79 by a conformal deposition process. Each portion of the deposited dielectric material that fills a backside trench 79 constitutes a backside trench fill structure. In this case, each backside trench fill structure may fill the entire volume of a backside trench 79 and may consist essentially of at least one dielectric material. In this alternative embodiment, the source region 61 may be omitted, and a horizontal source line (e.g., direct strap contact) may contact an side of the lower portion of the semiconductor channel 60.
As shown in
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The first etch mask layer 77 can be patterned to form an array of openings 171 therethrough. For example, a photoresist layer (not shown) can be applied over the first etch mask layer 77, and can be patterned by lithographic exposure and development. Each of the openings 171 in the first etch mask layer 77 can be formed within the area of a respective one of the steps 48. In one embodiment, the number of opening 171 within the area of each step 48 can be at least the total number of electrically conductive layers 46 in the step 48. For example, the steps 48 can be vertically offset from each other by K times the vertical distance between top surfaces of a vertically neighboring pair of insulating layers 32, where K is an integer greater than 1, such as an integer in a range from 2 to 2N, and N is an integer in a range from 2 to 6. In the illustrated example, K is four, and each area of the step 48 includes at least K (e.g., four) openings 171 through the first etch mask layer 77.
Each horizontal bottom surface segment of the stepped surfaces of the retro-stepped dielectric material portion 65 overlies a respective horizontal step 48. Thus, each of the openings 171 in the first etch mask layer 77 can be formed within the area of a respective one of the horizontal bottom surface segments of the stepped surfaces of the retro-stepped dielectric material portion 65. In one embodiment, the number of opening 171 within the area of each horizontal bottom surface segment of the stepped surfaces of the retro-stepped dielectric material portion 65 can be at least the total number of electrically conductive layers 46 contacting the vertical sidewall segment extending downward from an edge of the respective horizontal bottom surface segment. For example, the horizontal bottom surface segments of the stepped surfaces of the retro-stepped dielectric material portion 65 can be vertically offset from each other by K times the vertical distance between top surfaces of a vertically neighboring pair of insulating layers 32, where K is an integer greater than 1, such as an integer in a range from 2 to 2N, and N is an integer in a range from 2 to 6. In the illustrated example, K is four, and each area of a horizontal bottom surface segment of the retro-stepped dielectric material portion 65 includes at least K (e.g., four) openings 171 through the first etch mask layer 77. In one embodiment, the openings 171 through the first etch mask layer 77 can be formed in an array configuration such as a two-dimensional array configuration. The photoresist layer can be removed, for example, by ashing.
Referring to
A set of via cavities 850 can be formed through each step 48 and through each horizontal bottom surface segment of the retro-stepped dielectric material portion 65. For example, a first set of via cavities 850 can be formed through a first step 48 and through first horizontal bottom surface segment of the retro-stepped dielectric material portion 65, a second set of via cavities 850 can be formed through a second step 48 and through a second horizontal bottom surface segment of the retro-stepped dielectric material portion 65, etc. Each set of via cavities 850 extending through a respective step 48 and horizontal bottom surface segment of the retro-stepped dielectric material portion 65 can include more than one (i.e., a plurality) of via cavities 850. For example, each set of via cavities 850 can include a respective first via cavity, a respective second via cavity, etc. Each set of via cavities 850 includes at least K via cavities 850, in which K is an integer greater than 1.
For example, a first via cavity 85A, a second via cavity 85B, a third via cavity 85C, and a fourth via cavity 85D of each set of via cavities 850 (e.g., 85A, 85B, 85C, 85D) extend through a step 48 and a horizontal bottom surface segment of the retro-stepped dielectric material portion down to a top surface of a respective first electrically conductive layer 461 in each step 48 by performing the first anisotropic etch process. For example, a first via cavity 85A, a second via cavity 85B, a third via cavity 85C, and a fourth via cavity 85D of a first set of via cavities (85A, 85B, 85C, 85D) can extend through a first step 48A and a first one of the horizontal bottom surface segments, while a first via cavity 85A, a second via cavity 85B, a third via cavity 85C, and a fourth via cavity 85D of a second set of via cavities (85A, 85B, 85C, 85D) can extend through a second step 48B and a second one of the horizontal bottom surface segments, etc. Generally, each set of via cavities 850 vertically extending through a common step 48 and a common horizontal bottom surface segment of the retro-stepped dielectric material portion 65 includes at least a respective first via cavity 85A and a respective second via cavity 85B. The first etch mask layer 77 may be consumed during the first anisotropic etch process, or may be removed after the first anisotropic etch process, for example, by ashing.
While the present disclosure is described employing an embodiment in which each step 48 includes four electrically conductive layers 46 and in which vertical surface segment of the retro-stepped dielectric material portion 65 contacts four insulating layers and a set of via cavities (85A, 85B, 85C, 85D) is formed through each horizontal bottom surface segment, embodiments are expressly contemplated herein in which each step 48 includes two, three, five or more electrically conductive layers 46, and each set of via cavities 850 vertically extending through a horizontal bottom surface segment of a retro-stepped dielectric material portion 65 includes two, three, five, or more via cavities 85. The number of via cavities 850 within each set of via cavities 850 vertically extending through each step 48 and through each a horizontal bottom surface segment of a retro-stepped dielectric material portion 65 is at least the same as the number of electrically conductive layers 46 in each step 48 and is at least he same as the number of insulating layers 32 that contacts a vertical sidewall segment that extends downward from an edge of the horizontal bottom surface segment of a retro-stepped dielectric material portion 65, i.e., can be at least the number K discussed above.
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In one embodiment, if each step 48 contains 2N pairs of an insulating layer 32 and an electrically conductive layer 46 and the vertical sidewall segment of the retro-stepped dielectric material portion extends over 2N pairs of an insulating layer 32 and an electrically conductive layer 46, then the even-numbered via cavities (85A, 85D) can be vertically extended by over 2N−1 pairs of an insulating layer 32 and an electrically conductive layer 46. In the illustrated example, N is 2, and the second anisotropic etch process vertically extends the even-numbered via cavities (85B, 85D) through two electrically conductive layers 46 and two insulating layers 32. In one embodiment, the thickness of the first sacrificial etch mask layer 161 can be selected to be collaterally etched during the second anisotropic etch process. Thus, the first sacrificial etch mask layer 161 can be removed concurrently with vertical extension of the even-numbered via cavities (85A, 85D). For example, the first sacrificial etch mask layer 161 can have the same material as the insulating layers 32, and can have a thickness that is the sum of 2N−1 times the thickness of an insulating layer 32 and a thickness that corresponds to the collateral etch rate of the material of the first sacrificial etch mask layer 161 during etching of 2N−1 of electrically conductive layers 46.
Referring to
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Openings 174 can be formed through the second sacrificial etch mask layer 162 by applying and lithographically patterning a photoresist layer (not shown) over the second sacrificial etch mask layer 162, and by transferring the pattern of the openings in the photoresist layer through the second sacrificial etch mask layer 162. The photoresist layer can be subsequently removed, for example, by ashing. The pattern of the openings 174 through the second sacrificial etch mask layer 162 can be selected such that openings 174 through the second sacrificial etch mask layer 162 overlie one half of the sacrificial via cavity fill structures (181, 182) that fill odd-numbered via cavities and one half of the sacrificial via cavity fill structures (181, 182) that fill even-numbered via cavities. The complementary one half of the sacrificial via cavity fill structures (181, 182) that fill odd-numbered via cavities and the complementary one half of the sacrificial via cavity fill structures (181, 182) that fill even-numbered via cavities are covered by the second sacrificial etch mask layer 162.
Referring to
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In one embodiment, if each step 48 contains 2N pairs of an insulating layer 32 and an electrically conductive layer 46 and if each vertical sidewall segment of the retro-stepped dielectric material portion extends over 2N pairs of an insulating layer 32 and an electrically conductive layer 46, then the vacant via cavities 850 can be vertically extended by over 2N−2 pairs of an insulating layer 32 and an electrically conductive layer 46. In the illustrated example, N is 2, and the third anisotropic etch process vertically extends the vacant via cavities 850 through an electrically conductive layer 46 and an insulating layer 32. In one embodiment, the thickness of the second sacrificial etch mask layer 162 can be selected to be collaterally etched during the third anisotropic etch process. Thus, the second sacrificial etch mask layer 162 can be removed concurrently with vertical extension of the vacant via cavities 850. For example, the second sacrificial etch mask layer 162 can have the same material as the insulating layers 32, and can have a thickness that is the sum of 2N−2 times the thickness of an insulating layer 32 and a thickness that corresponds to the collateral etch rate of the material of the second sacrificial etch mask layer 162 during etching of 2N−2 of electrically conductive layers 46.
Generally, the processing steps of
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Each contiguous combination of a layer contact via structure 86 and a layer contact dielectric spacer 82 constitutes a laterally-isolated contact structure (86, 82). Each via cavity 850 vertically extends to a respective one of the electrically conductive layers 46. While two patterns of four laterally-isolated contact structures (86, 82) are expressly illustrated in
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Referring to all drawings and according to various embodiments of the present disclosure, a three-dimensional memory device is provided, which comprises: an alternating stack of insulating layers 32 and electrically conductive layers 46 containing a terrace region comprising a plurality of steps 48, memory stack structures 55 extending through the alternating stack (32, 46), a retro-stepped dielectric material portion 65 overlying terrace region of the alternating stack, first laterally-isolated contact structures (82A, 86A) each including a respective first contact via structure 86A and a respective first dielectric spacer 82A, wherein the respective first contact via structure 86A contacts a top surface of a respective upper electrically conductive layer 46A of the electrically conductive layers 46 in the respective step 48, and the respective first dielectric spacer 82A extends through the retro-stepped dielectric material portion 65 and does not contact any of the electrically conductive layers 46 other than the respective upper electrically conductive layer 46A in the respect step 48, and second laterally-isolated contact structures (82B, 86B) including a respective second contact via structure 86B and a respective second dielectric spacer 82B, wherein the respective second contact via structure 86B contacts a top surface of a respective lower electrically conductive layer 46B of the electrically conductive layers 46 in the respective step 48, and the respective second dielectric spacer 82B extends through the retro-stepped dielectric material portion 65 and through the respective upper electrically conductive layer 46, and contacts the respective lower electrically conductive layer 46B.
Additional laterally-isolated contact structures {(82C, 86C), (82D, 86D)} including a respective additional contact via structure (86C, 86D) and a respective additional dielectric spacer (82C, 82D) can be provided. The respective additional contact via structure (86C, 86D) contact top surfaces of respective additional electrically conductive layer (46C, 46D) of the electrically conductive layers 46, and the respective additional dielectric spacers (82C, 82D) extend through the retro-stepped dielectric material portion 65 and respective additional electrically conductive layers (46A, 46C, or 46B) and contact the respective additional electrically conductive layers (46C, 46D).
In one embodiment, the respective second dielectric spacer 82B extends through a via cavity 85B and contacts a sidewall of the upper electrically conductive layer 46A exposed in the via cavity 85B. In one embodiment, the respective second dielectric spacer 82B contacts a sidewall of a respective one of the insulating layers 32 exposed in the via cavity 85B.
In one embodiment, the first dielectric spacers and the second dielectric spacers comprise a same dielectric material and have annular top surfaces located within a horizontal plane located above a top surface of the retro-stepped dielectric material portion 65. In one embodiment, the first contact via structures 86A and the second contact via structures 86B have top surfaces located within the horizontal plane. In one embodiment, each contact via structure 86 can have a top surface within the horizontal plane.
In one embodiment, an annular bottom surface of the respective first dielectric spacer 82A contacts a top surface of the respective upper electrically conductive layer 46A, and an annular bottom surface of the respective second dielectric spacer 82B contacts the respective lower electrically conductive layer 46B. In one embodiment, a cylindrical portion of an outer sidewall of the respective second dielectric spacer 82B contacts a cylindrical surface of the respective upper electrically conductive layer 46A exposed in the via cavity 85B.
In one embodiment, the respective second dielectric spacer 82B contacts cylindrical sidewalls of at least two upper electrically conductive layers (46A, 46C) of the electrically conductive layers 46 exposed in the via cavity 85B.
In one embodiment, the three-dimensional memory device comprises third laterally-isolated contact structures (82C, 86C) including a respective third contact via structure 86C and a respective third dielectric spacer 82C, wherein the respective third contact via structure 86C contacts a top surfaces of a respective third electrically conductive layer 46C of electrically conductive layers 46, and the respective third dielectric spacer 82C extends through the retro-stepped dielectric material portion 65.
In one embodiment, the retro-stepped dielectric material portion 65 comprises a contiguous set of surfaces that includes horizontal bottom surface segments and vertical surface segments, the horizontal bottom surface segments are vertically spaced apart from each other and are laterally spaced apart from each other; and each of the horizontal bottom surface segments other than a bottommost one of the horizontal bottom surface segments is adjoined to a respective pair of vertical surfaces segments of the vertical surface segments of the retro-stepped dielectric material portion 65.
In one embodiment, each of the insulating layers 32 contacts has a respective sidewall that contacts a respective one of the vertical sidewall segments of the retro-stepped dielectric material portion 65, and each of electrically conducive layers 46 contacts the retro-stepped dielectric material portion 65, or is laterally spaced from the retro-stepped dielectric material portion 65 by a respective backside blocking dielectric layer 44. In one embodiment, one the vertical sidewall segments of the retro-stepped dielectric material portion 65 contacts sidewalls of at least two insulating layers 32 of the insulating layers (32, 46).
In one embodiment, the alternating stack (32, 46) has a vertical periodicity that is the same as a vertical separation distance between top surfaces of a vertically neighboring pair of insulating layers 32 within the alternating stack (32, 46); top surfaces of the first electrically conductive layers 46A are vertically offset from each other by multiples of K times the vertical periodicity, wherein K is an integer in a range from 2 to 2N, and wherein N is an integer in a range from 2 to 6; and top surfaces of the second electrically conductive layers 46B are vertically offset from each other multiples of K times the vertical periodicity.
In one embodiment, each of the memory stack structures 55 comprises a memory film 50 and a vertical semiconductor channel 60 which vertically extends through each layer within the alternating stack (32, 46).
The various embodiments of the present disclosure provide a compact terrace region in the staircase region 300 in which multiple contact via structures can be formed within the area of each step 48. The number of steps 48 can be reduced relative to prior art terrace regions to simplify and reduce the number of steps in the process of forming the staircase region 300. The total area of the staircase region 300 can be reduced to increase the device density in the three-dimensional memory device.
Referring to
In one embodiment, the alternating stack (32, 42) has a vertical periodicity that is the same as a vertical separation distance between top surfaces of a vertically neighboring pair of insulating layers within the alternating stack (32, 42). In one embodiment, a neighboring pair of horizontal bottom surface segments that is adjoined to each other by a vertical surface segment is vertically spaced apart from each other by Q times the vertical periodicity, wherein Q is an integer in a range from 2 to 16. While the integer Q is 2 in the illustrated example of
Generally, the stepped surfaces of the alternating stack (32, 42) in the second exemplary structure include a plurality of horizontal surfaces that are laterally spaced apart along the first horizontal direction (e.g., word line direction) hd1, laterally extend along the second horizontal direction (e.g., bit line direction) hd2 that is perpendicular to the first horizontal direction hd1, and are interlaced with the plurality of vertical surfaces. Each of the horizontal surfaces within the stepped surfaces may have two parallel edges that laterally extend along the second horizontal direction hd2 and are laterally spaced apart from each other by a uniform spacing therebetween.
In the embodiment illustrated in
Each vertical surface within the plurality of vertical surfaces of the stepped surfaces laterally extends straight along the second horizontal direction hd2 between the first backside trench fill structure (74, 76) and the second backside trench fill structure (74, 76). In one embodiment, the stepped surfaces continuously extend from a bottommost layer within the alternating stack (32, 42) to a topmost layer within the alternating stack (32, 42). The stepped surfaces comprise a plurality of horizontal surfaces that are interlaced with and adjoined to the plurality of vertical surfaces. Each horizontal surface within the plurality of horizontal surfaces of the stepped surfaces has a respective uniform width along the first horizontal direction hd1 and laterally extends along the second horizontal direction hd2 between the first backside trench fill structure (74, 76) and the second backside trench fill structure (74, 76).
In one embodiment, the retro-stepped dielectric material portion 65 comprises a contiguous set of surfaces that includes horizontal bottom surface segments and vertical surface segments. In one embodiment, the horizontal bottom surface segments are vertically spaced apart from each other and are laterally spaced apart from each other. In one embodiment, each of the horizontal bottom surface segments other than a bottommost one of the horizontal bottom surface segments is adjoined to a respective pair of vertical surfaces segments of the vertical surface segments of the retro-stepped dielectric material portion 65.
In one embodiment, the alternating stack (32, 42) has a vertical periodicity that is the same as a vertical separation distance between top surfaces of a vertically neighboring pair of insulating layers within the alternating stack (32, 42). In one embodiment, a neighboring pair of horizontal bottom surface segments that is adjoined to each other by a vertical surface segment is vertically spaced apart from each other by Q times the vertical periodicity, wherein Q is an integer in a range from 2 to 16.
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Generally, a combination of an alternating stack (32, 46) of insulating layers and electrically conductive layers 46, memory stack structures 55, and a retro-stepped dielectric material portion 65 can be formed over a substrate (9, 10). The memory stack structures 55 vertically extend through the alternating stack (32, 46). The alternating stack (32, 46) comprises stepped surfaces that continuously extend from a bottommost layer of the alternating stack (32, 46) to a topmost layer of the alternating stack (32, 46). The retro-stepped dielectric material portion 65 overlies the stepped surfaces of the alternating stack (32, 46).
In the embodiment illustrated in
In one embodiment, a first backside trench fill structure (74, 76) and a second backside trench fill structure (74, 76) can be located directly on a respective sidewall of the alternating stack (32, 46). The first backside trench fill structure (74, 76) laterally extends along the first horizontal direction hd1 and contacts first sidewalls of each layer within the alternating stack (32, 46). The second backside trench fill structure (74, 76) laterally extends along the first horizontal direction hd1 and contacts second sidewalls of each layer within the alternating stack (32, 46). A set of stepped surfaces of the alternating stack (32, 46) can be provided between the first backside trench fill structure (74, 76) and the second backside trench fill structure (74, 76). The set of stepped surfaces comprise a plurality of horizontal surfaces and a plurality of vertical surfaces. Each vertical surface within the plurality of vertical surfaces of the stepped surfaces laterally extends straight along the second horizontal direction hd2 between the first backside trench fill structure (74, 76) and the second backside trench fill structure (74, 76).
In one embodiment, the stepped surfaces continuously extend from a bottommost layer within the alternating stack (32, 46) to a topmost layer within the alternating stack (32, 42). The stepped surfaces comprise a plurality of horizontal surfaces that is interlaced with, and adjoined to, the plurality of vertical surfaces. Each horizontal surface within the plurality of horizontal surfaces of the stepped surfaces has a respective uniform width along the first horizontal direction hd1 and laterally extends along the second horizontal direction hd2 between the first backside trench fill structure (74, 76) and the second backside trench fill structure (74, 76).
In one embodiment, the stepped surfaces continuously extend from a bottommost layer within the alternating stack (32, 46) to a topmost layer within the alternating stack (32, 46). In one embodiment, the stepped surfaces comprise a plurality of horizontal surfaces that is interlaced with and adjoined to the plurality of vertical surfaces. In one embodiment, each horizontal surface within the plurality of horizontal surfaces of the stepped surfaces has a respective uniform width along the first horizontal direction hd1 and laterally extends along the second horizontal direction hd2 between the first backside trench fill structure (74, 76) and the second backside trench fill structure (74, 76).
In one embodiment, the retro-stepped dielectric material portion 65 comprises a contiguous set of surfaces that includes horizontal bottom surface segments and vertical surface segments. In one embodiment, the horizontal bottom surface segments are vertically spaced apart from each other and are laterally spaced apart from each other. In one embodiment, each of the horizontal bottom surface segments other than a bottommost one of the horizontal bottom surface segments is adjoined to a respective pair of vertical surfaces segments of the vertical surface segments of the retro-stepped dielectric material portion 65.
In one embodiment, the alternating stack (32, 46) has a vertical periodicity that is the same as a vertical separation distance between top surfaces of a vertically neighboring pair of insulating layers within the alternating stack (32, 46). In one embodiment, a neighboring pair of horizontal bottom surface segments that is adjoined to each other by a vertical surface segment is vertically spaced apart from each other by Q times the vertical periodicity, wherein Q is an integer in a range from 2 to 16.
Referring to
A first photoresist layer 187 can be applied over the hard mask layer 180, and can be lithographically patterned to form an array of openings between each neighboring pair of backside trench fill structures (74, 76). In one embodiment, Q rows of openings can be formed in the first photoresist layer 187 between each neighboring pair of backside trench fill structures (74, 76). Q is the integer that represents the number of insulating layers 32 or the number of electrically conductive layers 46 within each step. Generally, one, a plurality and/or each of the vertical steps of the stepped bottom surfaces of the retro-stepped dielectric material portion 65 may contact a respective set of vertically coincident sidewalls of Q insulating layers 32 and Q electrically conductive layers 46, or a respective set of vertically coincident sidewalls of Q insulating layers 32 and Q backside blocking dielectric layers 44.
In one embodiment, each row of openings in the first photoresist layer 187 may be arranged along the first horizontal direction hd1. In one embodiment, the Q rows of openings in the first photoresist layer 187 may be laterally spaced part from each other along the second horizontal direction hd2, and may be located between a respective neighboring pair of backside trench fill structures (74, 76). In one embodiment, the Q rows of openings in the first photoresist layer 187 may be arranged as a rectangular array. In one embodiment, each row of openings in the first photoresist layer 187 may comprise at least M openings in which M is an integer greater than 2, such as an integer within a range from 2 to 256, such as from 2 to 512. In this case, the Q rows of openings in the first photoresist layer 187 may comprise a Q×M rectangular array of openings.
Referring to
Referring to
Generally, the anisotropic etch process employs the hard mask layer 180 as an etch mask, and etches the material of the retro-stepped dielectric material portion 65 selective to the material of the electrically conductive layers 46. In one embodiment, K rows of via cavities 85 can be formed between each neighboring pair of backside trench fill structures (74, 76) in a plan view. In one embodiment, K equals to Q. A first row of via cavities 85 of the K rows of via cavities 85 may include first via cavities 85A, a second row of via cavities 85 of the K rows of via cavities 85 may include second via cavities 85B, etc. In one embodiment, the first via cavities 85A may be arranged along a first horizontal direction hd1 in a first row, and the second via cavities 85B may be arranged along the first horizontal direction hd1 in a second row. The second row is laterally offset from the first row along the second horizontal direction hd2. While
A subset of the first via cavities 85A and the second via cavities 85B can be formed through the retro-stepped dielectric material portion 65. In one embodiment, each of such first via cavities 85A and such second via cavities 85B vertically extends through the retro-stepped dielectric material portion 65, and has a bottom surface that coincides with a top surface segment of a respective one of the electrically conductive layers 46 in each step.
In one embodiment, for each first horizontal surface selected from the plurality of horizontal surfaces of the set of stepped surfaces of the retro-stepped dielectric material portion 65 that vertically extends from a bottommost layer within the alternating stack (32, 46) to a topmost layer within the alternating stack (32, 46), at least one of the first via cavities 85A vertically extends through the first horizontal surface, and at least one of the second via cavities 85B vertically extends through the first horizontal surface.
Referring to
An anisotropic etch process can be performed to vertically extend an unmasked subset of the via cavities 85 (such as the second via cavities 85B). The anisotropic etch process that etches a respective pair of the electrically conductive layer 46 and the insulating layer 32 underneath each second via cavity 85B while the patterned etch mask layer 197 masks the first via cavities 85A. The second via cavities 85B can be vertically extended through one electrically conductive layer 46 and through one insulating layer 32, and may stop on a respective underlying electrically conductive layer 46. In this case, each second via cavity 85B may be vertically extended by a sum of a thickness of an electrically conductive layer 46 and a thickness of an insulating layer 32. Generally, each second via cavities 85B can be vertically extended through a respective pair of an electrically conductive layer 46 and an insulating layer 32 while the first via cavities 85A are masked by the patterned etch mask layer 197. A top surface of a respective underlying electrically conductive layer 46 is physically exposed underneath each of the second via cavities 85B after the anisotropic etch process.
Referring to
Referring to
An anisotropic etch process (e.g., a sidewall spacer etch process) can be performed to remove horizontally-extending portions of the dielectric material layer. Each remaining cylindrical portion of the dielectric material layer constitutes a dielectric spacer 82. The dielectric spacers 82 comprise first dielectric spacers 82A that are formed at a periphery of a respective one of the first via cavities 85A, second dielectric spacers 82B that are formed at a periphery of a respective one of the second via cavities 85B, etc. If Q rows of via cavities 85 including Q types of via cavities 85 each vertically extending through a different number (including at least 0 and 1) of electrically conductive layers 46 are provided between a neighboring pair of backside trench fill structures (74, 76), then Q types of dielectric spacers 82 each vertically extending through a different number (including at least 0 and 1) of electrically conductive layers 46 can be formed.
In one embodiment, each first dielectric spacer 82A vertically extends through the retro-stepped dielectric material portion 65 and contacts no more than a respective single electrically conductive layer 46 of the insulating layers of the alternating stack (32, 46). In one embodiment, each second dielectric spacer 82B vertically extends through the retro-stepped dielectric material portion 65 and contacts an annular top surface segment of a respective first electrically conductive layer 46 of the electrically conductive layers 46 of the alternating stack (32, 46) and a cylindrical surface of a respective second electrically conductive layer 46 of the electrically conductive layers 46 of the alternating stack (32, 46) that overlies the respective first electrically conductive layer 46. Each second dielectric spacer 82B vertically extends through one electrically conducive layer 46 and contacts a top surface of another one underlying electrically conductive layer 46 in the same step.
Referring to
Alternatively, the hard mask layer 180 may be removed by CMP using the underlying contact-level dielectric layer 73 as a polish stop. In this case, the dielectric spacers 82 do not protrude above the underlying contact-level dielectric layer 73.
A photoresist layer (not shown) can be applied over the contact-level dielectric layer 73, and can be lithographically patterned to form openings over the drain regions 63 of the memory opening fill structures 58. An anisotropic etch process can be performed to form drain contact via cavities 87 over the drain regions 63 underneath each opening in the photoresist layer. The photoresist layer can be subsequently removed, for example, by ashing. A top surface of a drain region 63 can be physically exposed at the bottom of each drain contact via cavity 87.
Referring to
Remaining portions of the at least one conductive material that fill remaining voids in the via cavities 85 comprise contact via structures, which are herein referred to as layer contact via structures 86. Each layer contact via structure 86 contacts a top surface of a respective one of the electrically conductive layers 46 (e.g., word line or select gate line). Remaining portions of the at least one conductive material in the drain contact via cavities 87 comprise drain contact via structures 88. Remaining portions of the at least one conductive material in the optional peripheral via cavities extending to the semiconductor devices 700 comprise optional peripheral contact via structures 8P.
Each contiguous combination of a dielectric spacer 82 and a layer contact via structure 86 constitutes a laterally-isolated contact structure (82, 86). The laterally-isolated contact structures (82, 86) comprise first laterally-isolated contact structures (82A, 86A) that are formed in the first via cavities 85A and second laterally-isolated contact structures (82B, 86B) that are formed in the second via cavities 85B. Each of the first laterally-isolated contact structures (82A, 86A) includes a respective first layer contact via structure 86A and a respective first dielectric spacer 82A. Each of the second laterally-isolated contact structures (82B, 86B) comprises a respective second layer contact via structure 86B and a respective second dielectric spacer 82B.
Each first dielectric spacer 82A vertically extends through the retro-stepped dielectric material portion 65 and contacts no more than a respective single electrically conductive layer 46 of the alternating stack (32, 46). Each first layer contact via structure 86A contacts a top surface segment of the respective single electrically conductive layer 46. Each second layer contact via structure 86B vertically extends through the retro-stepped dielectric material portion 65 and contacts an annular top surface segment of a respective first electrically conductive layer 46 of the electrically conductive layers 46 of the alternating stack (32, 46) and a cylindrical sidewall surface of a respective second electrically conductive layer 46 of the electrically conductive layers 46 of the alternating stack (32, 46) that overlies the respective first electrically conductive layer 46. In one embodiment, a periphery of the top surface segment of the respective first electrically conductive layer 46 coincides with an inner periphery of the annular top surface segment for each of the second laterally-isolated contact structures (82B, 86B).
In one embodiment, the first dielectric spacers 82A and the second dielectric spacers 82B have a same dielectric material composition, have a same lateral distance between a respective inner sidewall and a respective outer sidewall, and have top surfaces within the horizontal plane including the top surfaces of the first layer contact via structures 86A and the second layer contact via structures 86B (such as the horizontal plane including the top surface of the contact-level dielectric layer 73). In one embodiment, the first layer contact via structures 86A and the second layer contact via structures 86B have top surfaces located within a horizontal plane located at or above a topmost surface of the alternating stack (32, 46) (such as the horizontal plane including the top surface of the contact-level dielectric layer 73). In one embodiment, the first layer contact via structures 86A and the second layer contact via structures 86B have the same or different material composition than the electrically conductive layers 46.
Referring to
A second photoresist layer 199 can be formed over the patterning film 177 and the dielectric etch mask layer 178 (if present). The second photoresist layer 199 can be lithographically patterned with the same pattern as the pattern in the patterned etch mask layer 197 illustrated in
Referring to
A second anisotropic etch process described above with respect to
Referring to
Subsequently, the processing steps of
Referring to
As discussed above, embodiments of the present disclosure may be practiced with one or more vertical steps including sidewalls of Q insulating spacers 32 and Q sacrificial material layers 42 that are vertically coincident among one another. In this case, Q rows of via cavities 85 including Q types of via cavities 85 can be formed. Each type of via cavities 85 of the Q types of via cavities each vertically extends through a different number (including at least 0 and 1) of electrically conductive layers 46 provided between a neighboring pair of backside trench fill structures (74, 76).
Referring to
In the embodiments in which Q is greater than 2, the processing steps described with reference to
Referring to
Subsequently, the processing steps described with reference to
Each third dielectric spacer 82C vertically extends through the retro-stepped dielectric material portion 65 and contacts an annular top surface segment of a respective first electrically conductive layer 46 of the electrically conductive layers 46 of the alternating stack (32, 46), a cylindrical surface of a respective second electrically conductive layer 46 of the electrically conductive layers 46 of the alternating stack (32, 46) that overlies the respective first electrically conductive layer 46, and a cylindrical surface of a respective third electrically conductive layer 46 of the electrically conductive layers 46 of the alternating stack (32, 46) that overlies the respective second electrically conductive layer 46.
Referring to
Referring to all drawings and according to various embodiments of the present disclosure, a three-dimensional memory device includes an alternating stack (32, 46) of insulating layers 32 and electrically conductive layers 46 containing a terrace region (e.g., the staircase region 300) having a plurality of steps, memory stack structures 55 extending through the alternating stack, a retro-stepped dielectric material portion 65 overlying the terrace region, first laterally isolated contact structures (82A, 86A) including a respective first contact via structure 86A and a respective first dielectric spacer 82A, and second laterally isolated contact structures (82B, 86B) including a respective second contact via structure 86B and a respective second dielectric spacer 82B. The respective first contact via structure 86A contacts a top surface of a respective first electrically conductive layer 46 in the respective step of the plurality of steps. The respective second contact via structure 86B extends through the respective first electrically conductive layer 46 in the respective step and contacts a top surface of a respective second electrically conductive layer 46 which underlies the first electrically conductive layer 46 in the respective step.
In one embodiment, the respective first contact via structure 86A contacts a top surface segment of the respective single electrically conductive layer 46; and the respective second contact via structure 86B contacts a top surface segment of the respective first electrically conductive layer 46. In one embodiment, a periphery of the top surface segment of the respective first electrically conductive layer 46 coincides with an inner periphery of the annular top surface segment for each of the second laterally-isolated contact structures (82B, 86B).
In one embodiment, the plurality of steps in the terrace region comprise stepped surfaces that include a plurality of vertical surfaces that are laterally spaced apart along a first horizontal direction hd1 and laterally extend along a second horizontal direction hd2 that is perpendicular to the first horizontal direction. The respective second dielectric spacer 82B vertically extends through the retro-stepped dielectric material portion 65 and contacts an annular top surface segment of the respective second electrically conductive layer 46 and a cylindrical sidewall surface of the respective first electrically conductive layer 46. The respective first dielectric spacer 82A vertically extends through the retro-stepped dielectric material portion 65 and contacts only the single first electrically conductive layer 46 of the electrically conductive layers. The respective first contact via structure 86A contacts a top surface segment of the respective single first electrically conductive layer 46, and the respective second contact via structure 86B contacts a top surface segment of the respective second electrically conductive layer 46.
In one embodiment, the stepped surfaces include a plurality of horizontal surfaces that are laterally spaced apart along the first horizontal direction hd1, laterally extend along the second horizontal direction hd2, and are interlaced with the plurality of vertical surfaces. In one embodiment, for a first horizontal surface selected from the plurality of horizontal surfaces: one of the first laterally-isolated contact structures (82A, 86A) vertically extends to or through the first horizontal surface; and one of the second laterally-isolated contact structures (82B, 86B) vertically extends through the first horizontal surface. In one embodiment, the one of the second laterally-isolated contact structures (82B, 86B) is laterally offset from the one of the first laterally-isolated contact via structures 86 along the second horizontal direction hd2.
In one embodiment, the first laterally-isolated contact structures (82A, 86A) are arranged along the first horizontal direction hd1 in a first row; the second laterally-isolated contact structures (82B, 86B) are arranged along the first horizontal direction hd1 in a second row; and the second row is laterally offset from the first row along the second horizontal direction hd2.
In one embodiment, the first contact via structures 86A and the second contact via structures 86B have top surfaces located within a horizontal plane located at, or above, a topmost surface of the alternating stack (32, 46). In one embodiment, the first dielectric spacers 82A and the second dielectric spacers 82B have a same dielectric material composition, have a same lateral distance between a respective inner sidewall and a respective outer sidewall, and have top surfaces within the horizontal plane including the top surfaces of the first contact via structures 86A and the second contact via structures 86B.
In one embodiment, the first contact via structures 86A and the second contact via structures 86B have a same or different material composition than the electrically conductive layers 46.
In one embodiment, the three-dimensional memory device comprises: a first backside trench fill structure (74, 76) laterally extending along the first horizontal direction hd1 and contacting first sidewalls of each layer within the alternating stack (32, 46); a second backside trench fill structure (74, 76) laterally extending along the first horizontal direction hd1 and contacting second sidewalls of each layer within the alternating stack (32, 46), wherein each vertical surface within the plurality of vertical surfaces of the stepped surfaces laterally extends straight along the second horizontal direction hd2 between the first backside trench fill structure (74, 76) and the second backside trench fill structure (74, 76). In one embodiment, the stepped surfaces continuously extend from a bottommost layer within the alternating stack (32, 46) to a topmost layer within the alternating stack (32, 46); the stepped surfaces comprise a plurality of horizontal surfaces that is interlaced with, and adjoined to, the plurality of vertical surfaces; and each horizontal surface within the plurality of horizontal surfaces of the stepped surfaces has a respective uniform width along the first horizontal direction hd1 and laterally extends along the second horizontal direction hd2 between the first backside trench fill structure (74, 76) and the second backside trench fill structure (74, 76).
In one embodiment, the retro-stepped dielectric material portion 65 comprises a contiguous set of surfaces that includes horizontal bottom surface segments and vertical surface segments; the horizontal bottom surface segments are vertically spaced apart from each other and are laterally spaced apart from each other; and each of the horizontal bottom surface segments other than a bottommost one of the horizontal bottom surface segments is adjoined to a respective pair of vertical surfaces segments of the vertical surface segments of the retro-stepped dielectric material portion 65.
In one embodiment, the three-dimensional memory device further comprises third laterally-isolated contact structures (82C, 86C), each including a respective third contact via structure 86C and a respective third dielectric spacer 82C, wherein the respective third contact via structure extends through the first and the second electrically conductive layers 46 in the respective step and contacts a top surface of a third electrically conductive layer 46 of the electrically conductive layers underlying the first and second electrically conductive layers in the respective step.
The various embodiments of the present disclosure may be employed to provide a contact region 300 having a smaller area. By forming layer contact via structures 86 contacting different electrically conductive layers 46 through a same horizontal surface of a step, the lateral dimension of the contact region 300 along a horizontal direction can be reduced by a factor of Q, which is an integer greater than 1. Thus, the three-dimensional memory device can be formed with a higher areal device density.
Although the foregoing refers to particular preferred embodiments, it will be understood that the disclosure is not so limited. It will occur to those of ordinary skill in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the disclosure. Compatibility is presumed among all embodiments that are not alternatives of one another. The word “comprise” or “include” contemplates all embodiments in which the word “consist essentially of” or the word “consists of” replaces the word “comprise” or “include,” unless explicitly stated otherwise. Where an embodiment employing a particular structure and/or configuration is illustrated in the present disclosure, it is understood that the present disclosure may be practiced with any other compatible structures and/or configurations that are functionally equivalent provided that such substitutions are not explicitly forbidden or otherwise known to be impossible to one of ordinary skill in the art. All of the publications, patent applications and patents cited herein are incorporated herein by reference in their entirety.
This application is a continuation-in-part (CIP) application of U.S. application Ser. No. 16/999,388 filed on Aug. 21, 2020, the entire contents of which are incorporated herein by reference.
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| Number | Date | Country | |
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| Parent | 16999388 | Aug 2020 | US |
| Child | 17806390 | US |
