Patent Application
20060073635
In recent years, portable electronic devices such as mobile telephones and non-volatile memory media such as IC memory cards have become smaller and smaller. Along with this trend, there have been demands for devices and memory media having a smaller number of components and a smaller size. Accordingly, it is desired to develop a technique of effectively packaging semiconductor chips that are main components constituting the aforementioned electronic devices and memory media. Examples of such packages that satisfy the above demands include a chip scale package (CSP) that is comparable in size to a semiconductor chip, a multi-chip package (MCP)that accommodates a plurality of semiconductor chips in one package, and a three dimensional (3D) package that incorporates at least a smaller second package within a larger first package.
3D packages allow more semiconductor functions per unit of area of board space and more semiconductor functions per unit of volume of application space, as well as significant size and weight reductions. Including two or more die in one package decreases the number of components mounted on a given printed circuit board. 3D packages provide a single package for assembly, test and handling which reduces package cost.
3D packages also allow a low overall cost without requiring cutting edge technology, because a desired set of functions can be included within the 3D package without having to put all of the functions in a single IC chip. Also, because die to die interconnects can be made within the package, the package I/O and the printed circuit board (PCB) routing are simplified. Because multiple dies are included with the footprint of a single 3D package, the length and/or width of the PCB can be reduced.
The 3D package or MCP is realized by stacking and turning a plurality of semiconductor chips and/or packages into one package. This technique is represented by a stacked multi-chip package (S-MCP).
a shows the structure of a conventional S-MCP in which two semiconductor chips are stacked. As shown in
In the above conventional S-MCP, however, the upper semiconductor chip 6 must be smaller than the lower semiconductor chip 2. The upper semiconductor chip 6 should be small enough not to cover the electrodes of the lower semiconductor chip 2. On the other hand, if the upper semiconductor chip 6 is too much smaller than the lower semiconductor chip 2, the distance between the electrodes of the upper semiconductor chip 6 and the pads of the substrate 4 becomes too long to perform a proper wire bonding operation.
In the configuration described above, semiconductor chips of the same size (i.e., of the same type) cannot be stacked if both are to be wire bonded to the package substrate. As the sizes of the semiconductor chips that can be stacked are limited, the types of the semiconductor chips that can be employed in the S-MCP are also limited.
Other types of prior art stacked packages are shown in
Some embodiments include a method of electrically connecting a plurality of semiconductor chips in a vertical stack. The method includes providing a first semiconductor chip carried by a first package substrate, the first substrate having plural contacts on the upper surface thereof and positioning one of plural conductive bumps or spheres on each of the plural contacts of the first substrate. The method also includes providing a layer of non-conductive material overlying the first chip and exposed substrate, and partially covering the conductive spheres. A second semiconductor chip on a second package substrate is provided. The second substrate has exposed contacts on its lower surface. The second substrate is positioned on the layer so that the exposed contacts are in electrical contact with the conductive bumps or spheres.
In some embodiments, a package comprises a first semiconductor chip carried by a first package substrate, the first substrate having plural contacts on an upper surface; plural conductive spheres, one on each of the plural contacts of the first substrate; and a layer of non conducting material overlaying the first chip and the first substrate partially covering the conductive spheres. The device also includes a second semiconductor chip on a second substrate, the second substrate having exposed contacts on the lower surface wherein the second substrate is positioned on the layer so that the exposed contacts of the second substrate contact the conductive spheres.
In some embodiments, a vertical stack of semiconductor chips form a three dimensional package. The vertical stack has a first semiconductor chip wire bonded to a upper surface of a first substrate, a second semiconductor chip wire bonded to a second upper surface of a second substrate above the first semiconductor chip, wherein the second semiconductor chip is electrically connected to the first semiconductor chip by electrical paths through the second substrate. An electrically non-conductive layer is positioned between the first and second substrates, the layer containing cavities securing conductive spheres that electrically connect the second substrate to contacts on the upper surface of the first substrate and structurally connect the first substrate with the second substrate.
These features and other advantages of the disclosed subject matter will be readily apparent to one skilled in the art to which the disclosure pertains from a perusal or the claims, the appended drawings, and the following detailed description of the preferred embodiments.
a-1d are representations of prior art three dimensional multi-chip packages.
a-2d are representations of a method for making a three dimensional chip scale package according to an embodiment of the disclosed subject matter.
An embodiment of a method for making a three dimensional (3D) package of stacked semiconductors is shown in
As shown in
As illustrated in
The layer 230 may be formed by molding the compound directly over the first semiconductor chip 210 and substrate 211, in which case, a resin or similar material is poured onto the upper surface of the chip 210, substrate 211 and conductive spheres 231 and allowed to cure or harden. When the layer 230 is formed in this manner, the wires 212 are also advantageously encapsulated. In other embodiments, the layer 230 may also be machined, cast, etched or molded prior to or concurrently with the positioning of the chip 210, substrate 211 and conductive spheres 231. If the layer 230 is machined, cast, etched, or molded in advance, a cavity is formed to accommodate the bonding wires 212. The layer 230 also serves to bond the first substrate 211 to a second substrate. Such bonding may be achieved by using a material for the layer 230 that bonds to the second package substrate 221 or by applying an adhesive between the top surface of the layer 230 and the bottom surface of the second package substrate 221.
As shown in
An embodiment of the disclosed 3D package formed with a plurality of semiconductor chips in a vertical stack is shown in
A non-conductive layer 230 of material overlies the first semiconductor chip 210 and the exposed upper surface 211a of the first substrate 211 as shown in
As shown in
The second substrate 221 is positioned on the layer 230, and the layer 230 so constructed, enables the exposed contacts 225 of the second substrate 221 to contact the conductive spheres 231. A second layer 240 also overlies the exposed upper surface 221a of the second substrate 221 and encapsulates the second semiconductor chip 220. The second layer 240 may also have a uniform height. In stacks with more than two semiconductor chips, the second molding compound layer 240 may have the same characteristics of the first, except it will be located between the second substrate 221 and a third package substrate (not shown). Also, solder bumps or conductive spheres will electrically connect contacts on the upper surface 221a of the second package substrate 221 with contacts in the lower surface of the third substrate. While the embodiments described herein relate to double and triple stacking, any number of chips can be stacked in the described process.
The lower surface 211b of the first substrate 211 also has a plurality of contacts (not shown) that connect to additional conductive spheres that provide attachment and electrical connection for the CSP to a circuit board (not shown). For example, the package may be a ball grid array package with a rectangular array of solder balls on the lower surface 211b.
The result of the configuration and method described above is a 3D package that has a thinner vertical thickness and can provide more options in stacked configurations.
It will be understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated above in order to explain the nature of this disclosure may be made by those skilled in the art without departing from the principle and scope of the disclosure as recited in the appended claims.
