Claims
- 1. A three-terminal integrated circuit switching structure comprising:
- a semiconductor substrate of a first conductivity type;
- first and second electrically isolated wells of a second conductivity type formed in said substrate;
- a first MOS device formed in said first well, said first MOS device comprising source and drain regions of said first conductivity type and a channel region extending therebetween, a gate electrode disposed over said channel region, and an input contact region of said second conductivity type, said source and input contact regions being connected to a common input terminal; and
- a second MOS device formed in said second well, said second MOS device comprising source and drain regions of said first conductivity type and a channel region extending therebetween, a gate electrode disposed over said channel region, and an output contact region of said second conductivity type, said drain and output contact regions being connected to a common output terminal;
- the gate electrodes of said first and second MOS devices being connected to a common gate terminal;
- the drain region of said first MOS device being connected to the source region of said second MOS device;
- whereby the application of a predetermined gate potential to said gate electrodes will simultaneously turn on both of said MOS devices and drive said structure to a conductive state, and whereby the removal of said gate potential will turn off both of said MOS devices.
- 2. A three-terminal integrated circuit switching structure comprising:
- a semiconductor substrate of a first conductivity type;
- first and second adjacently disposed, electrically isolated wells of a second conductivity type formed in said substrate;
- a first MOS device formed in said first well, said first MOS device comprising source and drain regions of said first conductivity type and a channel region extending therebetween, a gate electrode disposed over said channel region, and an input contact region of said second conductivity type said source and input contact regions being connected to a common input terminal; and
- a second MOS device formed in said second well, said second MOS device comprising source and drain regions of said first conductivity type and a channel region extending therebetween, a gate electrode disposed over said channel region, and an output contact region of said second conductivity type, said drain and output contact regions being connected to a common output terminal;
- the gate electrodes of said first and second MOS device being connected to a common gate terminal;
- the drain region of said first MOS device being connected to the source region of said second MOS device;
- whereby the application of a predetermined gate potential to said gate electrodes will simultaneously turn on both of said MOS devices and drive said structure to a conductive state, and whereby the removal of said gate potential will turn off both of said MOS devices.
Parent Case Info
This application is a continuation of application Ser. No. 06/686,329 filed Dec. 26, 1984.
US Referenced Citations (5)
Continuations (1)
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Number |
Date |
Country |
Parent |
686329 |
Dec 1984 |
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