Through-silicon via and method for forming the same

Abstract

A method for forming a through-silicon via includes the steps of defining a groove in each chip of a wafer which has a plurality of semiconductor chips; applying liquid polymer on the wafer to fill the groove; forming an insulation layer on a sidewall of the groove through patterning the polymer; forming a metal layer to fill the groove which is formed with the insulation layer on the sidewall thereof; and back-grinding a backside of the wafer to expose the metal layer filled in the groove.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A through 1G are cross-sectional views illustrating process steps of a method for forming a through-silicon via in accordance with an embodiment of the present invention. They also depict the structure of a semiconductor device formed to have a through-silicon via.

DETAILED DESCRIPTION

In the present invention, a relatively flexible polymer which adheres to both the surface of a silicon through-hole but also to a metal or metallic substance that is deposited over the polymer coating a silicon surface, provides a flexible, mechanical interface between silicon and a metal or metallic filler, which can accommodate variations in thermal expansion coefficients between silicon and the metal or metallic substance to provides improved mechanical compliance. The polymer also forms an insulation layer between silicon and an electrolytic or metallic substance. Such a polymer is referred to herein as a polymer that has “mechanical compliance” or which is “mechanically compliant.” That is to say, in the present invention, after filling a vertical hole defined for forming a vertical connection with liquid polymer, through patterning the polymer to a desired shape using a photolithography process, an insulation layer is formed.

In this case, since the liquid polymer is applied by a method such as spin coating, etc., in the present invention, it is possible to reduce the cost of forming the insulation layer when compared to the conventional art in which the insulation layer is formed by an oxide layer or a nitride layer. Also, in the present invention, due to the fact that the insulation layer is formed by patterning polymer after filling the entire vertical hole using liquid polymer, the uniform thickness and low roughness of the insulation layer can be secured, and an adequate thickness for obtaining a satisfactory insulation characteristic can be secured.

A polymer is a substance that is mechanically flexible and softer or more pliable than an oxide layer or a nitride layer used as the insulation layer in the prior art. Therefore, in the present invention, by using a polymer between silicon and an electrolytic or metallic layer, it is possible to significantly reduce or even eliminate the fatigue fractures caused by a difference in thermal expansion coefficient between silicon and a metal. In other words, silicon and a metal undergo thermal expansion by the heat generated while a semiconductor chip operates, and as a result, a mechanical stress is produced. In this regard, because the polymeric insulation layer interposed between the silicon and the metal, is a relatively soft and flexible polymer having mechanical compliance, the polymer absorbs and dissipates the mechanical stress. Fracture of a package due to a fatigue can therefore be reduced.

In the oxide layer or the nitride layer which is used as the insulation layer in the conventional art, a crack starting from a defect produced therein is propagated into the silicon and causes a chip substrate or wafer to fracture. However, in the present invention, because the polymer is flexible, even when a defect is produced in the polymer, a crack is not propagated into the silicon. Therefore, using the present invention, the fracture of a chip due to the flaw of the insulation layer can be substantially prevented.

FIGS. 1A through 1F are cross-sectional views illustrating process steps of a method for forming a through-silicon via in accordance with an embodiment of the present invention.

Referring to FIG. 1A, a photoresist layer is applied on a wafer 110, which can be used to make several semiconductor chips having through-silicon vias or “TSV” forming regions. Through conducting exposure and development processes for the photoresist layer 115, a first photoresist pattern 120 for exposing the TSV forming regions is formed on each chip. By etching the exposed TSV forming regions 128 using the first photoresist pattern 120 as an etch mask, one or more slots, holes or grooves 130, are defined and formed by etching as shown in FIG. 1A. As used herein, the terms “groove” and “grooves” should be construed to mean and include slots, grooves and holes, whether they extend part way through the wafer 110, or completely through the wafer 110.

Referring to FIG. 1B, after the first photoresist pattern 120 is used as an etch mask, it is removed by conducting a conventional process, such as O₂ plasma etching Then, a liquid polymer 140 is applied on the wafer 110 including the grooves 130 in the silicon wafer 110, as a material that forms an insulation layer 140a. The liquid polymer 140 is applied through processes, such as spin coating, which can be easily conducted and requires a process cost typically less than that required in an oxidization process.

Referring to FIG. 1C, through patterning the liquid polymer 140 applied in the grooves 130 in the silicon wafter 110, a polymer insulation layer 140a is formed, i.e., left remaining on the surface of the sidewall 141 of each groove 130 in the silicon wafer 110. Here, the patterning of the polymer 140 is conducted through a separate photolithographic process or, by exposing a photosensitive polymer to light in order to develop and thereby effectively remove such a polymer 140. The patterning of the polymer 140 can also be conducted by ablating a predetermined portion of the polymer 140 using a laser.

Referring to FIG. 1D, a thin film seed metal layer 150 is deposited on the wafer 110, including the polymer insulation layer 140a formed on the sidewall 141 of each groove 130. Next, a second photoresist pattern 160 for defining metal layer forming regions is formed on the seed metal layer 150. The second photoresist pattern 160 is formed to expose the grooves 130 and areas surrounding the grooves 130. As shown in FIG. 1E, using a process such as electroplating, a metal layer 170 is plated onto portions of the seed metal layer 150, which are exposed through the second photoresist pattern 160.

Still referring to FIG. 1E, the second photoresist pattern 160 used as a resist is removed through a conventional process. In succession, the portions of the seed metal layer 150, which are exposed due to the removal of the second photoresist pattern 160, are also removed.

Referring to FIG. 1F, the backside 112 of the wafer 110 is back-grinded so that the metal layer 170 filled in the groove 130 is exposed. In this way, as shown in FIG. 1G, a TSV 180 having a structure in which polymer 140a is interposed between the silicon of the wafer 110 and the metal 170. The polymer 140a acts as both an insulation layer and as a thermal stress absorber.

As is apparent from the above description, the through-silicon via 180 and the method for forming the same according to the present invention provide advantages in that, since an insulation layer 140a interposed between silicon and an electrolytic substance when forming a TSV 180 used for vertically stacking chips is made of an appropriate polymer, the cost of forming an insulation layer 140a can be reduced when compared to the prior art, in which the insulation layer comprises an oxide layer or a nitride layer. It is also possible to form an insulation layer having a uniform thickness and low roughness. In addition, an insulation characteristic can be secured, and an excellent mechanical characteristic can be secured whereby the fatigue fracture of a package can be prevented. As a result, the reliability of a stack package using a TSV can be improved.

In the drawings and specification, there has been disclosed a specific embodiment of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Claims

1. A semiconductor wafer having a through-silicon via, said semiconductor wafer comprising: a groove formed into a wafer; an insulation layer formed on a surface of the groove; and a metal filled in the groove, wherein the insulation layer is comprised of a mechanically compliant polymer.

2. A method for forming a through-silicon via in a semiconductor wafer, said method comprising the steps of: defining a groove in a wafer, said wafer capable of forming a plurality of semiconductor chips;applying a polymer onto the wafer to fill the groove;removing at least part of the polymer that fills the groove to form an insulation layer on a sidewall of the groove through patterning the polymer;applying a metal to fill the groove, which includes an insulation layer on a sidewall; andback-grinding a backside of the wafer to expose the metal layer filled in the groove.

3. The method as set forth in claim 2, wherein the step of defining a groove includes the steps of: forming on the wafer, a photoresist pattern for exposing a through-silicon via forming region on at least one chip;etching exposed portions, using the photoresist pattern as an etch mask; andremoving the photoresist pattern.

4. The method as set forth in claim 2, wherein the step of patterning the polymer uses a photolithographic process.

5. The method as set forth in claim 2, wherein the step of patterning of the polymer includes the step of exposing and developing a photosensitive polymer.

6. The method as set forth in claim 2, wherein the patterning of the polymer removes a portion of the polymer using a laser.

7. The method as set forth in claim 2, wherein the step of forming a metal layer comprises the sub steps of: depositing a seed metal layer in the groove, which includes the insulation layer and on the wafer;forming on the seed metal layer deposited on the wafer a photoresist pattern for exposing the groove and surrounding portions of the seed metal layer;plating a metal layer on exposed portions of the seed metal layer through an electroplating process; andremoving the photoresist pattern.