Claims
- 1. A memory cell comprising:
a thyristor device including doped regions of opposite polarity; a first word line providing read and write access to the memory cell; and a second word line located adjacent to and separated by an insulative material from at least one of the doped regions of the thyristor device and used for write operation to the memory cell by enhancing the switching of the thyristor device from a high conductance state to a low conductance state and from the low conductance state to the high conductance state.
- 2. The memory cell of claim 1, further comprising a transistor, wherein the read and write access is provided by the transistor with its gate forming at least part of the first word line.
- 3. The memory cell of claim 2, wherein the transistor is a MOSFET transistor.
- 4. The memory cell of claim 1, wherein the second word line enhances the switching of the thyristor device by substantially improving the switching speed of the thyristor device from the high conductance state to the low conductance state.
- 5. The memory cell of claim 1, wherein the second word line is adapted to enhance the switching of the thyristor device by substantially reducing the voltage requirement of the thyristor device for switching from the low conductance state to the high conductance state.
- 6. The memory cell of claim 1, wherein at least part of the cell is arranged in a vertical configuration extending above a substrate surface.
- 7. The memory cell of claim 1, wherein at least part of the cell is arranged in a vertical configuration extending below a substrate surface.
- 8. The memory cell of claim 1, wherein at least part of the cell is arranged in a planar configuration parallel to a substrate surface.
- 9. The memory cell of claim 8, wherein the substrate surface is part of a silicon-on-insulator substrate.
- 10. The memory cell of claim 2, wherein the transistor and the thyristor device are arranged in a planar configuration parallel to a substrate surface.
- 11. The memory cell of claim 10, wherein the substrate surface is part of a silicon-on-insulator substrate.
- 12. A memory array comprising:
a first and a second word line; and a plurality of memory cells, each memory cell comprising a thyristor device including doped regions of opposite polarity, wherein
the first word line providing read and write access to the memory cell; and a portion of the second word line located adjacent to and separated by an insulative material from at least one of the doped regions of the thyristor device and used for write operation to the memory cell by enhancing the switching of the thyristor device from a high conductance state to a low conductance state and from the low conductance state to the high conductance state.
- 13. The memory array of claim 12, wherein the memory cell further comprises a transistor, and wherein the read and write access is provided by the transistor with its gate forming at least part of the first word line.
- 14. The memory array of claim 13, wherein the transistor is a MOSFET transistor.
- 15. The memory array of claim 12, wherein the second word line enhances the switching of the thyristor device by substantially improving the switching speed of the thyristor device from the high conductance state to the low conductance state.
- 16. The memory array of claim 12, wherein the second word line enhances the switching of the thyristor device by substantially reducing the voltage requirement of the thyristor device for switching from the low conductance state to the high conductance state.
- 17. The memory array of claim 12, wherein at least part of the memory cell is arranged in a vertical configuration extending above a substrate surface.
- 18. The memory array of claim 12, wherein at least part of the memory cell is arranged in a vertical configuration extending below a substrate surface.
- 19. The memory array of claim 12, wherein at least part of the memory cell is arranged in a planar configuration parallel to a substrate surface.
- 20. The memory array of claim 19, wherein the substrate surface is part of a silicon-on-insulator substrate.
- 21. The memory array of claim 13, wherein the transistor and the thyristor device are arranged in a planar configuration parallel to a substrate surface.
- 22. The memory array of claim 21, wherein the substrate surface is part of a silicon-on-insulator substrate.
RELATED PATENT DOCUMENTS
[0001] This is a continuation of U.S. patent application Ser. No. 10/103,241, filed on Mar. 20, 2002 (STFD.003C3), which is a continuation of U.S. patent application Ser. No. 10/103,240, filed Mar. 20, 2002 (STFD.003C2), now U.S. Pat. No. 6,528,356, which is a continuation of U.S. patent application Ser. No. 09/666,825, filed on Sep. 21, 2000 (STFD.003C1), now U.S. Pat. No. 6,448,586, which is a continuation of Ser. No. 09/092,449, filed on Jun. 5, 1998 (STFD.003PA), now U.S. Pat. No. 6,229,161, to which priority is claimed under 35 U.S.C. §120.
Government Interests
[0002] The Government has certain rights in this invention which was made with Government support under contract MDA972-95-1-0017 awarded by the Defense Research Projects Agency.
Continuations (4)
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Number |
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10103241 |
Mar 2002 |
US |
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10777453 |
Feb 2004 |
US |
Parent |
10103240 |
Mar 2002 |
US |
Child |
10103241 |
Mar 2002 |
US |
Parent |
09666825 |
Sep 2000 |
US |
Child |
10103240 |
Mar 2002 |
US |
Parent |
09092449 |
Jun 1998 |
US |
Child |
09666825 |
Sep 2000 |
US |