Claims
- 1. A system comprising:
a built-in self-test (BIST) controller that stores a set of commands defining an algorithm for testing a memory module; a sequencer that receives the commands and issues one or more memory operations in accordance with the commands; and a memory interface that applies the memory operations to the memory module in accordance with physical characteristics of the memory module.
- 2. The system of claim 1, wherein the BIST controller comprises:
an algorithm memory that stores the set of commands as one of set of selectable memory test algorithms having associated commands; and an algorithm controller to retrieve the commands from the algorithm memory and issue the commands associated with the selected memory test algorithm to the sequencer.
- 3. The system of claim 2, wherein the BIST controller includes an interface to receive one or more additional memory test algorithms, wherein the algorithm controller delivers the additional memory test algorithm to the sequencer for application to the memory interface.
- 4. The system of claim 2, wherein the memory interface comprises one of a plurality of memory interfaces associated with respective memory modules, and the sequencer comprises one of a plurality of sequencers associated with respective subsets of the memory interfaces, and the algorithm controller issues each of the commands to the sequencers in parallel for application to the respective subsets of the memory interfaces.
- 5. The system of claim 4, further comprising a set of command data interconnects to communicate the commands from the BIST controller to the plurality of sequencers and a set of acknowledgement interconnects to communicate acknowledge signals from the plurality of sequencers to the BIST controller to indicate the completion of the commands.
- 6. The system of claim 1, wherein the sequencer controls an application speed of the memory operations to the memory interface in accordance with timing requirements of the memory module.
- 7. The system of claim 1, wherein the sequencer comprises:
a plurality of command controllers that implement the commands in accordance with a command protocol; and a command parser to parse each command to identify an operational code and a set of parameters based on the command protocol, wherein the command parser selectively invokes the command controllers based on the operational codes of the commands received from the BIST controller.
- 8. The system of claim 7, wherein when invoked the command controllers issue the memory operations to the memory interface by sequencing through address ranges defined by the respective commands
- 9. The system of claim 7, wherein the command controllers issue the memory operations by asserting signals to apply addresses and data to the memory interface based on the commands received from the BIST controller.
- 10. The system of claim 9, wherein the command controllers issue the memory operations by further asserting control signals to direct the memory interface to automatically store inverted data between least one of neighboring rows, neighboring columns, and neighboring row-column matrices based on the physical characteristics of the memory module.
- 11. The system of claim 9, wherein based on the physical characteristics of the memory module the memory interface translates the addresses specified by the sequencer for the memory operations.
- 12. The system of claim 11, wherein the memory module includes memory cells arranged in rows and columns, and the memory interface translates the addresses to fill the memory module in a row-wise or column-wise fashion as specified by the commands from the BIST controller.
- 13. The system of claim 9, wherein the commands specify a bit pattern to be written to the memory module, and the memory interface translates the data specified by the sequencer based on the specified bit pattern and the physical characteristics of the memory module.
- 14. The system of claim 1, wherein the memory interface comprises a data generation unit that receives data signals from the sequencer and generates transformed data signals based on the data signals and the physical characteristics of the memory module.
- 15. The system of claim 14, wherein, in response to a control signal received from the sequencer, the data generation unit automatically transforms the data to store inverted data within at least one of neighboring rows, neighboring columns, and neighboring row-column matrices of the memory module.
- 16. The system of claim 1, wherein the memory interface comprises an address generation unit that receives address signals from the sequencer and generates transformed address signals applied based an arrangement of rows and columns of the memory module.
- 17. The system of claim 1, wherein the memory interface comprises a comparator to compare data read from the memory module to data previously written to the memory module and set a state of a failure signal based on the comparison.
- 18. The system of claim 1, wherein the physical characteristics include at least one of a number of rows, a number of columns, and a number of row-column matrices of the memory module.
- 19. The system of claim 1, wherein the commands conform to a generalized command protocol that substantially define the test algorithm without regard to physical characteristics and timing requirements of the memory module.
- 20. The system of claim 19, wherein the command protocol defines a command syntax having a set of supported commands, and each command includes an operand and a set of parameters.
- 21. The system of claim 20, wherein at least one of the commands includes fields to specify an address range, one or more memory operations to apply over the address range, and a bit pattern for application to the memory module of the address range.
- 22. The system of claim 1, wherein the BIST controller, memory interface and sequencer are integrated within an electronic device.
- 23. A system comprising:
a plurality of memory modules; a built-in self-test (BIST) controller that stores an algorithm for testing the memory modules; and a plurality of sequencers that are respectively coupled to different subsets of the memory modules, wherein each subset of the memory module is selected to include the memory modules having common clock domains, and each sequencer controls the application of the test algorithm to the respective subset of memory modules in accordance with the common clock domain of that subset of memory modules.
- 24. The system of claim 23, further comprising a plurality of memory interfaces that are respectively coupled the memory modules, wherein each of the memory interfaces receive address and data signals generated by the sequencer based on the algorithm and translates the address and data signals in accordance with an arrangement of rows and columns of the respective memory module.
- 25. A device comprising:
first-level built-in, self-test (BIST) means for issuing commands that define a BIST algorithm for a plurality of distributed memory modules having different timing requirements and physical characteristics; second-level BIST means for processing the commands to generate sequences of memory operations in accordance with the timing requirements of the memory modules; and third-level BIST means for generating translated address and data signals from the memory operations based on the physical characteristics of the memory modules to apply the BIST algorithm to the distributed memory modules.
- 26. The device of claim 25, wherein the first-level BIST means comprises:
algorithm storage means for storing the commands as one of set of selectable memory test algorithms having associated commands; and algorithm control means for retrieving the commands from the algorithm memory and issue the commands associated with the selected memory test algorithm to the sequencer.
- 27. A method comprising:
issuing commands from a centralized BIST controller to a sequencer, wherein the commands define a memory test algorithm to be applied to a set of distributed memory modules without regard to physical characteristics or timing requirements of the memory modules; processing the commands with the sequencer to generate one or more sequences of memory operations in accordance with the timing requirements of the memory modules; and applying the memory operations to the distributed memory modules to test the memory modules.
- 28. The method of claim 27, further comprising translating address and data signals associated with the memory operations with memory interfaces coupled to each of the memory modules to generate translated address and data signals based on the physical characteristics of each of the memory modules, and wherein applying the memory operations comprises applying the translated address and data signals to test the memory modules.
- 29. The method of claim 27, further comprising selecting the memory test algorithm from one of a plurality of memory test algorithms stored within an algorithm memory.
- 30. The method of claim 28, wherein translating address and data signals comprises translating address and data signals with memory interfaces based on at least one of a number of rows of the respective memory module, a number of columns of the respective memory module, and a number of row-column matrices of the respective memory module.
- 31. The method of claim 27, wherein issuing commands comprising issuing commands in accordance with a command protocol that defines a set of supported commands having operands and a set of parameters that define the memory operations to be generated by the sequencer.
Parent Case Info
[0001] This application claims the benefit of U.S. Provisional Application Serial No. 60/456,452, entitled “An Apparatus and Method for a Memory Built-in Self-Test Engine,” filed Mar. 20, 2003.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60456452 |
Mar 2003 |
US |