This application claims the benefit of Taiwan application Serial No. 105129531, filed Sep. 12, 2016, the subject matter of which is incorporated herein by reference.
The invention relates in general to a time de-interleaving circuit and method, and more particularly to a time de-interleaving circuit and method capable of preventing information units from being inappropriately overwritten.
In general, before a Digital Video Broadcasting—Second Generation Terrestrial (DVB-T2) broadcast signal is transmitted, cell interleaving and time interleaving processes are performed on data to be transmitted to minimize effects that various types of interference has on transmitted data, so that the receiver may obtain correct transmitted data. After the signal is received at the receiver, time de-interleaving and cell de-interleaving processes are performed on the received signal to correctly decode the data.
In addition to adopting time de-interleaving to improve the resistance against impulsive interference, DVB-T2 also enhances channel transmission capabilities to satisfy transmission bandwidth requirements of high-definition resolution images and three-dimensional images. Meanwhile, DVB-T2 adopts a physical layer pipe (PLP) technology to provide flexibilities for different commercial modes, so as to further provide service-oriented response capabilities.
When a DVB-T2 receiver uses multiple PLPs, a part of received signals of the receiver provide data to individual PLPs (to be referred to as data PLP, formed by a plurality of information units), whereas another part provides data to all PLPs (to be referred to as common PLP, formed by a plurality of information units), e.g., center frequencies, single frequency network/multiple input single output (SFN/MISO) parameters and bandwidths. Conventional technologies may use following methods to access data PLP and common PLP.
In the first method, data PLP and common PLP are individually accessed using non-shared (i.e., separate) memory spaces. Although this method prevents access processes of data PLP and common PLP from interfering each other, sufficient spaces need to be individually provided for data PLP and common PLP. For example, a memory space having a capacity prepared for writing and reading data PLP of each PLP is 2×Memorydata_max (e.g., a storage space having 2×(219+215) information units), and a memory space having a capacity prepared for writing and reading common PLP of each PLP is 2×Memorycommon_max (e.g., a storage space having 2×216) information units. However, because the data size of each set of data PLP and the data size of each set of common PLP usually do not reach their maximum, particularly do not simultaneously reach their maximum, a part in each of the storage spaces of data PLP and common PLP is usually idle and wasted.
In the second method, data PLP and common PLP are accessed by using a shared memory space through ping-pong buffering. As shown from
(i) As shown in
(ii) As shown in
(iii) As shown in
(iv) As shown in
Known from
It is known from the above description that, when handling access of data PLP and common PLP, current technologies result in issues of either memory space waste or overwriting data that is not yet read out.
The invention is directed to a time de-interleaving circuit and a time de-interleaving method to reduce the memory capacity that a time de-interleaving process requires and to prevent data from being inappropriately overwritten.
The present invention discloses a time de-interleaving circuit located at a signal receiver of a communication system to perform a time de-interleaving process on an interleaved signal. The interleave signal includes a plurality of information units, which include a plurality of data units and a plurality of common units. According to an embodiment, the time de-interleaving circuit includes: a data unit access address generator, generating a plurality of data unit access addresses according to a first address sequence to accordingly access the data units in a memory; and a common unit access address generator, generating a plurality of common unit access addresses according to a second address sequence to accordingly access the common units in the memory. The first address sequence is a reverse sequence of the first address sequence.
The present invention further discloses a time de-interleaving method applied to a signal receiver of a communication system to perform a time de-interleaving process on an interleaved signal. The interleaved signal includes a plurality of information units, which include a plurality of data units and a plurality of common units. According to an embodiment, the method includes: generating a plurality of data unit access addresses according to a first sequence; generating a plurality of common unit access addresses according to a second address sequence, wherein a change trend between two adjacent addresses among the common unit access addresses is different from a change trend between two adjacent addresses among the data unit access address; and accessing the data units in a memory according to the data unit access addresses, and accessing the common units in the memory according to the common unit access addresses.
The above and other aspects of the invention will become better understood with regard to the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.
The present invention discloses a time de-interleaving circuit and a time de-interleaving method capable of reducing the memory capacity that a time de-interleaving process requires and preventing data from being inappropriately overwritten.
The data unit access generator 210 generates a plurality of data unit access addresses according to a first address sequence. For example, the first address sequence is an address incremental/decremental sequence, which may adopt a successive address incremental/decremental rule or other rule defined by a designer implementing the present invention as the address incremental/decremental rule. Once the first address sequence is determined, one person skilled in the art may design and provide the data unit access address generator 210 based on the disclosure of the present invention. Referring to
The common unit access generator 220 generates a plurality of common unit access addresses according to a second address sequence. The second address sequence is a reverse sequence of the first address sequence, and may adopt a successive address decremental/incremental rule or other rule defined by a designer implementing the present invention as the address decremental/incremental rule. Similarly, once the second address sequence is determined, one person skilled in the art may design and provide the common unit access address generator 220 based on the disclosure of the present invention. Referring to
The memory 230 accesses the data units of the information units according to the data unit access addresses, and accesses the common units of the information units according to the common unit access addresses. For example, as shown in
Referring to
As demonstrated in the above description, the time de-interleaving circuit of the present invention reduces the amount of memory used for accessing the data units and common units through a shared memory, and eliminates the issue of overwriting between the data units and common units through arrangements of access sequences and addresses of the memory, thereby solving the dilemma in the technical field through a simple and feasible solution.
In addition to the foregoing circuit, the present invention further discloses a time de-interleaving method applied to a signal receiver of a communication system to perform a time de-interleaving process on an interleaved signal. The interleaved signal includes a plurality of information units, which include a plurality of data units and a plurality of common units. Referring to
In step S610, a plurality of data unit access addresses are generated according to a first address sequence. This step may be performed by the data unit access address generator 210 in
In step S620, a plurality of common unit access addresses are generated according to a second address sequence. A change trend between two adjacent addresses of the common unit access addresses is different from a change trend between two adjacent addresses of the data unit access addresses. For example, the change trend is a difference between a latter address and a former address of the two adjacent addresses. This step may be performed by the common unit access address generator 220 in
In step S630, the data units are read from or written to a memory according to the data unit access addresses, and the common units are read from or written to the memory according to the common unit access addresses. For example, the memory is the memory 230 in
One person skilled in the art may understand the implementation details and variations of the method of the present invention based on the disclosure associated with the foregoing circuit of the present invention. That is, the technical features of the foregoing circuit may be reasonably applied in the method of the present invention. Therefore, without affecting the full disclosure and possible implementation of the method of the present invention, such repeated details are omitted herein.
In conclusion, the time de-interleaving circuit and the time de-interleaving method of the present invention are capable of reducing the amount of memory that a time de-interleaving process requires as well as preventing data to be read out from being overwritten, thereby enhance cost-effectiveness and accuracy of the de-interleaving process.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
Number | Date | Country | Kind |
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105129531 | Sep 2016 | TW | national |