Timer circuit

Abstract

A disclosed timer circuit for clocking a predetermined time includes an oscillator and a frequency dividing unit for dividing a frequency of an oscillating signal output from the oscillator. A comparing unit determines whether a short-time mode instruction is received by comparing a voltage received at an external terminal with a predetermined voltage. A switch causes the oscillating signal to bypass a part of the frequency dividing unit in response receiving the short-time mode instruction.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings, in which:

FIG. 1 is a circuit diagram of a timer circuit according to one embodiment of the present invention;

FIG. 2 is a diagram for describing a battery temperature detection voltage and a short-time mode instruction voltage; and

FIG. 3 is a block diagram of an example of a conventional charge controller.

Claims

1. A timer circuit for clocking a predetermined time, comprising: an oscillator configured to output an oscillating signal;a frequency dividing unit configured to divide a frequency of the oscillating signal output from the oscillator;an external terminal configured to receive from outside a voltage within a predetermined range or a short-time mode instruction voltage that is outside the predetermined range;a comparing unit configured to determine whether a short-time mode instruction is received by comparing the voltage received at the external terminal with a predetermined voltage; anda first switch configured to switch a status of a part of the frequency dividing unit to a bypass status so as to be bypassed by the oscillating signal output from the oscillator, in response to the comparing unit determining that the short-time mode instruction is received.

2. The timer circuit according to claim 1, further comprising: a second switch configured to cancel the bypass status of the part of the frequency dividing unit caused by the first switch.

3. The timer circuit according to claim 2, further comprising: a third switch configured to operate the second switch.

4. The timer circuit according to claim 1, wherein the frequency dividing unit includes plural stages of flip-flops that are cascade-connected.