Claims
- 1. A method of designing an integrated circuit, comprising:
monitoring user interaction with logical blocks during a functional design process of an integrated circuit; and deriving indications of timing properties during the functional design process based on the monitored user interaction.
- 2. The method as described in claim 1, wherein user interaction with logical blocks includes at least one of specifying an interconnection between functional components of an integrated circuit, selecting components of an integrated circuit and arranging components of an integrated circuit.
- 3. The method as described in claim 2, wherein the user interaction is performed in a graphical design environment.
- 4. The method as described in claim 1, further comprising accumulating the derived indications of timing properties.
- 5. The method as described in claim 4, wherein a functional design is achieved, the timing is closed based on the accumulated indications.
- 6. The method as described in claim 1, wherein the logical blocks are treated as independent modules for deriving indications of timing properties.
- 7. The method as described in claim 1, wherein the logical blocks are grouped and indications of timing properties derived based on the groupings.
- 8. The method as described in claim 1, wherein a suggestion is provided to a user after a functional design is achieved of at least one of an area of concern, a path to resolution of a timing problem, timing violations, tight margins, layout anomalies and jitter accumulation.
- 9. The method as described in claim 1, wherein a database is provided of characteristics of the functional blocks, the characteristics utilized to derive indications of timing properties.
- 10. The method as described in claim 1, wherein the indications are not explicitly incorporated in the functional design, but are passed on to a back-end process as guidance regarding timing violations, tight margins, layout anomalies and jitter accumulation.
- 11. The method as described in claim 1, wherein a mathematical formulation is provided based on an achieved functional design and the derived timing indications, the mathematical formulation including functional description of the integrated circuit, block structure in which a relationship of logical blocks is expressed, hierarchy in which the logical blocks are expressed, timing implications of logical blocks in terms of timing specification for the integrated circuit, content of timing indications and structure of timing indications.
- 12. The method as described in claim 1, wherein indications of timing properties are derived during the functional design process through an examination of how timing evolves in simulated and emulated stages of functional development.
- 13. The method as described in claim 1, wherein indications of timing properties are derived during the functional design process by applying a speed scaling factor to a logical block to predict timing margins associated with such scaling, thereby having a functional version of the integrated circuit design serve as a proxy for a design transposed to an actual target technology.
- 14. A system for designing an integrated circuit, comprising:
a memory suitable for storing a program of instructions; and a processor communicatively coupled to the memory, the processor suitable for performing the program of instructions, wherein the program of instructions configures the processor to
monitor user interaction with logical blocks during a functional design process of an integrated circuit; and derive indications of timing properties during the functional design process based on the monitored user interaction.
- 15. The system as described in claim 14, wherein user interaction with logical blocks includes at least one of specifying an interconnection between functional components of an integrated circuit, selecting components of an integrated circuit and arranging components of an integrated circuit.
- 16. The system as described in claim 15, wherein the user interaction is performed in a graphical design environment.
- 17. The system as described in claim 14, further comprising accumulating the derived indications of timing properties.
- 18. The system as described in claim 17, wherein a functional design is achieved, the timing is closed based on the accumulated indications.
- 19. The system as described in claim 14, wherein the logical blocks are treated as independent modules for deriving indications of timing properties.
- 20. The system as described in claim 14, wherein the logical blocks are grouped and indications of timing properties derived based on the groupings.
- 21. The system as described in claim 14, wherein a suggestion is provided to a user after a functional design is achieved of at least one of an area of concern, a path to resolution of a timing problem, timing violations, tight margins, layout anomalies and jitter accumulation.
- 22. The system as described in claim 14, wherein a database is provided of characteristics of the functional blocks, the characteristics utilized to derive indications of timing properties.
- 23. The system as described in claim 14, wherein the indications are not explicitly incorporated in the functional design, but are passed on to a back-end process as guidance regarding timing violations, tight margins, layout anomalies and jitter accumulation.
- 24. The system as described in claim 14, wherein a mathematical formulation is provided based on an achieved functional design and the derived timing indications, the mathematical formulation including functional description of the integrated circuit, block structure in which a relationship of logical blocks is expressed, hierarchy in which the logical blocks are expressed, timing implications of logical blocks in terms of timing specification for the integrated circuit, content of timing indications and structure of timing indications.
- 25. The system as described in claim 14, wherein indications of timing properties are derived during the functional design process through an examination of how timing evolves in simulated and emulated stages of functional development.
- 26. The system as described in claim 14, wherein indications of timing properties are derived during the functional design process by applying a speed scaling factor to a logical block to predict timing margins associated with such scaling, thereby having a functional version of the integrated circuit design serve as a proxy for a design transposed to an actual target technology.
- 27. A system for designing an integrated circuit, comprising:
means for monitoring user interaction with logical blocks during a functional design process of an integrated circuit; and means for deriving indications of timing properties during the functional design process, the deriving means communicatively coupled to the monitoring means.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] The present application hereby incorporates the following United Stated Patent Applications by reference in their entirety:
1AttorneyDocket NumberExpress Mail L.N./U.S.P.N.Filing DateLSI 01-39010/015,194November 20, 2001LSI 01-48810/021,414October 30, 2001LSI 01-48910/021,619October 30, 2001LSI 01-49010/021,696October 30, 2001LSI 01-524B10/044,781January 10, 2002LSI 01-54310/135,189April 30, 2002LSI 01-69509/842,335April 25, 2001LSI 01-82710/034,839December 27, 2001LSI 01-828B10/061,660February 1, 2002LSI 02-016610/135,869April 30, 2002LSI 02-0560EV 087 433 682 USJune 27, 2002