Claims
- 1. A system for providing a plurality of synchronous timing signals having period values that are not even multiples of a clock period comprising
- a clock for generating clock signals separated in time by a clock period, and
- a plurality of local edge generator connected by respective paths to said clock receiving said clock signals, each said local edge generator including
- local programmable counting means to provide local outputs upon receiving predetermined clock signals,
- said local programmable counting means including a first random access memory (RAM) loaded with integer numbers of clock periods in predetermined time values, said integer numbers corresponding to said predetermined clock signals,
- means for generating a deskew value to correct for a particular delay in said respective path between said edge generator and said clock, and
- local programmable delay means for providing a timing signal after a delay interval following each said local output, said local programmable delay means having a resolution,
- said local programmable delay means including a deskew circuit for receiving said deskew value,
- said deskew circuit providing a delay control signal based on said deskew value to said local programmable delay means so that said timing signal is synchronous with timing signals of other local edge generators,
- the resolution of said local programmable delay means being greater than that of said clock,
- said local programmable delay means including a delay line providing said timing signal and a second RAM loaded with remainder values of a division of said predetermined time values by said clock period, said second RAM being connected to provide said remainder values to said deskew circuit for generating said delay control signal, the system further comprising a common address bus connected to said first and second RAMs in each of said local generators.
- 2. The system of claim 1 wherein said local programmable counting means includes a local counter that counts clock signals and produces an output related to said counted clock signals and a coincidence detector that compares the output of the local counter with an integer number of clock periods corresponding to a desired time value and provides an output to a flip flop, said flip flop being triggered on an immediately following clock signal to provide said local output.
- 3. The system of claim 2 wherein said coincidence detector is connected to receive said integer number from said first RAM.
- 4. A system for providing a plurality of synchronous timing signals having period values that are not even multiples of a clock period comprising
- a clock for generating clock signals separated in time by a clock period, and
- a plurality of local edge generators connected by respective paths to said clock receiving said clock signals, each said local edge generator including
- local programmable counting means to provide local outputs upon receiving predetermined clock signals,
- means for generating a deskew value to correct for a particular delay in said respective path between said edge generator and said clock, and
- local programmable delay means for providing a timing signal after a delay interval following each said local output, said local programmable delay means having a resolution, said local programmable delay means including a deskew circuit for receiving said deskew value, said deskew circuit providing a delay control signal based on said deskew value to said local programmable delay means so that said timing signal is synchronous with timing signals of other local edge generators,
- the resolution of said local programmable delay means being grater than that of said clock,
- wherein said local programmable counting means includes a local counter that counts clock signals and produces an output related to said counted clock signals and a coincidence detector that compares the output of the local counter with an integer number of clock periods corresponding to a desired time value and provides an output to a flip flop, said flip flop being triggered on an immediately following clock signal to provide said local output,
- wherein said local programmable counting means includes a first random access memory loaded with integer numbers of clock periods in predetermined time values and wherein said coincidence detector is connected to receive said integer number from said first RAM,
- wherein said local programmable delay means includes a delay line providing said timing signal and a second RAM loaded with remainder values of a division of said predetermined time values by said clock period, said second RAM being connected to provide said remainder values to said deskew circuit for generating said delay control signal, the system further comprising a common address bus connected to said first and second RAMs in each of said local generators.
- 5. The system of claim 4 wherein each said local edge generator comprises means for generating residue values, and wherein said programmable delay means includes a first adder for adding a residue value to a said remainder value to provide a sum as said delay control signal to said delay line.
- 6. The system of claim 5 wherein said deskew circuit includes a deskew adder for adding said deskew value to the residue and remainder values to provide a sum as said delay control signal to the delay line.
- 7. The system of claim 6 wherein said means for generating said deskew value is provided by a deskew generator that can vary the deskew value on a cycle-by-cycle basis.
- 8. A system for providing a plurality of synchronous timing signals having period values that are not even multiples of a clock period comprising
- a clock for generating clock signals separated in time by a clock period, and
- a plurality of local edge generators connected by respective paths to said clock receiving said clock signals, each said local edge generator including
- local programmable counting means to provide local outputs upon receiving predetermined clock signals,
- means for generating a deskew value to correct for a particular delay in said respective path between said edge generator and said clock, and
- local programmable delay means for providing a timing signal after a delay interval following each said local output, said local programmable delay means having a resolution, said local programmable delay means including a deskew circuit for receiving said deskew value, said deskew circuit providing a delay control signal based on said deskew value to said local programmable delay means so that said timing signal is synchronous with timing signals of other local edge generators,
- the resolution of said local programmable delay means being greater than that of said clock,
- wherein there is a master control circuit that includes said clock and provides master end-of-count pulses and residue values to the local edge generators, said master end-of-count pulses being used to reset said local programmable counting means, said residue values being used by said local programmable delay means in generating said delay control signal.
- 9. The system of claim 8 wherein said master control circuit is a period oscillator including master programmable counting means to provide master end-of-count outputs upon receiving predetermined clock signals and master programmable delay means for providing a period output signal after a delay interval following each said master end-of-count output, said master programmable delay means having a resolution, the resolution of said master programmable delay means being grater than that of said clock.
Parent Case Info
This application is a continuation of application Ser. No. 521,272, filed May 9, 1990 of George W. Conner, for "TIMING GENERATOR," now abandoned, which is a continuation of application Ser. No. 012,815 filed Feb. 9, 1987, of George W. Conner, for "TIMING GENERATOR," now abandoned.
US Referenced Citations (11)
Continuations (2)
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Number |
Date |
Country |
Parent |
521272 |
May 1990 |
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Parent |
12815 |
Feb 1987 |
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