Claims
- 1. A transistor, comprising:
- a trench formed in a semiconductor substrate;
- a nonuniform dielectric lining formed in the trench, the nonuniform dielectric lining having a thin portion and a thick portion;
- a drain drift region formed in the semiconductor substrate, the drain drift region abutting and substantially surrounding the thick portion of the nonuniform dielectric lining;
- a drain region formed in a top surface of the semiconductor substrate in the drain drift region;
- a source region formed in the semiconductor substrate, the source region abutting the thin portion of the nonuniform dielectric lining, wherein the region between the source region and the drain drift region along the thin portion of the nonuniform dielectric lining forms a channel region; and
- a gate formed in the trench.
- 2. The transistor of claim 1 further comprising an isolation region formed below the source region, wherein the isolation region electrically isolates the source region from the semiconductor substrate.
- 3. A transistor, comprising:
- a trench formed in a semiconductor substrate;
- a nonuniform dielectric lining formed in the trench, the nonuniform dielectric lining having a thin portion and a thick portion;
- a drain drift region formed in the semiconductor substrate, the drain drift region abutting and substantially surrounding the thick portion of the nonuniform dielectric lining;
- a drain region formed in a top surface of the semiconductor substrate in the drain drift region;
- a p-well region formed in the semiconductor substrate, the p-well region abutting and substantially surrounding the thin portion of the nonuniform dielectric lining;
- a source region formed in the p-well region, the source region abutting the thin portion of the nonuniform dielectric lining, wherein the region within the p-well region between the source region and the drain drift region along the thin portion of the nonuniform dielectric lining forms a channel region; and
- a gate, formed in the trench.
- 4. The transistor of claim 3 further comprising an isolation region formed below the p-well region, wherein the isolation region electrically isolates the source region from the semiconductor substrate.
Parent Case Info
This is a continuation of application Ser. No. 07/883,985 filed on May 18, 1992, U.S. Pat. No. 5,640,034.
US Referenced Citations (8)
Continuations (1)
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Number |
Date |
Country |
Parent |
883985 |
May 1992 |
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