BRIEF DESCRIPTION OF THE DRAWINGS
The above and other objects, features and other advantages of the invention will be moire clearly understood from the following detailed description taken in conjunction with the accompanying, drawings, in which:
FIGS. 1A to 1C are diagrams for explaining a conventional transistor;
FIG. 2 is a diagram for explaining a structure of a transistor configured according to the invention;
FIGS. 3 to 6 are diagrams for explaining an end portion of a gate line in a cell region and a peripheral circuit region.
FIG. 7 shows a cross sectional view of the gate line; and
FIGS. 8A to 11C are diagrams for a method for manufacturing a transistor in accordance with embodiments of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
Preferred embodiments of the invention will now be described in detail with reference to the accompanying drawings. These embodiments are used only for illustrative purposes, and the invention is not limited thereto.
FIG. 2 is a diagram for explaining a structure of a transistor configured according to the invention.
Referring to FIG. 2, the transistor configured according to the invention includes gate lines 110 disposed at specified intervals on an active region 100 of a semiconductor substrate. An end portion 120 of each gate line 110 disposed on the active region 100 of the semiconductor substrate adjacent to a device isolation region 105 engages a trench of a valley structure etched to a specified depth or a protrusion of a mesa structure protruded to a specified height. Here, the transistor includes a NMOS transistor and a PMOS transistor in a peripheral circuit region. The device isolation region 105 is a remaining region except for the active region 100, and the device isolation region 105 and the active region 100 are separated by a device isolation layer (not shown) such as a shallow trench isolation (STI). In the drawings, “X” designates a direction in which the gate line is extended and “Y” designates a direction perpendicular to the X direction.
Further, although not shown in the drawing, spacers are formed at both side walls of the gate line 110, and source/drain regions are formed in the active region 100 of the substrate exposed at both sides of the gate line 110. Further, contact electrodes 130 are formed on the active region 100 such that the contact electrodes 130 are vertically connected to the source/drain regions.
The end portion 120 of the gate line 110 may have a T-shaped cross section due to the trench of the valley structure formed in the active region 100 of the semiconductor substrate adjacent to the device isolation region. Further, the end portion 120 of the gate line 110 may have an inverted U-shaped cross section) wherein the recess in the cross section faces the substrate, due to the protrusion of the mesa structure formed in the active region 100 of the semiconductor substrate adjacent to the device isolation region.
In the transistor according to the invention, the end portion 120 of the gate line in contact with the active region 100 of the semiconductor substrate is formed to have a width equal to the line width of the gate lines 110 formed on the active region 100. The end portion 120 of the gate line 110 has a T-shaped cross section or an inverted U-shaped cross section with the recess in the cross section facing the substrate, due to the trench of the valley structure or the protrusion of the mesa structure formed in the active region. Accordingly, a channel of the gate line can be longer than that of the conventional gate line. Thus, all gate lines can be designed to have the same line width while reducing leakage current generated at the end portion of each gate line due to the HEIP effect when a voltage is applied from a source to a drain of the transistor.
Hereinafter, an end portion of a gate line in a cell region and a peripheral circuit region will be described.
FIGS. 3 to 6 show cross sectional views of the peripheral circuit region taken along lines C-C′ in FIG. 2. FIG. 7 shows a cross sectional view of the gate line in the peripheral circuit region taken along lines D-D′.
Referring to FIG. 3, a first gate line structure of the transistor according to the invention includes a gate line 202 that is formed to have a flat bottom surface on a semiconductor substrate 200, in the cell region. The first gate line structure also includes a gate line 204 in the peripheral circuit region including NMOS and PMOS regions, wherein an end portion of the gate line 204 engages a trench 205 of the valley structure that is formed in an active region of the semiconductor substrate 200 adjacent to the device isolation region by etching the substrate to a specified depth from the surface thereof. Further, “X” designates a direction in which the gate line is extended and “Y” designates a direction perpendicular to the X direction. Hereinafter, description of the X and Y directions will be omitted.
Referring to FIG. 4, a second gate line structure of the transistor according to the invention includes t gate line 206 engages a trench 207 for a recessed channel formed by etching the substrate to a specified depth from the surface thereof, in the cell region. The second gate line structure also includes a gate line 208 in the peripheral circuit region, wherein an end portion of the gate line 208 engages a trench 209 of the valley structure that is formed in the active region of the semiconductor substrate 200 adjacent to the device isolation layer by etching the substrate to a specified depth from the surface thereof.
Referring to FIG. 5, a third gate line structure of the transistor according to the invention includes a gate line 210 that is formed to have a flat bottom surface on the active region of the semiconductor substrate 200 adjacent to the device isolation layer and an end portion of the gate line, in the cell region. The third gate line structure also includes a gate line 212 in the peripheral circuit region including NMOS and PMOS regions, wherein an end portion of the gate line 212 is engaged with a protrusion 213 of the mesa structure that is formed on the active region of the semiconductor substrate 200 adjacent to the device isolation layer to be protruded to a specified height from the surface of the substrate.
Referring to FIG. 6, a fourth gate line structure of the transistor according to the present invention includes a gate line 214 that is engaged with a protrusion 215 protruded to a specified height from the surface of the semiconductor substrate 200, in the cell region. The fourth gate line structure also includes a gate line 216 in the peripheral circuit region including NMOS and PMOS regions, wherein an end portion of the gate line 216 engages a protrusion 217 of the mesa structure having a flat top surface that is formed on the active region of the semiconductor substrate 200 adjacent to the device isolation layer to be protruded to a specified height from the surface of the substrate.
As shown in FIGS. 3 to 6, in the peripheral circuit region, the end portions of the gate lines of the transistor are formed to be engaged with the trenches 205 and 209 of the valley structure or the protrusions 213 and 217 of the mesa structure. As a result, the end portion of the gate line can be formed to have the same line width a as the line width b of the gate line 110 shown in FIG. 7.
Hereinafter, a method for manufacturing the transistor according to the invention will be described in accordance with embodiments of the invention.
FIGS. 8A to 8C are diagrams for a method for manufacturing a transistor, wherein an end portion of a gate line is engaged with a trench of the valley structure in accordance with a first embodiment of the invention.
Referring to FIG. 5A, a photoresist film pattern 302 is formed on a semiconductor substrate 300 including a device isolation region to cover the substrate 300 in the cell region and selectively expose the substrate 300 in the peripheral circuit region. In the peripheral circuit region, it is preferable to expose only a region adjacent to the device isolation region to be engaged with the end portion of the gate line.
Referring to FIG. 8B, in the peripheral circuit region, the exposed region to be engaged with the end portion of the gate line is etched through a mask of the photoresist film pattern 302, so that a trench 304 of the valley structure is formed. The trench 304 of the valley structure may be formed in a rectangular shape.
Then, as shown in FIG. 8C, gate lines 306 and 308 disposed at specified intervals are formed by depositing and patterning a gate insulating film (not shown) and a gate electrode on the semiconductor substrate 300. Specifically, the gate line 306 having a flat bottom surface is formed in the cell region, and the gate line 308 is formed in the peripheral circuit region, wherein an end portion of the gate line 308 is engaged with the trench 304 of the valley structure adjacent to the device isolation region. The end portion of the gate line 308 has a T-shaped cross section due to the trench 304 of the valley structure formed on the semiconductor substrate. Further, “X” designates a direction in which the gate line is extended and “Y” designates a direction perpendicular to the X direction. Hereinafter, description of the X and Y directions will be omitted.
FIGS. 9A to 9C are diagrams for a method for manufacturing a transistor, wherein an end portion of a gate line is engaged with a trench of the valley structure in accordance with a second embodiment of the invention.
Referring to FIG. 9A, a photoresist film pattern 310 is formed on the semiconductor substrate 300 including the device isolation region to selectively expose the substrate 300 in the cell region and the peripheral circuit region. In this case, exposed regions in the cell region and the peripheral circuit region are regions for forming a recessed channel trench and a trench, respectively. In the peripheral circuit region, it is preferable to expose only an active region of the semiconductor substrate 300 to be engaged with the end portion of the gate line, adjacent to the device isolation region.
Referring to FIG. 9B, the exposed regions in the cell region and the peripheral circuit region are etched through a mask of the photoresist film pattern 310, so that trenches 311 and 312 of the valley structure are formed. The trench 312 of the valley structure may be formed in a rectangular shape.
Then, as shown in FIG. 9C, gate lines 314 and 316 disposed at specified intervals are formed by depositing and patterning a gate insulating film (not shown) and a gate electrode on the semiconductor substrate 300. Specifically, the gate line 314 for a recessed channel is formed in the cell region, and the gate line 316 is formed in the peripheral circuit region, wherein an end portion of the gate line 316 is engaged with the trench 312 of the valley structure adjacent to the device isolation region. The end portion of the gate line 316 formed in the peripheral circuit region has a T-shaped cross section due to the trench 312 of the valley structure. In this case, while the trench 311 for a recessed channel is formed in the cell region, the trench 312 of the valley structure is formed at the same time in the peripheral circuit region, whereby the number of steps in a photolithography process can be reduced.
As described above, in the peripheral circuit region the end portion of the gate line engages the trench of the valley structure, which is formed in the active region of the semiconductor substrate adjacent to the device isolation region. Accordingly, the channel can be lengthened while the end portion of the gate line is formed to have the same line width as the gate line width. Thus, an interval between neighboring gate lines can be further shortened, thereby improving integration of the device. Further, since the end portion of the gate line adjacent to the device isolation region is formed to have the same line width as the gate line width, it is possible to prevent a contact between tabs and improve characteristics of the device.
FIGS. 10A to 10C are diagrams for a method for manufacturing a transistor, wherein an end portion of a gate line engages a protrusion of the mesa structure in accordance with a third embodiment of the invention.
Referring to FIG. 10A, a photoresist film pattern 318 is formed on the semiconductor substrate 300 including the device isolation region to cover the substrate 300 in the cell region and selectively cover the substrate 300 in the peripheral circuit region. In the peripheral circuit region, it is preferable to cover only an active region of the semiconductor substrate 300 adjacent to the device isolation region to be engaged with the end portion of the gate line.
Referring to FIG. 10B, in the peripheral circuit region, an exposed region in the peripheral circuit region is etched through a mask of the photoresist film pattern 318, so that a protrusion 320 of the mesa structure having a flat top surface is formed to be protruded from the surface of the substrate. The protrusion 320 of the mesa structure may be formed in a rectangular shape. In this case, the protrusion 320 of the mesa structure can be formed by etching the semiconductor substrate 300 to a specified depth c from the surface thereof.
Then, as shown in FIG. 10C, gate lines 322 and 324 disposed at specified intervals are formed by depositing and patterning a gate insulating film (not shown) and a gate electrode on the semiconductor substrate 300. An end portion of the gate line 324 has an inverted U-shaped cross section, wherein the recess in the cross section faces the semiconductor substrate 300.
FIGS. 11A to 11C are diagrams for a method for manufacturing a transistor, wherein an end portion of a gate line engages a protrusion of the mesa structure in accordance with a fourth embodiment of the invention.
Referring to FIG. 11A, a photoresist film pattern 326 is formed on a semiconductor substrate 300 including the device isolation region to selectively cover the substrate 300 in the cell region and the peripheral circuit region. In the peripheral circuit region, it is preferable to cover only an active region of the semiconductor substrate 300 to be engaged with the end portion of the gate line, adjacent to the device isolation region.
Referring to FIG. 11B, an exposed region in the cell region and the peripheral circuit region is etched through a mask of the photoresist film pattern 326, so that a protrusion 328 of a fin type is formed in the cell region, and a protrusion 330 of the mesa structure having a flat top surface is formed in the peripheral circuit region to be protruded from the surface of the substrate. The protrusion 330 of the mesa structure may be formed in a rectangular shape. In this case, the protrusion 330 of the mesa structure can be formed by etching the semiconductor substrate 300 to a specified depth d from the surface thereof.
Then, as shown in FIG. 11C, gate lines 332 and 334 disposed at specified intervals are formed by depositing and patterning a gate insulating film and a gate electrode on the semiconductor substrate 300. Specifically, the gate line 332 for a fin channel is formed in the cell region, and the gate line 334 is formed in the peripheral circuit region, wherein an end portion of the gate line 334 has an inverted U-shaped cross section due to the protrusion 330 of the mesa structure formed on the semiconductor substrate 300. In this case, while the protrusion 328 for the fin channel is formed in the cell region, at the same time, the protrusion 330 of the mesa structure is formed in the peripheral circuit region, whereby the number of steps in a photolithography process can be reduced.
As described above, the end portion of the gate line adjacent to the device isolation region engages the protrusion of the mesa structure in the peripheral circuit region. Accordingly, the channel can be lengthened while the end portion of the gate line is formed to have the same line width as the gate line width. Thus, an interval between neighboring gate lines can be further shortened, thereby improving integration of the device. Further, since the end portion of the gate line adjacent to the device isolation region is formed to have the same line width as the gate line width, it is possible to prevent a contact between tabs and improve characteristics of the device.
Next, although not shown in the drawings, spacer films are formed at both side walls of the gate lines engaged with the trench of the valley structure and the protrusion of the mesa structure by depositing and patterning an insulating film such as a silicon nitride film on the gate lines. Then, source/drain regions are formed in the semiconductor substrate by performing ion implantation of n-type or p-type conductive impurities into the active region of the substrate, thereby forming a transistor.
In the method for manufacturing the transistor according to the invention, the end portion of the gate line is engaged the trench of the valley structure etched to a specified depth or the protrusion of the mesa structure protruded to a specified height that is formed in the active region of the semiconductor substrate. Since the end portion of the gate line in contact with the active region has a T-shaped cross section or an inverted U-shaped cross section with the recess in the cross section facing the substrate, due to the trench or protrusion, the channel can be longer than that of a general gate line while the end portion of the gate line in contact with the active region is formed to have the same line width as a general gate line width.
As described above, according to the invention, the trench of the valley structure or the protrusion of the mesa structure protruded to a specified height is formed in the active region in contact with the end portion of the gate line, whereby the channel can be longer than that of a general gate line while the end portion of the gate line in contact with the active region is formed to have the same line width as a general gate line width.
Therefore, by forming the trench of the valley structure or the protrusion of the mesa structure protruded to a specified height according to the invention, it is possible to reduce the leakage current generated at an interface of the end portion of the gate line due to the HEIP effect when a voltage is applied from the source to the drain of the transistor. Further, all gate lines can be designed to have the same line width, thereby preventing the size of a semiconductor device chip from increasing. Furthermore, it is possible to secure stability of threshold voltage under the gate line by forming the gate line having an equal line width.
Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as defined in the accompanying claims.
Patent Application
20080079040
