The present invention relates generally to array structures, and more particularly to an array structure that may improve transistor characteristic measurement accuracy.
Process variations can cause component characteristics on a semiconductor device to greatly vary. Test structures may be constructed to test operating characteristics of devices such as insulated gate field effect transistors (IGFETs). However, as devices operate at lower voltages and currents, measurements may be distorted by leakage currents in current paths other than the desired path of the device under test (DUT).
In view of the above, it would be desirable to provide a way of reducing or eliminating leakage currents in a device, such as an IGFET being tested.
Various embodiments of the present invention will now be described in detail with reference to a number of drawings. The embodiments show transistor array circuits and methods constructed with insulated gate field effect transistors (IGFETs), for example IGFETs of complementary conductivity types (n-channel and p-channel types). In particular, the embodiments may include implementations using IGFETs having substantially lower absolute value of threshold voltage VT, e.g. about 0.4 volts for n-channel IGFETs and about −0.4 volts for p-channel IGFETs as compared to about 0.6 volts and −0.6 volts, respectively. Such low threshold voltage IGFETs may comprise DDC technology, as but one example. DDC transistors are particularly advantageous for the embodiments herein based on the ability to reliably set threshold voltage with substantially reduced variation compared with conventional planar CMOS transistors. DDC transistors are also amenable to be designed with reduced threshold voltage, based upon, among other device design attributes, there being a heavily doped region and structure below a substantially undoped channel. Further discussion regarding transistor structure and methods of implementation is provided in U.S. Pat. No. 8,273,617 entitled ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING THE SAME, which disclosure is incorporated by reference herein in its entirety. Such low threshold voltage IGFETs may be based upon a different transistor design, such as a design that is not planar but three-dimensional. Such low threshold voltage IFGETs may be produced on bulk silicon or on a substrate that has an insulating layer embedded therein.
Referring now to
Each row of drain mux circuits (120-0 to 120-7) may receive column factor signals (CF1(7:0) and CF2(3:0)) and corresponding bank select signal (BS0 to BS7). Each column of drain mux circuits (120-0 to 120-7) may also receive a respective drain drive signal (DDRV0 to DDRV7) and a drain current reduction signal DTRACK.
Each column of gate mux circuits (130-0 to 130-7) may receive row factor signals (RF1(7:0) and RF2(3:0)) and corresponding bank select signal (BS0 to BS7). Each row of gate mux circuits (130-0 to 130-7) may also receive a gate drive signal GDRV and a gate line low drive signal GTRACK.
Array drain drive circuit (140-0 to 140-7) may receive a global drain drive signal GDDRV and may provide a local drain drive signal (DDRV0 to DDRV7), respectively to respective row of drain mux circuits (120-0 to 120-7).
Semiconductor circuit 100 may include an address generator 190. Address generator 190 may receive a clock signal CLK and a reset signal RST and may provide column factor signals (CF1(7:0) and CF2(3:0)), row factors (RF1(7:0) and RF2(3:0)), and bank select signal (BS7:0). Address generator 190 may be a clocked counter.
Referring now to
Each drain line (DL-1 to DL-27) may be connected to a row of drain mux circuits 220-k and each gate line (GL-1 to GL-32) may be connected to a column of gate mux circuits 230-k, where k=0-7 and denotes the array (110-0 to 110-7) that a bank select signal (BS0-7) selects (
Array 200 may have 27 different types of transistors (i.e. different sizes, implant dopings, geometries, etc.) in the gate line (GL-1 to GL-32) direction. In this way, characteristics for different transistor types can be tested in each array. By having 32 transistors in each column connected to each drain line (DL-1 to DL-27), characteristic variations for same transistor types may be tested. Such variations may be caused by process variations or close proximity affects, for instance.
Referring now to
Drain mux circuit 300 may receive column factor signals (CF1(7:0) and CF2(3:0)) and bank select signal BSk, drain drive signal DDRVk, and drain current reduction signal DTRACK. It is understood that only one of the column factor signals (CF1(7:0) and one of the column factor signals (CF2(3:0)) may be used per drain mux circuit 300 in accordance with the proper address decoding.
Drain mux circuit 300 may include logic gates (G302 and G304) and pass gates (PG302 and PG304). Logic gate G302 can receive column factors signals (CF1(7:0) and CF2(3:0)), and bank select signal BSk as inputs and may provide a data line select complement signal DSELECTN-n as an output. Logic gate G302 may be a NAND logic gate. Logic gate G304 may receive data line select complement signal DSELECTN-n and may provide a data line select signal DSELECT-n. Logic gate G304 may be an inverter logic gate. Logic gates (G302 and G304) may include complementary conductive type IGFETs with the p-channel IGFETs receiving a body bias potential Vbp1 at a body terminal and n-channel IGFETs receiving a body bias potential Vbn1 at a body terminal. Logic gates (G302 and G304) may receive a power supply potential VDD1 and a ground potential VSS1.
Pass gate PG302 may receive drain current reduction signal DTRACK, data line select signal DSELECT-n, and data line select complement signal DSELECTN-n as inputs and may have an output coupled to a drain line DL-n. Pass gate PG302 can include transistors (P302 and N302). Transistor P302 may be p-channel IGFET and transistor N302 may be an n-channel IGFET N302. Transistor P302 may provide a controllable impedance path between source and drain terminals connected between drain current reduction signal DTRACK and data line DL-n. Transistor P302 may receive data line select signal DSELECT-n at a gate terminal and a body bias voltage Vbp1 at a body bias terminal. Transistor N302 may be connected in parallel with transistor P302 to provide a controllable impedance path between source and drain terminals connected between drain current reduction signal DTRACK and data line DL-n. Transistor N302 may receive data line select complement signal DSELECTN-n at a gate terminal and a body bias voltage Vbn1 at a body bias terminal.
Pass gate PG304 may receive local drain drive signal DDRVk, data line select signal DSELECT-n, and data line select complement signal DSELECTN-n as inputs and may have an output coupled to a drain line DL-n. Pass gate PG304 can include transistors (P304 and N304). Transistor P304 may be p-channel IGFET and transistor N304 may be an n-channel IGFET N304. Transistor P304 may provide a controllable impedance path between source and drain terminals connected between local drain drive signal DDRVk and data line DL-n. Transistor P304 may receive data line select complement signal DSELECTN-n at a gate terminal and a body bias voltage Vbp1 at a body bias terminal. Transistor N304 may be connected in parallel with transistor P304 to provide a controllable impedance path between source and drain terminals connected between local drain drive signal DDRVk and data line DL-n. Transistor N304 may receive data line select signal DSELECT-n at a gate terminal and a body bias voltage Vbn1 at a body bias terminal.
Referring now to
Gate mux circuit 400 may receive row factor signals (RF1(7:0) and RF2(3:0)) and bank select signal BSk, gate drive signal GDRV, and gate line low drive signal GTRACK. It is understood that only one of the row factor signals (RF1(7:0) and one of the row factor signals (RF2(3:0)) may be used per gate mux circuit 400 in accordance with the proper address decoding.
Gate mux circuit 400 may include logic gates (G402 and G404) and pass gates (PG402 and PG404). Logic gate G402 can receive row factors signals (RF1(7:0) and RF2(3:0)), and bank select signal BSk as inputs and may provide a gate line select signal GSELECT-m as an output. Logic gate G402 may be a NAND logic gate. Logic gate G404 may receive gate line select signal GSELECT-m and may provide a gate line select complement signal GSELECTN-m. Logic gate G404 may be an inverter logic gate. Logic gates (G402 and G404) may include complementary conductive type IGFETs with the p-channel IGFETs receiving a body bias potential Vbp2 at a body terminal and n-channel IGFETs receiving a body bias potential Vbn2 at a body terminal. Logic gates (G402 and G404) may receive a power supply potential VDD2 and a ground potential VSS2.
Pass gate PG402 may receive gate line low drive signal GTRACK, gate line select signal GSELECT-m, and gate line select complement signal GSELECTN-m as inputs and may have an output coupled to a gate line GL-m. Pass gate PG402 can include transistors (P402 and N402). Transistor P402 may be p-channel IGFET and transistor N402 may be an n-channel IGFET. Transistor P402 may provide a controllable impedance path between source and drain terminals connected between gate line low drive signal GTRACK and gate line GL-m. Transistor P402 may receive gate line select signal GSELECT-m at a gate terminal and a body bias voltage Vbp2 at a body bias terminal. Transistor N402 may be connected in parallel with transistor P402 to provide a controllable impedance path between source and drain terminals connected between gate line low drive signal GTRACK and gate line GL-m. Transistor N402 may receive gate line select complement signal GSELECTN-m at a gate terminal and a body bias voltage Vbn2 at a body bias terminal.
Pass gate PG404 may receive gate drive signal GDRV, gate line select signal GSELECT-m, and gate line select complement signal GSELECTN-m as inputs and may have an output coupled to a gate line GL-m. Pass gate PG404 can include transistors (P404 and N404). Transistor P404 may be p-channel IGFET and transistor N404 may be an n-channel IGFET. Transistor P404 may provide a controllable impedance path between source and drain terminals connected between gate drive signal GDRV and gate line GL-m. Transistor P404 may receive gate line select complement signal GSELECTN-m at a gate terminal and a body bias voltage Vbp2 at a body bias terminal. Transistor N404 may be connected in parallel with transistor P404 to provide a controllable impedance path between source and drain terminals connected between gate drive signal GDRV and gate line GL-m. Transistor N404 may receive gate line select signal GSELECT-m at a gate terminal and a body bias voltage Vbn2 at a body bias terminal.
Referring now to
Array drain drive circuit 500 may receive bank select signal BSk and global drain drive signal GDDRV as inputs and may have an output connected to provide local drain drive signal DDRVk. Array drain drive circuit 500 may include a logic gate G502 and a pass gate PG502.
Logic gate G502 may receive bank select signal BSk as an input and may provide an output. Logic gate G502 may be an inverter. Logic gate G502 may include complementary conductive type IGFETs with the p-channel IGFETs receiving a body bias potential Vbp1 at a body terminal and n-channel IGFETs receiving a body bias potential Vbn1 at a body terminal. Logic gate G502 may receive a power supply potential VDD1 and a ground potential VSS1.
Pass gate PG502 may receive bank select signal BSk, the output of inverter G502, and global drain drive signal GDDRV as inputs and may have an output coupled to provide local drain drive signal DDRVk. Pass gate PG502 can include transistors (P502 and N502). Transistor P502 may be p-channel IGFET and transistor N502 may be an n-channel IGFET. Transistor P502 may provide a controllable impedance path between source and drain terminals connected between global drain drive signal GDDRV and local drain drive signal DDRVk. Transistor P502 may receive the output of logic gate G502 at a gate terminal and a body bias voltage Vbp1 at a body bias terminal. Transistor N502 may be connected in parallel with transistor P502 to provide a controllable impedance path between source and drain terminals connected between between global drain drive signal GDDRV and local drain drive signal DDRVk. Transistor N502 may receive bank select signal BSk at a gate terminal and a body bias voltage Vbn1 at a body bias terminal.
The operation of semiconductor circuit 100 of
Bank select signal BS1 may transition to a high logic level to activate bank 110-1. The predetermined set of two row factors (RF1(7:0) and RF2(3:0)) uniquely received by gate G402 of gate mux circuit 400 (each of the other gate mux circuits 400 in column of gate mux circuits 130-1, receive a different unique combination of two row factors (RF1(7:0) and RF2(3:0))) may be at a high logic level. In this way, logic gate G402 may provide a gate line select complement signal GSELECTN-m, in this case m=30, having a logic low level and logic gate G404 may provide a gate line select signal GSELECT-m having a logic high level. With gate line select signal GSELECT-m at a logic high level, pass gate PG402 may be turned off and pass gate PG404 may be turned on and a low impedance path may be provided between gate drive signal GDRV and gate line GL-m, where m=30. In this way gate line GL-30 may be driven by gate drive signal GDRV through pass gate PG404.
All the other gate mux circuits 400 in column of gate mux circuits 130-1 that drive gate lines (GL-1 to GL-29, GL-31, and GL32) provide a gate line select signal GSELECT-m at a logic low level. With gate line select signal GSELECT-m at a logic low level, pass gate PG402 may be turned on and pass gate PG404 may be turned off and a low impedance path may be provided between gate line low drive signal GTRACK and gate line GL-m, where m=1=29, 31 and 32). In this way gate lines (GL-1 to GL-29, GL-31, and GL32) may be driven by gate line low drive signal GTRACK through pass gate PG402.
With bank select signal BS1 at a logic high level, pass gate PG502 in drive mux circuit 500 may be turned on and a low impedance path may be provided between global drain drive signal GDDRV and local drain drive signal DDRV1.
The predetermined set of two column factors (CF1(7:0) and CF2(3:0)) uniquely received by gate G302 of drain mux circuit 300 (each of the other drain mux circuits 300 in row of column mux circuits 120-1, receive a different unique combination of two column factors (CF1(7:0) and CF2(3:0))) may be at a high logic level. In this way, logic gate G302 may provide a drain line select complement signal DSELECTN-n, in this case m=25, having a logic low level and logic gate G304 may provide a drain line select signal DSELECT-n having a logic high level. With drain line select signal DSELECT-n at a logic high level, pass gate PG302 may be turned off and pass gate PG304 may be turned on and a low impedance path may be provided between local drain drive signal DDRV1 and drain line DL-n, where n=25. In this way gate line DL-25 may be driven by global drain drive signal GDDRV through pass gates PG502 and PG304.
All the other drain mux circuits 300 in row of drain mux circuits 120-1 that drive drain lines (DL-1 to DL-24, DL-26, and DL27) provide a drain line select signal DSELECT-n at a logic low level. With drain line select signal DSELECT-n at a logic low level, pass gate PG302 may be turned on and pass gate PG304 may be turned off and a low impedance path may be provided drain current reduction signal DTRACK and gate line DL-n, where n=1-24, 26, and 27). In this way drain lines (DL-1 to DL-24, DL-26, and DL27) may be driven by drain current reduction signal DTRACK through pass gate PG302.
As described above, the column of drain mux circuits 120-k may operate to drive a selected drain line DL-25 with a global drain drive signal GDDRV by way of pass gates (PG502 and PG304) while driving unselected drain lines (DL-1 to DL-24, DL-26, and DL27) with a drain current reduction signal DTRACK through pass gate PG302. In this way, a potential drop across the unselected pass gates PG304 (e.g. the 26 unselected pass gates PG304) connected to local drain drive signal DDRVk may be reduced to zero thereby eliminating or significantly reducing channel leakage currents to unselected columns. By reducing the potential across the unselected pass gates, a drive current through drain drive signal GDDRV may more accurately represent the actual drain current in selected transistor N(30,25). In this way, testing characteristics of a selected transistor N(30,25) can be more accurately performed.
For transistors operating with extremely low currents, for example low voltage IGFETs, such as FINFETs, DDC transistors, and/or transistors operating in subthreshold regions, the reduction of alternate leakage current paths may be particularly necessary to provide accurate current measurements.
In yet another feature, the row of gate mux circuits 130-k may operate to drive a selected gate line GL-30 with a gate drive signal GDRV by way of pass gate PG404 while driving unselected gate lines (GL-1 to GL-29, GL-31, and DL-32) with a gate line low drive signal GTRACK through pass gate PG402. In this way, a gate potential of unselected transistors (e.g. the 31 unselected transistors (N(1,25) to N(29,25), N(31,25), and N(32,25) along drain line DL25) may be set to a potential below ground potential VSS. The low gate potential may provide a substantially higher impedance path through the unselected transistors (N(1,25) to N(29,25), N(31,25), and N(32,25) along drain line DL25) and leakage current along drain line DL-25 may be substantially reduced. In this way, testing characteristics of a selected transistor N(30,25) can be more accurately performed.
Referring now to
Array 600 of
Referring now to
Referring now to
Referring now to
At step S910, the semiconductor circuit 100 may be provided on a probing apparatus. At step S920, a reset signal RST may be provided. In this way, address generator 190 may be reset to begin incrementing at the first address. At step S930, gate drive signal GDRV may be provided on a pad. At step S940, gate line low drive signal GTRACK may be provided on a pad. At step S950, global drain drive signal GDDRV may be provided on a pad. At step S960, drain current reduction signal DTRACK may be provided on a pad. At this point, the gate drive signal GDRV can be provided to the gate terminal of the transistor being tested, for instance, GL1 connected to transistor under test N(1,1). Global drain drive signal GDDRV may be provided to the drain line of the transistor being tested, for instance DL1 connected to transistor under test N(1,1). Also, at this time, the gate line low drive signal GTRACK can be provided to the gate lines (GL2-GL32) of transistors that are not selected and the drain current reduction signal can be provided to the drain lines (DL2-DL27) of transistors that are not selected. At step S970, the current flowing through global drain drive signal GDDRV may be determined. The current in step S970 may have a current value that is essentially the same as the current flowing through the transistor under test N(1,1). By driving a target current through drive signal at given drain voltage and slewing gate voltage, the gate voltage rises until the target current is hit, then the gate voltage can be measured for a selected drain voltage (typically value of 0.1V or Vdd).
At step S980, the clock signal CLK may transition through one clock cycle. In this way, address generator may output a subsequent address. The process may return to step S930 to test a subsequent transistor in accordance with the subsequent address. The test process may continue in this manner until all of the transistors in all of the arrays (110-0 to 110-7) may be tested.
The appearance of the phrase “in one embodiment” in various places in the specification do not necessarily refer to the same embodiment. The term “to couple” or “electrically connect” as used herein may include both to directly and to indirectly connect through one or more intervening components. While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific constructions and arrangements shown and described, since various other modifications may occur to those ordinarily skilled in the art. Accordingly, the specifications and drawings are to be regarded in an illustrative rather than a restrictive sense.
Number | Name | Date | Kind |
---|---|---|---|
3958266 | Athanas | May 1976 | A |
4000504 | Berger | Dec 1976 | A |
4021835 | Etoh et al. | May 1977 | A |
4242691 | Kotani et al. | Dec 1980 | A |
4276095 | Beilstein, Jr. et al. | Jun 1981 | A |
4315781 | Henderson | Feb 1982 | A |
4578128 | Mundt et al. | Mar 1986 | A |
4617066 | Vasudev | Oct 1986 | A |
4761384 | Neppl et al. | Aug 1988 | A |
4819043 | Yazawa et al. | Apr 1989 | A |
5034337 | Mosher et al. | Jul 1991 | A |
5144378 | Hikosaka | Sep 1992 | A |
5156989 | Williams et al. | Oct 1992 | A |
5156990 | Mitchell | Oct 1992 | A |
5166765 | Lee et al. | Nov 1992 | A |
5208473 | Komori et al. | May 1993 | A |
5298763 | Shen et al. | Mar 1994 | A |
5369288 | Usuki | Nov 1994 | A |
5384476 | Nishizawa et al. | Jan 1995 | A |
5559368 | Hu et al. | Sep 1996 | A |
5608253 | Liu et al. | Mar 1997 | A |
5663583 | Matloubian et al. | Sep 1997 | A |
5712501 | Davies et al. | Jan 1998 | A |
5719422 | Burr et al. | Feb 1998 | A |
5726488 | Watanabe et al. | Mar 1998 | A |
5780899 | Hu et al. | Jul 1998 | A |
5847419 | Imai et al. | Dec 1998 | A |
5856003 | Chiu | Jan 1999 | A |
5861334 | Rho | Jan 1999 | A |
5877049 | Liu et al. | Mar 1999 | A |
5889315 | Farrenkopf et al. | Mar 1999 | A |
5895954 | Yasumura et al. | Apr 1999 | A |
5923987 | Burr | Jul 1999 | A |
5989963 | Luning et al. | Nov 1999 | A |
6020227 | Bulucea | Feb 2000 | A |
6087210 | Sohn | Jul 2000 | A |
6087691 | Hamamoto | Jul 2000 | A |
6096611 | Wu | Aug 2000 | A |
6103562 | Son et al. | Aug 2000 | A |
6121153 | Kikkawa | Sep 2000 | A |
6147383 | Kuroda | Nov 2000 | A |
6157073 | Lehongres | Dec 2000 | A |
6175582 | Naito et al. | Jan 2001 | B1 |
6184112 | Maszara et al. | Feb 2001 | B1 |
6190979 | Radens et al. | Feb 2001 | B1 |
6194259 | Nayak et al. | Feb 2001 | B1 |
6218895 | De et al. | Apr 2001 | B1 |
6229188 | Aoki et al. | May 2001 | B1 |
6245618 | An et al. | Jun 2001 | B1 |
6288429 | Iwata et al. | Sep 2001 | B1 |
6300177 | Sundaresan et al. | Oct 2001 | B1 |
6313489 | Letavic et al. | Nov 2001 | B1 |
6320222 | Forbes et al. | Nov 2001 | B1 |
6326666 | Bernstein et al. | Dec 2001 | B1 |
6358806 | Puchner | Mar 2002 | B1 |
6380019 | Yu et al. | Apr 2002 | B1 |
6391752 | Colinge et al. | May 2002 | B1 |
6426279 | Huster et al. | Jul 2002 | B1 |
6444550 | Hao et al. | Sep 2002 | B1 |
6444551 | Ku et al. | Sep 2002 | B1 |
6461920 | Shirahata | Oct 2002 | B1 |
6461928 | Rodder | Oct 2002 | B2 |
6472278 | Marshall et al. | Oct 2002 | B1 |
6482714 | Hieda et al. | Nov 2002 | B1 |
6489224 | Burr | Dec 2002 | B1 |
6492232 | Tang et al. | Dec 2002 | B1 |
6500739 | Wang et al. | Dec 2002 | B1 |
6503801 | Rouse et al. | Jan 2003 | B1 |
6506640 | Ishida et al. | Jan 2003 | B1 |
6518623 | Oda et al. | Feb 2003 | B1 |
6534373 | Yu | Mar 2003 | B1 |
6541829 | Nishinohara et al. | Apr 2003 | B2 |
6548842 | Bulucea et al. | Apr 2003 | B1 |
6551885 | Yu | Apr 2003 | B1 |
6573129 | Hoke et al. | Jun 2003 | B2 |
6600200 | Lustig et al. | Jul 2003 | B1 |
6620671 | Wang et al. | Sep 2003 | B1 |
6624488 | Kim | Sep 2003 | B1 |
6630710 | Augusto | Oct 2003 | B1 |
6660605 | Liu | Dec 2003 | B1 |
6667200 | Sohn et al. | Dec 2003 | B2 |
6670260 | Yu et al. | Dec 2003 | B1 |
6693333 | Yu | Feb 2004 | B1 |
6730568 | Sohn | May 2004 | B2 |
6737724 | Hieda et al. | May 2004 | B2 |
6743291 | Ang et al. | Jun 2004 | B2 |
6753230 | Sohn et al. | Jun 2004 | B2 |
6770944 | Nishinohara et al. | Aug 2004 | B2 |
6797994 | Hoke et al. | Sep 2004 | B1 |
9787424 | Yu | Sep 2004 | |
6808994 | Wang | Oct 2004 | B1 |
6821825 | Todd et al. | Nov 2004 | B2 |
6822297 | Nandakumar et al. | Nov 2004 | B2 |
6831292 | Currie et al. | Dec 2004 | B2 |
6881641 | Wieczorek et al. | Apr 2005 | B2 |
6881987 | Sohn | Apr 2005 | B2 |
6893947 | Martinez et al. | May 2005 | B2 |
6916698 | Mocuta et al. | Jul 2005 | B2 |
6930007 | Bu et al. | Aug 2005 | B2 |
6930360 | Yamauchi et al. | Aug 2005 | B2 |
6963090 | Passlack et al. | Nov 2005 | B2 |
7002214 | Boyd et al. | Feb 2006 | B1 |
7008836 | Algotsson et al. | Mar 2006 | B2 |
7013359 | Li | Mar 2006 | B1 |
7015546 | Herr et al. | Mar 2006 | B2 |
7057216 | Quyang et al. | Jun 2006 | B2 |
7061058 | Chakravarthi et al. | Jun 2006 | B2 |
7064039 | Liu | Jun 2006 | B2 |
7064399 | Babcock et al. | Jun 2006 | B2 |
7071103 | Chan et al. | Jul 2006 | B2 |
7078325 | Curello et al. | Jul 2006 | B2 |
7078776 | Nishinohara et al. | Jul 2006 | B2 |
7089515 | Hanafi et al. | Aug 2006 | B2 |
7119381 | Passlack | Oct 2006 | B2 |
7170120 | Datta et al. | Jan 2007 | B2 |
7186598 | Yamauchi et al. | Mar 2007 | B2 |
7189627 | Wu et al. | Mar 2007 | B2 |
7199430 | Babcock et al. | Apr 2007 | B2 |
7202517 | Dixit et al. | Apr 2007 | B2 |
7211871 | Cho | May 2007 | B2 |
7221021 | Wu et al. | May 2007 | B2 |
7223646 | Miyashita et al. | May 2007 | B2 |
7226833 | White et al. | Jun 2007 | B2 |
7226843 | Weber et al. | Jun 2007 | B2 |
7235822 | Li | Jun 2007 | B2 |
7294877 | Rueckes et al. | Nov 2007 | B2 |
7297994 | Wieczorek et al. | Nov 2007 | B2 |
7301208 | Handa et al. | Nov 2007 | B2 |
7304350 | Misaki | Dec 2007 | B2 |
7312500 | Miyashita et al. | Dec 2007 | B2 |
7323754 | Ema et al. | Jan 2008 | B2 |
7332439 | Lindert et al. | Feb 2008 | B2 |
7348629 | Chu et al. | Mar 2008 | B2 |
7354833 | Liaw | Apr 2008 | B2 |
7427788 | Li et al. | Sep 2008 | B2 |
7442971 | Wirbeleit et al. | Oct 2008 | B2 |
7462908 | Bol et al. | Dec 2008 | B2 |
7485536 | Jin et al. | Feb 2009 | B2 |
7491988 | Tolchinsky et al. | Feb 2009 | B2 |
7494861 | Chu et al. | Feb 2009 | B2 |
7498637 | Yamaoka et al. | Mar 2009 | B2 |
7501324 | Babcock et al. | Mar 2009 | B2 |
7507999 | Kusumoto et al. | Mar 2009 | B2 |
7521323 | Surdeanu et al. | Apr 2009 | B2 |
7531393 | Doyle et al. | May 2009 | B2 |
7538412 | Schulze et al. | May 2009 | B2 |
7564105 | Chi et al. | Jul 2009 | B2 |
7592241 | Takao | Sep 2009 | B2 |
7598142 | Ranade et al. | Oct 2009 | B2 |
7605041 | Ema et al. | Oct 2009 | B2 |
7605060 | Meunier-Beillard et al. | Oct 2009 | B2 |
7605429 | Bernstein et al. | Oct 2009 | B2 |
7608496 | Chiu | Oct 2009 | B2 |
7615802 | Elpelt et al. | Nov 2009 | B2 |
7622341 | Chudzik et al. | Nov 2009 | B2 |
7642140 | Bae et al. | Jan 2010 | B2 |
7645665 | Kubo et al. | Jan 2010 | B2 |
7651920 | Siprak | Jan 2010 | B2 |
7655523 | Babcock et al. | Feb 2010 | B2 |
7675126 | Cho | Mar 2010 | B2 |
7678638 | Chu et al. | Mar 2010 | B2 |
7681628 | Joshi et al. | Mar 2010 | B2 |
7682887 | Dokumaci et al. | Mar 2010 | B2 |
7683442 | Burr et al. | Mar 2010 | B1 |
7696000 | Liu et al. | Apr 2010 | B2 |
7704844 | Zhu et al. | Apr 2010 | B2 |
7709828 | Braithwaite et al. | May 2010 | B2 |
7723750 | Zhu et al. | May 2010 | B2 |
7750405 | Nowak | Jul 2010 | B2 |
7750682 | Bernstein et al. | Jul 2010 | B2 |
7755146 | Helm et al. | Jul 2010 | B2 |
7759714 | Itoh et al. | Jul 2010 | B2 |
7795677 | Bangsaruntip et al. | Sep 2010 | B2 |
7818702 | Mandelman et al. | Oct 2010 | B2 |
7829402 | Matocha et al. | Nov 2010 | B2 |
7867835 | Lee et al. | Jan 2011 | B2 |
7883977 | Babcock et al. | Feb 2011 | B2 |
7888747 | Hokazono | Feb 2011 | B2 |
7897495 | Ye et al. | Mar 2011 | B2 |
7906413 | Cardone et al. | Mar 2011 | B2 |
7906813 | Kato | Mar 2011 | B2 |
7919791 | Flynn et al. | Apr 2011 | B2 |
7948008 | Liu et al. | May 2011 | B2 |
7952147 | Ueno et al. | May 2011 | B2 |
7960232 | King et al. | Jun 2011 | B2 |
7960238 | Kohli et al. | Jun 2011 | B2 |
7968400 | Cai | Jun 2011 | B2 |
7968411 | Williford | Jun 2011 | B2 |
8004024 | Furukawa et al. | Aug 2011 | B2 |
8012827 | Yu et al. | Sep 2011 | B2 |
8039332 | Bernard et al. | Oct 2011 | B2 |
8048791 | Hargrove et al. | Nov 2011 | B2 |
8048810 | Tsai et al. | Nov 2011 | B2 |
8067279 | Sadra et al. | Nov 2011 | B2 |
8105891 | Yeh et al. | Jan 2012 | B2 |
8106424 | Schruefer | Jan 2012 | B2 |
8106481 | Rao | Jan 2012 | B2 |
8119482 | Bhalla et al. | Feb 2012 | B2 |
8120069 | Hynecek | Feb 2012 | B2 |
8129246 | Babcock et al. | Mar 2012 | B2 |
8129797 | Chen et al. | Mar 2012 | B2 |
8134159 | Hokazono | Mar 2012 | B2 |
8143120 | Kerr et al. | Mar 2012 | B2 |
8143124 | Challa et al. | Mar 2012 | B2 |
8143678 | Kim et al. | Mar 2012 | B2 |
8148774 | Mori et al. | Apr 2012 | B2 |
8163619 | Yang et al. | Apr 2012 | B2 |
8173502 | Yan et al. | May 2012 | B2 |
8178430 | Kim et al. | May 2012 | B2 |
8183096 | Wirbeleit | May 2012 | B2 |
8183107 | Mathur et al. | May 2012 | B2 |
8236661 | Dennard et al. | Aug 2012 | B2 |
20010014495 | Yu | Aug 2001 | A1 |
20030122203 | Nishinohara et al. | Jul 2003 | A1 |
20030183856 | Wieczorek et al. | Oct 2003 | A1 |
20030202374 | Hayashi | Oct 2003 | A1 |
20040075118 | Heinemann et al. | Apr 2004 | A1 |
20040084731 | Matsuda et al. | May 2004 | A1 |
20050116282 | Pattanayak et al. | Jun 2005 | A1 |
20050250289 | Babcock et al. | Nov 2005 | A1 |
20060022270 | Boyd et al. | Feb 2006 | A1 |
20060049464 | Rao | Mar 2006 | A1 |
20060068555 | Zhu et al. | Mar 2006 | A1 |
20060068586 | Pain | Mar 2006 | A1 |
20060071278 | Takao | Apr 2006 | A1 |
20060154428 | Dokumaci | Jul 2006 | A1 |
20060284633 | Park | Dec 2006 | A1 |
20070040222 | Van Camp et al. | Feb 2007 | A1 |
20070158790 | Rao | Jul 2007 | A1 |
20070238253 | Tucker | Oct 2007 | A1 |
20080067589 | Ito et al. | Mar 2008 | A1 |
20080169493 | Lee et al. | Jul 2008 | A1 |
20080197439 | Goerlach et al. | Aug 2008 | A1 |
20080227250 | Ranade et al. | Sep 2008 | A1 |
20080258198 | Bojarczuk et al. | Oct 2008 | A1 |
20080272409 | Sonkusale et al. | Nov 2008 | A1 |
20090057746 | Sugll et al. | Mar 2009 | A1 |
20090108350 | Cai et al. | Apr 2009 | A1 |
20090134468 | Tsuchiya et al. | May 2009 | A1 |
20090302388 | Cai et al. | Dec 2009 | A1 |
20090311837 | Kapoor | Dec 2009 | A1 |
20090321849 | Miyamura et al. | Dec 2009 | A1 |
20100012988 | Yang et al. | Jan 2010 | A1 |
20100038724 | Anderson et al. | Feb 2010 | A1 |
20100187641 | Zhu et al. | Jul 2010 | A1 |
20110073961 | Dennard et al. | Mar 2011 | A1 |
20110074498 | Thompson et al. | Mar 2011 | A1 |
20110079860 | Verhulst | Apr 2011 | A1 |
20110079861 | Shifren et al. | Apr 2011 | A1 |
20110169082 | Zhu et al. | Jul 2011 | A1 |
20110175170 | Wang et al. | Jul 2011 | A1 |
20110180880 | Chudzik et al. | Jul 2011 | A1 |
20110193164 | Zhu | Aug 2011 | A1 |
20120021594 | Gurtei et al. | Jan 2012 | A1 |
20120056275 | Cai et al. | Mar 2012 | A1 |
20120108050 | Chen et al. | May 2012 | A1 |
20120190177 | Kim et al. | Jul 2012 | A1 |
Number | Date | Country |
---|---|---|
0274278 | Jul 1988 | EP |
59-193066 | Nov 1984 | JP |
4-186774 | Jul 1992 | JP |
8-153873 | Jun 1996 | JP |
8-288508 | Nov 1996 | JP |
2004087671 | Mar 2004 | JP |
2011062788 | May 2011 | WO |
Entry |
---|
Abiko, H et al., “A Channel Engineering Combined with Channel Epitaxy Optimization and TED Suppression for 0.15μm n-n Gate CMOS Technology”, 1995 Symposium on VLSI Technology Digest of Technical Papers, pp. 23-24, 1995. |
Chau, R et al., “A 50nm Depleted-Substrate CMOS Transistor (DST)”, Electron Device Meeting 2001, IEDM Technical Digest, IEEE International, pp. 29.1.1-29.1.4, 2001. |
Ducroquet, F et al. “Fully Depleted Silicon-On-Insulator nMOSFETs with Tensile Strained High Carbon Content Si1-yCy Channel”, ECS 210th Meeting, Abstract 1033, 2006. |
Ernst, T et al., “Nanoscaled MOSFET Transistors on Strained Si, SiGe, Ge Layers: Some Integration and Electrical Properties Features”, ECS Trans. 2006, vol. 3, Issue 7, pp. 947-961, 2006. |
Goesele, U et al., Diffusion Engineering by Carbon in Silicon, Mat. Res. Soc. Symp. vol. 610, 2000. |
Hokazono, A et al., “Steep Channel & Halo Profiles Utilizing Boron-Diffusion-Barrier Layers (Si:C) for 32 nm Node and Beyond”, 2008 Symposium on VLSI Technology Digest of Technical Papers, pp. 112-113, 2008. |
Hokazono, A et al., “Steep Channel Profiles in n/pMOS Controlled by Boron-Doped Si:C Layers for Continual Bulk-CMOS Scaling”, IEDM09-676 Symposium, pp. 29.1.1-29.1.4, 2009. |
Holland, OW and Thomas, DK “A Method to Improve Activation of Implanted Dopants in SiC”, Oak Ridge National Laboratory, Oak Ridge, TN, 2001. |
Kotaki, H., et al., “Novel Bulk Dynamic Threshold Voltage MOSFET (B-DTMOS) with Advanced Isolation (SITOS) and Gate to Shallow-Well Contact (SSS-C) Processes for Ultra Low Power Dual Gate CMOS”, IEDM 96, pp. 459-462, 1996. |
Lavéant, P. “Incorporation, Diffusion and Agglomeration of Carbon in Silicon”, Solid State Phenomena, vols. 82-84, pp. 189-194, 2002. |
Noda, K et al., “A 0.1-μm Delta-Doped MOSFET Fabricated with Post-Low-Energy Implanting Selective Epitaxy” IEEE Transactions on Electron Devices, vol. 45, No. 4, pp. 809 -814, Apr. 1998. |
Ohguro, T et al., “An 0.18-μm CMOS for Mixed Digital and Analog Aplications with Zero-Volt-Vth Epitaxial-Channel MOSFET's”, IEEE Transactions on Electron Devices, vol. 46, No. 7, pp. 1378 -1383, Jul. 1999. |
Pinacho, R et al., “Carbon in Silicon: Modeling of Diffusion and Clustering Mechanisms”, Journal of Applied Physics, vol. 92, No. 3, pp. 1582-1588, Aug. 2002. |
Robertson, LS et al., “The Effect of Impurities on Diffusion and Activation of Ion Implanted Boron in Silicon”, Mat. Res. Soc. Symp. vol. 610, 2000. |
Scholz, R et al., “Carbon-Induced Undersaturation of Silicon Self-Interstitials”, Appl. Phys. Lett. 72(2), pp. 200-202, Jan. 1998. |
Scholz, RF et al., “The Contribution of Vacancies to Carbon Out-Diffusion in Silicon”, Appl. Phys. Lett., vol. 74, No. 3, pp. 392-394, Jan. 1999. |
Stolk, PA et al., “Physical Mechanisms of Transient Enhanced Dopant Diffusion in Ion-Implanted Silicon”, J. Appl. Phys. 81(9), pp. 6031-6050, May 1997. |
Thompson, S et al., “MOS Scaling: Transistor Challenges for the 21st Century”, Intel Technology Journal Q3' 1998, pp. 1-19, 1998. |
Wann, C. et al., “Channel Profile Optimization and Device Design for Low-Power High-Performance Dynamic-Threshold MOSFET”, IEDM 96, pp. 113-116, 1996. |
Werner, P. et al., “Carbon Diffusion in Silicon”, Applied Physics Letters, vol. 73, No. 17, pp. 2465-2467, Oct. 1998. |
Yan, Ran-Hong et al., “Scaling the Si MOSFET: From Bulk to SOI to Bulk”, IEEE Transactions on Electron Devices, vol. 39, No. 7, Jul. 1992. |