Patent Application
20240147730
The present disclosure relates generally to the field of semiconductor devices and specifically to transistor circuits including fringeless transistors and methods of making the same.
Peripheral (i.e., driver) circuitry for a memory device includes multiple types of field effect transistors configurated to operate at different operating voltages. Providing field effect transistors that operate at different operating voltages at a high device density is a challenge.
According to an aspect of the present disclosure, a semiconductor structure comprises: a first field effect transistor comprising a first active region and a first gate electrode that comprises a first semiconductor gate electrode portion; a first trench isolation structure laterally surrounding the first active region; a second field effect transistor comprising a second active region and a second gate electrode that comprises a stack of a lower semiconductor gate electrode portion and an upper semiconductor gate electrode portion; a second trench isolation structure laterally surrounding the second active region; and at least one dielectric material layer overlying the first field effect transistor and the second field effect transistor, wherein: the first semiconductor gate electrode portion contacts sidewall surface segments of the first trench isolation structure and comprises a top surface contacting the at least one dielectric material layer; the lower semiconductor gate electrode portion has a same material composition and a same thickness as the first semiconductor gate electrode portion, and contacts sidewall surface segments of the second trench isolation structure; and the upper semiconductor gate electrode portion comprises a bottom surface contacting the lower semiconductor gate electrode and top surface segments of the second shallow trench isolation structure.
According to another aspect of the present disclosure, a method of forming a semiconductor structure comprises: forming a first patterned stack including a first gate dielectric layer and a first gate semiconductor material portion and a second patterned stack including a second gate dielectric layer and a second gate semiconductor material portion over a semiconductor substrate, wherein the first gate semiconductor material portion and the second gate semiconductor material portion comprise patterned portions of a first semiconductor material layer; forming shallow trench isolation structures around the first patterned stack and the second patterned stack, and into an upper portion of the semiconductor substrate; forming a dielectric capping layer directly on the first gate semiconductor material portion; forming a second semiconductor material layer directly on the second gate semiconductor material portion; patterning the second semiconductor material layer, the dielectric capping layer, the first gate dielectric layer, and the second gate dielectric layer to form a first gate electrode comprising a portion of the first gate semiconductor material portion and a second gate electrode comprising a portion of the second gate semiconductor material portion and a patterned portion of the second semiconductor material layer; forming a first field effect transistor by forming a first source region and a first drain region in portions of the semiconductor substrate adjacent to the first gate electrode; and forming a second field effect transistor by forming a second source region and a second drain region in portions of the semiconductor substrate adjacent to the second gate electrode.
According to yet another aspect of the present disclosure, a semiconductor structure comprises: a first field effect transistor comprising a first active region and a first gate electrode that comprises a first semiconductor gate electrode portion and a first metallic gate electrode portion; and a second field effect transistor comprising a second active region and a second gate electrode that comprises a second semiconductor gate electrode portion and a second metallic gate electrode portion, wherein: the first active region comprises a first source region and a first drain region that are laterally spaced from each other by a first channel along a first channel direction; the first gate electrode laterally extends along a first gate electrode direction that is perpendicular to the first channel direction; and a maximum lateral extent of the first metallic gate electrode portion along the first gate electrode direction is greater than a maximum lateral extent of the first semiconductor gate electrode portion along the first gate electrode direction.
According to still another aspect of the present disclosure, a method of forming a semiconductor structure comprises: forming a first patterned stack including a first gate dielectric layer, a first gate semiconductor material portion, and a first hardmask plate over a first portion of a semiconductor substrate; forming a first trench isolation structure around the first patterned stack and into the first portion of the semiconductor substrate; forming a peripheral recess region around the first patterned stack in a portion of the first trench isolation structure that is proximal to the first hardmask plate by vertically recessing a portion of the first trench isolation structure; forming a stepped cavity by removing the first hardmask plate, wherein the stepped cavity comprises a volume from which the first hardmask plate is removed and a volume of the peripheral recess region; forming a stepped metallic plate in the stepped cavity, wherein the stepped metallic plate comprise a first region having a first thickness and a second region having a second thickness that is less than the first thickness; patterning the stepped metallic plate and the first semiconductor gate semiconductor material portion into a first gate electrode; and forming a first field effect transistor by forming a first source region and a first drain region in the first portion of the semiconductor substrate adjacent to the first gate electrode.
According to another aspect of the present disclosure, a semiconductor structure comprises: a first field effect transistor; a second field effect transistor; and a third field effect transistor. The second field effect transistor and the third field effect transistor comprise a shared source/drain region, and are located in a same second active region; the second field effect transistor comprises a second gate electrode which comprises only one semiconductor layer; the third field effect transistor comprises a third gate electrode which comprises two different semiconductor layers; a gate length of the second gate electrode along a gate length direction that is perpendicular to a channel direction of the second field effect transistor is the same as a width of the second active region along the gate length direction; and a gate length of the third gate electrode along the gate length direction that is perpendicular to the channel direction of the third field effect transistor is greater than the width of the second active region along the gate length direction and is greater than the gate length of the second gate electrode.
According to yet another aspect of the present disclosure, a method of forming a semiconductor structure is provided. The method comprises: depositing and patterning a first semiconductor material layer including a first semiconductor material over a semiconductor substrate, wherein patterned portions of the first semiconductor material layer comprise a lower semiconductor plate, a first-transistor lower gate material portion, and a second-transistor gate material portion; forming a dielectric plate over the lower semiconductor plate; depositing and patterning a second semiconductor material layer including a second semiconductor material, wherein patterned portions of the second semiconductor material layer comprises a middle semiconductor plate that is formed on the dielectric plate; depositing a third semiconductor material layer including a third semiconductor material over the patterned portions of the second semiconductor material layer; forming a first-transistor upper gate material portion by patterning a first portion of the third semiconductor material layer; patterning a second portion of the third semiconductor material layer and the first-transistor lower gate electrode portion into a first gate electrode of a first field effect transistor; and patterning the second-transistor gate material portion into a second gate electrode of a second field effect transistor.
According to another aspect of the present disclosure, a semiconductor structure comprises: a first field effect transistor; a second field effect transistor; and a third field effect transistor. The second field effect transistor and the third field effect transistor comprise a shared source/drain region, and are located in a same second active region; the second field effect transistor comprises a second gate electrode which comprises a second lower semiconductor gate electrode portion and a second upper semiconductor gate electrode portion; the third field effect transistor comprises a third gate electrode which comprises a third lower semiconductor gate electrode portion and a third upper semiconductor gate electrode portion; the third gate electrode is thicker than the second gate electrode; a gate length of the second gate electrode along a gate length direction that is perpendicular to a second channel direction of the second field effect transistor is the same as a width of the second active region along the gate length direction; and a gate length of the third gate electrode along the gate length direction that is perpendicular to the second channel direction is greater than the width of the second active region along the gate length direction and is greater than the gate length of the second gate electrode.
According to even further another aspect of the present disclosure, a method of forming a semiconductor structure is provided. The method comprises: depositing and patterning a first semiconductor material layer including a first semiconductor material over a semiconductor substrate, wherein patterned portions of the first semiconductor material layer comprises a first-transistor lower gate material portion and a second-transistor lower gate material portion; forming a first trench isolation structure around the first-transistor lower gate material portion and forming a second trench isolation structure around the second-transistor lower gate material portion; depositing and patterning a second semiconductor material layer including a second semiconductor material over the first-transistor lower gate material portion and the second-transistor lower gate material portion; thinning a first portion of the second semiconductor material layer overlying a first segment of the second-transistor lower gate material portion without thinning a second portion of the second semiconductor material layer overlying the first-transistor lower gate material portion, wherein a thinned portion of the second semiconductor material layer has a top surface that is formed entirely below a horizontal plane including a top surface of the second trench isolation structure; and patterning the second semiconductor material layer, the first-transistor lower gate material portion, and a second-transistor lower gate material portion to form a first gate electrode that comprises a patterned portion of the second portion of the second semiconductor material layer and a patterned portion of the first-transistor lower gate material portion, and to form a second gate electrode that comprises a patterned portion of the thinned portion of the second semiconductor material layer and a patterned portion of the second-transistor lower gate material portion.
Embodiments of the present disclosure provide transistor circuits including fringeless transistors and methods of making the same, the various aspects of which are described below. Such high density transistor circuits including fringeless transistors may be employed in various applications such as sense amplifier and peripheral low voltage driver circuits of memory device, such as a three-dimensional memory array.
The drawings are not drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure. The same reference numerals refer to the same element or similar element. Unless otherwise indicated, elements having the same reference numerals are presumed to have the same composition. As used herein, a first element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, a first element is located “directly on” a second element if there exist a physical contact between a surface of the first element and a surface of the second element.
As used herein, a “layer” refers to a material portion including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. For example, a layer may be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer may extend horizontally, vertically, and/or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and/or may have one or more layer thereupon, thereabove, and/or therebelow.
As used herein, a “layer stack” refers to a stack of layers. As used herein, a “line” or a “line structure” refers to a layer that has a predominant direction of extension, i.e., having a direction along which the layer extends the most.
As used herein, a “semiconducting material” refers to a material having electrical conductivity in the range from 1.0×10−6 S/cm to 1.0×105 S/cm. As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1.0×10−6 S/cm to 1.0×105 S/cm in the absence of electrical dopants therein, and is capable of producing a doped material having electrical conductivity in a range from 1.0 S/cm to 1.0×105 S/cm upon suitable doping with an electrical dopant. As used herein, an “electrical dopant” refers to a p-type dopant that adds a hole to a valence band within a band structure, or an n-type dopant that adds an electron to a conduction band within a band structure. As used herein, a “conductive material” refers to a material having electrical conductivity greater than 1.0×105 S/cm. As used herein, an “insulator material”, “insulating material” or a “dielectric material” refers to a material having electrical conductivity less than 1.0×10'S/cm. As used herein, a “heavily doped semiconductor material” refers to a semiconductor material that is doped with electrical dopant at a sufficiently high atomic concentration to become a conductive material, i.e., to have electrical conductivity greater than 1.0×105 S/cm. A “doped semiconductor material” may be a heavily doped semiconductor material, or may be a semiconductor material that includes electrical dopants (i.e., p-type dopants and/or n-type dopants) at a concentration that provides electrical conductivity in the range from 1.0×10−6 S/cm to 1.0×105 S/cm. An “intrinsic semiconductor material” refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material may be semiconducting or conductive, and may be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive depending on the atomic concentration of electrical dopants therein. As used herein, a “metallic material” refers to a conductive material including at least one metallic element therein. All measurements for electrical conductivities are made at the standard condition.
As used herein, a “field effect transistor” refers to any semiconductor device having a semiconductor channel through which electrical current flows with a current density modulated by an external electrical field. As used herein, a “channel region” refers to a semiconductor region in which mobility of charge carriers is affected by an applied electrical field. A “gate electrode” refers to a conductive material portion that controls electron mobility in the channel region by application of an electrical field. A “source region” refers to a doped semiconductor region that supplies charge carriers that flow through the channel region. A “drain region” refers to a doped semiconductor region that receives charge carriers supplied by the source region and passes through the channel region. A “source/drain region” may be a source region or a drain region. An “active region” collectively refers to a source region, a drain region, and a channel region of a field effect transistor. A “source extension region” refers to a doped semiconductor region that is a portion of a source region and having a lesser dopant concentration than the rest of the source region. A “drain extension region” refers to a doped semiconductor region that is a portion of a drain region and having a lesser dopant concentration than the rest of the drain region. An “active region extension” refers to a source extension region or a drain extension region.
Referring to
The semiconductor substrate 2 can include a substrate semiconductor layer 4 that includes a lightly doped semiconductor material portion, on which at least one field effect transistor can be formed. In one embodiment, the entirety of the semiconductor substrate 2 may be the substrate semiconductor layer 4. In another embodiment, the substrate semiconductor layer 4 may comprise an upper portion of the semiconductor substrate 2, such as doped well in a silicon wafer. The substrate semiconductor layer 4 may include a lightly doped semiconductor material including electrical dopants at an atomic concentration in a range from 1.0×1014/cm3 to 1.0×1018/cm3, such as from 1.0×1015/cm3 to 1.0×1017/cm3, although lesser and greater atomic concentrations can also be employed.
The semiconductor material of the substrate semiconductor layer 4 can be an elemental semiconductor material (such as silicon) or an alloy of at least two elemental semiconductor materials (such as a silicon-germanium alloy), or can be a compound semiconductor material (such as a III-V compound semiconductor material or a II-VI compound semiconductor material), or can be an organic semiconductor material. The thickness of the substrate semiconductor layer 4 can be in a range from 0.5 mm to 2 mm in case the semiconductor substrate 2 is a bulk semiconductor substrate. In case the semiconductor substrate 2 is a semiconductor-on-insulator substrate, the thickness of the substrate semiconductor layer 4 may be in a range from 100 nm to 1,000 nm, although lesser and greater thicknesses can also be employed.
Various doped wells (5, 6) can be formed in an upper portion of the semiconductor substrate 2 (e.g., in the substrate semiconductor layer 4). The various doped wells (5, 6) may include p-type wells 5 having a respective p-type doping and n-type wells 6 having a respective n-type doping. For example, the p-type wells 5 may include a first p-type well 6A, a second p-type well 5B, a third p-type well 5C, etc. The n-type wells 6 may include a first n-type well 6A, a second n-type well 6B, a third n-type well 6C, a fourth n-type well 6D, etc. The regions including the various doped wells (5, 6) may be employed to form various semiconductor devices. For example, the region including the first n-type well 6A may comprise a first p-type field effect transistor region 100 in which first p-type field effect transistors including p-doped source and drain regions are to be subsequently formed; the region including the first p-type well 5A may comprise a first n-type field effect transistor region 200 in which first n-type field effect transistors including n-doped source and drain regions are to be subsequently formed; the region including the second n-type well 6B may comprise a second p-type field effect transistor region 300 in which second p-type field effect transistors including p-doped source and drain regions are to be subsequently formed; the region including the second p-type well 5B may comprise a second n-type field effect transistor region 400 in which second n-type field effect transistors including n-doped source and drain regions are to be subsequently formed; the region including the third n-type well 6C may comprise a third p-type field effect transistor region 500 in which third p-type field effect transistors including p-doped source and drain regions are to be subsequently formed; and the region including the third p-type well 5C may comprise a third n-type field effect transistor region 600 in which third n-type field effect transistors including n-doped source and drain regions are to be subsequently formed. Optionally, the region including the fourth n-doped well 6D may comprise a first passive device region 700 in which a first passive device such as a resistor is subsequently formed. Optionally, a region in which the substrate semiconductor layer 4 is physically exposed may be employed for a passive device region, such as a second passive device region 800, in which a second passive device such as a capacitor is subsequently formed. For example, regions 100 and 200 may contain low voltage transistors, regions 300 and 400 may contain very low voltage transistors which operate at a lower voltage than the low voltage transistors, and regions 500 and 600 may contain high voltage transistors which operate at a higher voltage than the low voltage transistors.
The various device regions may be arranged in any pattern on a top surface of the semiconductor substrate 2. While the present disclosure is described employing an embodiment in which the direction of semiconductor channels (i.e., the direction of current flow in the channel regions of the field effect transistors) is parallel to a first horizontal direction hd1 and perpendicular to a second horizontal direction hd2, it is understood that the direction of the semiconductor channel may be oriented along any direction for each field effect transistor to be subsequently formed. The depth of each doped well (5, 6) and the dopant concentration in each doped well (5, 6) may be suitably selected. For example, the dopant concentration in each doped well (5, 6) may be in a range from 1.0×1014/cm3 to 1.0×1018/cm3, such as from 1.0×1015/cm3 to 1.0×1017/cm3, although lesser and greater atomic concentrations can also be employed. The depth of each well (5, 6) may be in a range from 50 nm to 2,000 nm, although lesser and greater depths may also be employed.
Referring to
A polish stop pad layer 23L and a semiconductor material layer 24L may be formed over the first and second gate dielectric layers (22L, 20L). The polish stop pad layer 23L may comprise any suitable sacrificial material, such as silicon nitride and/or a bilayer of silicon nitride and silicon oxide, which may be used as a polish stop. The semiconductor material layer 24L may comprise a heavily doped polysilicon layer. Optionally, the polish stop pad layer 23L may also be formed on top of the semiconductor material layer 24L. The thickness of layers (23L, 24L) may be in a range from 50 nm to 300 nm, such as from 100 nm to 200 nm, although lesser and greater thicknesses may also be employed.
Referring to
Referring to
Referring to
The remaining portions of the at least one trench fill material layer 8L filling the trenches 7 constitute trench isolation structures 8, which may be a continuous structure contacting the semiconductor material of the semiconductor substrate 2 with dielectric surfaces and providing electrical isolation between adjacent semiconductor devices to be subsequently formed. The trench isolation structures 8 include deep trench isolation structures 8D located in the deep trenches 7D and shallow trench isolation structures 8S located in the shallow trenches 7S.
Generally, a trench isolation structure 8 can be formed through the plates (23L, 24L) and the gate dielectric layers (22L, 20L). Patterned portions of the semiconductor material layer 24L and the first gate dielectric layer 22L comprise stacks of a gate dielectric plate 22 and a gate electrode material plate 24 that is laterally surrounded by a respective portion of the trench isolation structure 8.
Referring to
Referring to
An anisotropic etch process can be performed to remove unmasked portions of the planar semiconductor spacer layer 34L and the planar dielectric spacer layer 30L. Top surfaces of the plates 23 and the trench isolation structure 8 can be physically exposed in the third p-type field effect transistor region 500 and the third n-type field effect transistor region 600. In one embodiment, an opening through the planar semiconductor spacer layer 34L and the planar dielectric spacer layer 30L in the first p-type field effect transistor region 100 and in the first n-type field effect transistor region 200 may include an area of a portion of the shallow trench isolation structure 8S, an area of a portion of a first gate electrode material plate 24, and an area of a portion of another first gate electrode material plate 24.
Generally, the planar semiconductor spacer layer 34L and the planar dielectric spacer layer 30L can be patterned employing an etch process that employs an etch mask, such as a patterned photoresist layer. A portion of the top surface of the first semiconductor material layer 24L (comprising a portion of the top surface of a first semiconductor gate material plate 24) is physically exposed by patterning the planar semiconductor spacer layer 34L and the planar dielectric spacer layer 30L. The photoresist layer can be subsequently removed, for example, by ashing.
Referring to
A gate cap dielectric layer 50L can be subsequently deposited over the conductive gate cap layer 40L. The gate cap dielectric layer 50L includes a dielectric material, such as silicon nitride. The thickness of the gate cap dielectric layer 50L can be in a range from 20 nm to 100 nm, such as from 30 nm to 50 nm, although lesser and greater thicknesses may also be employed.
Referring to
A first anisotropic etch process can be performed to transfer the pattern in the first photoresist layer 53 through the gate cap dielectric layer 50L, the conductive gate cap layer 40L, the planar semiconductor spacer layer 34L, and portions of the plates 23 located outside the areas of the planar dielectric spacer layer 30L, which include portions of plates 23 located within the third p-type field effect transistor region 500 and the third n-type field effect transistor region 600. The planar dielectric spacer layer 30L, the second gate dielectric plate 20, and the trench isolation structure 8 can function as etch stop structures for the first anisotropic etch process. In case the planar dielectric spacer layer 30L, the second gate dielectric plate 20, and the trench isolation structure 8 comprise silicon oxide, the etch chemistry of the terminal step of the first anisotropic etch process can etch the semiconductor materials of the planar semiconductor spacer layer 34L and the plates 23 selective to silicon oxide.
Each patterned portion of the gate cap dielectric layer SOL comprises a gate cap dielectric 50. Each patterned portion of the conductive gate cap layer 40L comprises a conductive gate cap structure 40. Each patterned portion of the planar semiconductor spacer layer 34L comprises a planar semiconductor spacer plate 34.
A contiguous combination of a first gate cap dielectric 50, a first conductive gate cap structure 40, and a first planar semiconductor spacer plate 34 can be formed on a top surface of each gate electrode material plate 24 in the first p-type field effect transistor region 100 and/or in the first n-type field effect transistor region 200. In this case, the first conductive gate cap structure 40 can be formed on the physically exposed top surface of a portion of the first gate electrode material plate 24. According to an aspect of the present disclosure, a first conductive gate cap structure 40 in the first p-type field effect transistor region 100 or in the first n-type field effect transistor region 200 comprises a first segment that contacts portion of the top surface of an underlying gate electrode material plate 24; a second segment that overlies the first planar dielectric spacer layer 34L; and a connecting segment that contacts a first sidewall of the first planar dielectric spacer layer 34L and connecting the first segment and the second segment.
According to an aspect of the present disclosure, a portion of the first conductive gate cap structure 40 covers a portion of a top surface of an underlying portion of the shallow trench isolation structure 8, and a portion of a bottom surface of the first conductive gate cap structure 40 contacts the portion of the top surface of the underlying portion of the shallow trench isolation structure 8. A first sidewall of the first planar semiconductor spacer plate 34 overlies, and is vertically coincident with, the first sidewall of the planar dielectric spacer layer 30L, and contacts the connecting segment of the first conductive gate cap structure 40. The first planar semiconductor spacer plate 34 can be formed on a top surface of the planar dielectric spacer layer 30L while a semiconductor gate plate 24 (i.e., a portion of the semiconductor material layer 24L) is covered with the planar dielectric spacer layer 30L. The first conductive gate cap structure 40 is formed directly on the first planar semiconductor spacer plate 34. The first photoresist layer 53 can be subsequently removed, for example, by ashing.
Referring to
Referring to
Generally, stacks of a first gate dielectric plate 22 and a gate electrode material plate 24 can be patterned into a stack of a first gate dielectric 12 and a first gate electrode 14. The gate electrode material plate 24 is patterned into the gate electrode 14 by the second anisotropic etch process employing the photoresist layer 57 as a patterned etch mask. The first gate dielectric plate 22 and the planar dielectric spacer layer 30L can be patterned into the first gate dielectric 12 and a first planar dielectric spacer plate 30, respectively, by a same etch process such as the second anisotropic etch process.
A first planar dielectric spacer plate 30 covers a first portion of a top surface of the gate electrode 14 upon patterning the first gate electrode material plate 24 into the first gate electrode 14. A first portion of a top surface of the gate electrode 14 contacts a bottom surface of the first planar dielectric spacer plate 30. A first conductive gate cap structure 40 comprises a first segment that contacts a second portion of the top surface of the gate electrode 14 a second segment that overlies the first planar dielectric spacer plate 30, and a connecting segment that contacts a first sidewall of the first planar dielectric spacer plate 30 and connecting the first segment and the second segment.
Referring to
The anisotropic etch process may be extended to etch unmasked portions of the dielectric materials of the second gate dielectric plates 20 and the trench isolation structures 8 selective to the materials of the gate electrodes 14. In this case, the second gate dielectric plates 20 can be patterned into second gate dielectrics 10 (which may comprise portions of a composite silicon nitride/silicon oxide gate dielectrics (10, 13) for the high voltage transistors in regions 500 and 600), and the physically exposed top surfaces of the trench isolation structures 8 can be vertically recessed. In one embodiment, an outer sidewall of each second gate dielectric 10 can be vertically coincident with an outer sidewall of a respective one of the dielectric gate spacers 56. As used herein, a first surface and a second surface are vertically coincident with each other if the first surface and the second surface overlie or underlie each other, and are located within a same vertical plane. In one embodiment, the recessed portions of the top surfaces of the trench isolation structure 8 may be at, or about, the height of the top surfaces of the third doped wells (5C, 5D) in the third field effect transistor regions (500, 600).
In one embodiment, a first dielectric gate spacer 56 located within a first field effect transistor region (100 or 200) comprises an upper portion that laterally surrounds and contacts a first conductive gate cap structure 40 and the planar semiconductor spacer plate 34, and contacts a portion of a top surface of the first planar dielectric spacer plate 30. The first dielectric gate spacer 56 contacts a first sidewall of the first semiconductor spacer plate 34 that is vertically coincident with a first sidewall of the first planar dielectric spacer plate 30, and a second sidewall of the first planar semiconductor spacer plate 34 that is laterally offset from a second sidewall of the first planar dielectric spacer plate 34. An outer sidewall of the first dielectric gate spacer 56 can be vertically coincident with the second sidewall of the first planar dielectric spacer plate 30.
The first planar semiconductor spacer plate 34 can contact a top surface of the first planar dielectric spacer plate 30, can have a lesser area than the first planar dielectric spacer plate 30, and can contact a bottom surface of the second segment of the first conductive gate cap structure 40 that overlies the stack of the first planar dielectric spacer plate 30 and the first planar semiconductor spacer plate 34. A portion of the first conductive gate cap structure 40 covers a top surface of a first portion of the shallow trench isolation structure 8 that surrounds a portion of a first doped well (5A or 6A) that underlies a gate structure (12, 14, 30, 34, 40, 50) and the first dielectric gate spacer 56. As shown in
A first gate structure (12, 14, 30, 34, 40, 50) including a first gate dielectric 12, a first gate electrode 14, a first planar dielectric spacer plate 30, and a first conductive gate cap structure 40 overlies a first channel region 15 of a first (e.g., low voltage or very low voltage) field effect transistor in regions 100 and 200, as shown in
In one embodiment, the first gate dielectric 12 and the first gate electrode 14 contact a sidewall of a protruding region (i.e., a protruding segment) 8P2 of the portion of the trench isolation structure 8. The sidewall laterally extends along a first horizontal direction hd1. The first planar dielectric spacer plate 30 contacts a first portion of a top surface of the first gate electrode 14, and the first conductive gate cap structure 40 comprises a first segment that contacts a second portion of the top surface of the first gate electrode 14, a second segment that overlies the first planar dielectric spacer plate 30, and a connecting segment that contacts a first sidewall of the first planar dielectric spacer plate 30 and connecting the first segment and the second segment.
In one embodiment, the first gate dielectric 12 comprises a first sidewall that contacts the sidewall of the protruding region 8P2 of the first portion of the trench isolation structure 8. The first gate electrode 14 comprises a first sidewall that contacts the sidewall of the protruding region 8P2 of the first portion of the trench isolation structure 8. A second sidewall of the first gate dielectric 12 and a second sidewall of the first gate electrode 14 that laterally extend along the first horizontal direction hd1 contacts a sidewall of a lower portion of the first dielectric gate spacer 56. Additional sidewalls of the first gate dielectric 12 and the first gate electrode 14 contact additional sidewalls of the lower portion of the first dielectric gate spacer 56 that laterally extends along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1.
A second gate structure (10, 13, 40, 50) including a second composite silicon nitride/silicon oxide gate dielectric (13, 10), a second gate electrode 40 (which comprises a second conductive gate cap structure 40) overlies a second channel region 17 of a second (e.g., high voltage) field effect transistor in regions 500 and 600, as shown in
Referring to
In one embodiment, configurations for increasing the breakdown voltage of field effect transistors may be employed in device regions in which high-voltage field effect transistors are formed such as the third field effect transistor regions (500, 600). In this case, the p-doped source/drain regions 65 may include inner p-doped source/drain regions 651 and outer p-doped source/drain regions 650 that are laterally spaced apart by an additional trench isolation structure 8 (e.g., deep trench isolation structure 8D), which may be disjoined from the trench isolation structure 8 (e.g., shallow trench isolation structure 8S) in the first field effect transistor regions (100, 200). Further, the n-doped source/drain regions 66 may include inner n-doped source/drain regions 661 and outer n-doped source/drain regions 660 that are laterally spaced apart by another additional trench isolation structure 8. Optionally, a well contact source/drain region 65W may be employed to facilitate biasing of a doped well.
In one embodiment, gate electrodes 14 located within the low and very low voltage field effect transistor regions (100, 200, 300, 400) may be doped with p-type dopants or n-type dopants to form doped gate electrodes (25, 26) that are doped with p-type dopants or n-type dopants. The doped gate electrodes (25, 26) include p-doped second gate electrodes 25 formed in the p-type field effect transistor regions (100, 300) and n-doped second gate electrodes 26 formed in the n-type field effect transistor regions (200, 400). Alternatively or in addition, the polysilicon gate electrodes 14 and/or heavily doped semiconductor (e.g., heavily doped polysilicon) conductive gate cap structures 40 may be silicided by forming a metal on the polysilicon 14 and annealing the metal to form a metal silicide on the exposed top surfaces of the polysilicon.
Generally, various field effect transistors having different gate dielectric thicknesses, different gate lengths (i.e., different lateral distances between a source region and a drain region), and different configurations can be formed in the various field effect transistor regions (100, 200, 300, 400, 500, 600).
Referring to
The contact-level dielectric layer 70 overlies and laterally surrounds each of the field effect transistors. In one embodiment shown in
The contact via structures (76A, 76G, 86A, 86G, 96A, 96G, 96R, 96C) comprise first source/drain region contact via structures 76A contacting source/drain regions (65, 66) within the first field effect transistor regions (100, 200), as shown in
Generally, a first field effect transistor can be formed in a first field effect transistor region (100 or 200). The first field effect transistor comprises a first active region having a pair of lengthwise sidewalls and a pair of widthwise sidewalls that contact sidewalls of and are laterally surrounded by a first portion of a trench isolation structure 8. The first active region comprises a first source region, a first drain region, and a first channel region located between the first source region and the first drain region. The first field effect transistor can comprise a first gate structure (12, 14, 25 or 26, 30, 34, 40, 50).
A second field effect transistor can be formed in a second field effect transistor region (300 or 400). The second field effect transistor comprises a second active region having a pair of lengthwise sidewalls and a pair of widthwise sidewalls that contact sidewalls of and are laterally surrounded by a second portion of the trench isolation structure 8. A second gate structure (12, 25 or 26) including a second gate dielectric 12 and a second gate electrode (25 or 26) overlies the second active region. The contact-level dielectric layer 70 overlies the first gate structure (12, 14, 25 or 26, 30, 34, 40, 50) and the second gate structure (12, 25 or 26). At least one gate contact structure (such as a second gate contact via structures 86G) is in contact with a portion of a top surface of the second gate electrode (25 or 26). An entirety of the top surface of the second gate electrode (25 or 26) that is not in contact with the at least one gate contact structure 86G is in contact with the contact-level dielectric layer 70.
The first exemplary structure can comprise an additional field effect transistor such as a third field effect transistor formed in a third field effect transistor region (500 or 600). The additional field effect transistor comprises an additional active region having a pair of lengthwise sidewalls and a pair of widthwise sidewalls that contact sidewalls of and are laterally surrounded by an additional portion of the trench isolation structure 8. The additional field effect transistor comprises an additional gate structure (10, 13, 40, 50) overlies the additional active region. The additional gate structure (10, 13, 40, 50) can include an additional composite gate dielectric comprising a silicon oxide sublayer 10 having a greater thickness than the first gate dielectric 12, and a silicon nitride sublayer 13, and an additional conductive gate cap structure 40 having a same thickness and a same material composition as the first segment of the first conductive gate cap structure 40. An entirety of a top surface of the silicon nitride portion 13 is in contact with a bottom surface of the additional conductive gate cap structure 40.
In one embodiment, the first exemplary structure may further comprise a passive device, which may be selected from a capacitor, a resistor, or any other passive device known in the art. The passive device comprises a layer stack including, from bottom to top, a first dielectric layer (such as another instance of a silicon oxide gate dielectric 12 and a silicon nitride portion 13), a second dielectric layer (such as a planar dielectric spacer plate 30), a semiconductor plate (such as a planar semiconductor spacer plate 34), and a metallic plate (such as a conductive gate cap structure 40). The second dielectric layer has a same material composition and a same thickness as the first planar dielectric spacer plate 30. The metallic plate has a same material composition and a same thickness as the first segment of the first conductive gate cap structure 40.
Referring to
Generally, at least one gate dielectric layer and at least one semiconductor material layer over a semiconductor material layer within the semiconductor substrate 2, and a trench isolation structure 8 can be formed through the at least one semiconductor material layer and the at least one gate dielectric layer. As shown in
The first stack (22A, 24A) and the second stack (22B, 24B) can be located within a same field effect transistor region such as the first n-type field effect transistor region 200. The trench isolation structure 8 comprises a frame portion 8F that laterally surrounds the first active region 51 and the second active region 52 continuously. A laterally-extending portion 8L of the trench isolation structure 8 can be located between the first active region 51 and the second active region 52.
Referring to
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A first anisotropic etch process can be performed to transfer the pattern in the first photoresist layer 53 through the gate cap dielectric layer SOL, the conductive gate cap layer 40L, the planar semiconductor spacer layer 34L, and portions of the plates 23 located outside the areas of the planar dielectric spacer layer 30L located within the third p-type field effect transistor region 500 and the third n-type field effect transistor region 600. The planar dielectric spacer layer 30L, the second gate dielectric plate 20, and the trench isolation structure 8 can function as etch stop structures for the first anisotropic etch process. In case the planar dielectric spacer layer 30L, the second gate dielectric plate 20, and the trench isolation structure 8 comprise silicon oxide, the etch chemistry of the terminal step of the first anisotropic etch process can etch the semiconductor materials of the planar semiconductor spacer layer 34L and the silicon nitride plates 23 selective to silicon oxide.
Each patterned portion of the gate cap dielectric layer SOL comprises a gate cap dielectric 50. Each patterned portion of the conductive gate cap layer 40L comprises a conductive gate cap structure 40. Each patterned portion of the planar semiconductor spacer layer 34L comprises the planar semiconductor spacer plate 34. Each patterned portion of the gate electrode material plates 126 constitutes a gate electrode 116.
Generally, a first gate electrode material plate 126 can be provided over a first active region 51 and a second gate electrode material plate 126 can be provided over a second active region 52 that is spaced from the first active region by a portion 8L of the trench isolation structure 8. Portions of the first gate electrode material plate 126 and the second gate electrode material plate 126 can be anisotropically etched. Patterned portions of the first gate electrode material plate 126 and the second gate electrode material plate 126 comprise a first gate electrode 116 and a second gate electrode 116, respectively.
According to an aspect of the present disclosure, a sidewall of a conductive gate cap structure 40 can be formed adjacent to an sidewall of the planar semiconductor spacer layer 34L as formed at the processing steps of
A contiguous combination of a first gate cap dielectric 50, a first conductive gate cap structure 40, a first planar semiconductor spacer plate 34, and a pair of first gate electrodes 116 can be formed across a pair of active regions (51, 52) in the first n-type field effect transistor region 200. Generally, each first conductive gate cap structure 40 constitutes a conductive gate connection structure that provide an electrically conductive path between an underlying pair of first gate electrodes 116 overlying the pair of active regions (51, 52) separated by the trench isolation structure 8L. Thus, the conductive gate connection material layer which comprises the conductive gate cap layer 40L can be patterned into conductive gate connection structure which comprises the first conductive gate cap structures 40. The first photoresist layer 53 can be subsequently removed, for example, by ashing.
Referring to
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Subsequently, another anisotropic etch process may be optionally performed to pattern the gate dielectric plates 22 located within the first field effect transistor regions (100, 200). Portions of the gate dielectric plates 22 that do not underlie a gate electrode 126 can be etched, and remaining portions of the gate dielectric plates 22 in the first field effect transistor regions (100, 200) constitute gate dielectrics 12.
A stack of a first gate dielectric 12 and a first gate electrode 116 overlies a first channel region within the first active region 51 in a first field effect transistor region (100 or 200) and contacts a first sidewall of the laterally-extending portion 8F of the trench isolation structure 8. A stack of a second gate dielectric 12 and a second gate electrode 116 overlies a second channel region within the second active region 52 and contacts a second sidewall of the laterally-extending portion 8F of the trench isolation structure 8. A conductive gate connection structure (comprising the first conductive gate cap structure 40) contacts a top surface of the first gate electrode 116, a top surface of the second gate electrode 116, and a portion of a top surface of the laterally-extending portion 8F of the trench isolation structure 8. The conductive gate connection structure comprising the first conductive gate cap structure 40 comprises a pair of widthwise sidewalls that laterally extend along a first horizontal direction hd1 and a pair of lengthwise sidewalls that laterally extend along a second horizontal direction hd2.
The trench isolation structure 8 comprises a frame portion 8F that laterally surrounds the first active region and the second active region continuously. The conductive gate connection structure comprising the first conductive gate cap structure 40 comprises a first end portion and a second end portion that overlies and contacts a respective segment of a top surface of the frame portion 8F of the trench isolation structure 8. Lengthwise sidewalls of the first gate electrode 116 and the second gate electrode 116 are vertically coincident with the pair of lengthwise sidewalls of the conductive gate connection structure that laterally extend along the second horizontal direction hd2.
A first widthwise sidewall (extending along the first horizontal direction hd1) of the first gate dielectric 12 and a first widthwise sidewall (extending along the first horizontal direction hd1) of the first gate electrode 116 are vertically coincident with each other and contact a first sidewall of the laterally-extending portion 8L of the trench isolation structure 8. A first widthwise sidewall (extending along the first horizontal direction hd1) of the second gate dielectric 12 and a first widthwise sidewall (extending along the first horizontal direction hd1) of the second gate electrode 116 are vertically coincident with each other and contact a second sidewall of the laterally-extending portion 8L of the trench isolation structure 8.
A second widthwise sidewall (extending along the first horizontal direction hd1) of the first gate dielectric 12 and a second widthwise sidewall (extending along the first horizontal direction hd1) of the first gate electrode 116 are vertically coincident with each other and contact a first sidewall of the frame portion 8F of the trench isolation structure 8. A second widthwise sidewall (extending along the first horizontal direction hd1) of the second gate dielectric 12 and a second widthwise sidewall (extending along the first horizontal direction hd1) of the second gate electrode 116 are vertically coincident with each other and contact a second sidewall of the frame portion 8F of the trench isolation structure 8.
In one embodiment, the conductive gate connection structure comprises a metallic gate connection structure 40 having a first thickness over a predominant segment of the first gate electrode 116, over the laterally-extending portion 8L of the trench isolation structure 8, and over an entire area of the second gate electrode 116, and having a second thickness that is greater than the first thickness over a complementary segment of the first gate electrode 116.
Referring to
The anisotropic etch process may be extended to etch unmasked portions of the dielectric materials of the second gate dielectric plates 20 and the trench isolation structures 8 selective to the materials of the gate electrodes 116. The planar dielectric spacer plates 30 in the second field effect transistor regions (300, 400) can be collaterally etched during the anisotropic etch process. In this case, the second gate dielectric plates 20 in the third field effect transistor regions (500, 600) can be patterned into second gate dielectrics 10, and the physically exposed top surfaces of the trench isolation structures 8 can be vertically recessed. In one embodiment, an outer sidewall of each second gate dielectric 10 can be vertically coincident with an outer sidewall of a respective one of the dielectric gate spacers 56. In one embodiment, the recessed portions of the top surfaces of the trench isolation structure 8 may be at, or about, the height of the top surfaces of the third doped wells (5C, 6C) in the third field effect transistor regions (500, 600).
In one embodiment, a first dielectric gate spacer 56 located within a first field effect transistor region (100 or 200) comprises an upper portion laterally surrounding the conductive gate connection structure comprising first conductive gate cap structure 40, and four lower portions vertically extending between a horizontal plane including a top surface of frame portion 8F of the trench isolation structure 8 and a horizontal plane including top surfaces of the first active region and the second active region and contacting a respective lengthwise sidewall of one of the first gate electrode 116 and the second gate electrode 116.
Referring to
In one embodiment, configurations for increasing the breakdown voltage of field effect transistors may be employed in device regions in which high-voltage field effect transistors are formed such as the third field effect transistor regions (500, 600). In this case, the p-doped source/drain regions 65 may include inner p-doped source/drain regions 651 and outer p-doped source/drain regions 650 that are laterally spaced apart by an additional trench isolation structure 8, which may be disjoined from the trench isolation structure 8 in the first field effect transistor regions (100, 200). Further, the n-doped source/drain regions 66 may include inner n-doped source/drain regions 661 and outer n-doped source/drain regions 660 that are laterally spaced apart by another additional trench isolation structure 8. Optionally, a well contact source/drain region 65W may be employed to facilitate biasing of a doped well.
Referring to
The contact via structures (76A, 76G, 86A, 86G, 96A, 96G, 96R, 96C) comprise first source/drain region contact via structures 76A contacting source/drain regions (65, 66) within the first field effect transistor regions (100, 200), first gate contact via structures 76G contacting top surfaces of conductive gate cap structures 40 within the first field effect transistor regions (100, 200), second source/drain region contact via structures 86A contacting source/drain regions (65, 66) within the second field effect transistor regions (300, 400), second gate contact via structures 86G contacting the second gate electrodes (25, 26), third source/drain region contact via structures 96A contacting source/drain regions (65, 66) within the third field effect transistor regions (500, 600), and third gate contact via structures 96G contacting top surfaces of conductive gate cap structures 40 within the third field effect transistor regions (500, 600). Further, the contact via structures (76A, 76G, 86A, 86G, 96A, 96G, 96R, 96C) can comprise first passive device contact via structures 96R that contact first passive devices such as resistors, and second passive device contact via structures 96C that contact second passive devices such as capacitors.
Generally, various field effect transistors having different gate dielectric thicknesses, different gate lengths (i.e., different lateral distances between a source region and a drain region), and different configurations can be formed in the various field effect transistor regions (100, 200, 300, 400, 500, 600). A dielectric gate spacer 56 may overlie a periphery region of a source/drain region (65, 66) of field effect transistors in the second field effect transistor regions (300, 400), and contact sidewalls of a respective portion of the trench isolation structure 8.
The second exemplary structure can include a combination of a first field effect transistor and a second field effect transistor located in a first field effect transistor region (100 or 200). The first field effect transistor and the second field effect transistor comprise a first active region 51 and a second active region 52, respectively. The first active region and the second active region contact sidewalls of, and are laterally surrounded by, a trench isolation structure 8. A laterally-extending portion 8L of the trench isolation structure 8 is located between the first active region 51 and the second active region 52.
The second exemplary structure may comprise a third field effect transistor located in a second field effect transistor region (300 or 400). The third field effect transistor comprises: a third active region that is laterally surrounded by an additional portion of the trench isolation structure 8, a stack of a third gate dielectric 12 and a third gate electrode (116 or 115) having widthwise sidewalls contacting sidewalls of the additional portion of the trench isolation structure 8 and laterally extending along the first horizontal direction hd1, additional dielectric gate spacers 56 having a respective opening therethrough and contacting a respective subset of sidewalls of the additional portion of the trench isolation structure 8 and a respective lengthwise sidewall (which laterally extends along the second horizontal direction hd2) of the third gate electrode (116 or 115).
The first gate electrode 116 and the second gate electrode 116 do not contact the contact-level dielectric layer 70, and are spaced from the contact-level dielectric layer 70 by a first dielectric gate spacer 56 and a conductive gate connection structure (as embodied as a conductive gate cap structure 40). The third gate electrode (116 or 115) can have a same thickness as the first gate electrode 116 and the second gate electrode 116. A portion of a top surface of the third gate electrode (116 or 115) is in direct contact with the contact-level dielectric layer 70.
At least one gate contact structure (such as a first gate contact via structure 76G) extends through the contact-level dielectric layer 70 and contacts a top surface of the portion of the conductive gate connection structure comprising the conductive gate cap structure 40 which at least partially overlies the underlying first gate electrode 116, and at least one additional gate contact structure (such as a second gate contact via structure 86G) extends through the contact-level dielectric layer 70 and contacts a portion of a top surface of the third gate electrode 116. An entirety of the top surface of the third gate electrode 116 is in contact with the at least one additional gate contact structure or the contact-level dielectric layer 70.
The second exemplary structure can comprise an additional field effect transistor such as a fourth field effect transistor formed in a third field effect transistor region (500 or 600). The additional field effect transistor comprises an additional active region having a pair of lengthwise sidewalls and a pair of widthwise sidewalls that contact sidewalls of, and are laterally surrounded by, an additional portion of the trench isolation structure 8. The additional field effect transistor comprises an additional gate structure (10, 13, 40, 50) overlies the additional active region. The additional gate structure (10, 13, 40, 50) can include an additional composite gate dielectric (10, 13) comprising a silicon oxide sublayer 10 having a greater thickness than the first gate dielectric 12, and a silicon nitride sublayer 13, and an additional conductive gate cap structure 40 having a same thickness and a same material composition as the first segment of the first conductive gate cap structure 40. An entirety of a top surface of the silicon nitride sublayer 13 is in contact with a bottom surface of the additional conductive gate cap structure 40.
In one embodiment, the second exemplary structure may comprise a passive device, which may be selected from a capacitor, a resistor, or any other passive device known in the art. The passive device comprises a layer stack including, from bottom to top, a first dielectric layer (such as another instance of a silicon oxide gate dielectric 12 and a silicon nitride gate dielectric 13), a second dielectric layer (such as a planar dielectric spacer plate 30), a second semiconductor plate (such as a planar semiconductor spacer plate 34), and a metallic plate (such as a conductive gate cap structure 40). The first dielectric layer has a same material composition and a same thickness as the first gate dielectric 12. The first semiconductor plate may a same thickness as the first gate electrode (14, 25 or 26). The second dielectric layer has a same material composition and a same thickness as the first planar dielectric spacer plate 30. The metallic plate has a same material composition and a same thickness as the first segment of the first conductive gate cap structure 40.
Referring to
Generally, at least one gate dielectric layer and at least one semiconductor material layer over a semiconductor material layer within the semiconductor substrate 2, and a trench isolation structure 8 can be formed through the at least one semiconductor material layer and the at least one gate dielectric layer. Patterned portions of the at least one semiconductor material layer and the at least one gate dielectric layer comprise a first stack (22, 24) of a first gate dielectric plate 22 and a first gate electrode material plate 24 overlying a first active region of the semiconductor material layer and a second stack (22, 24) of a second gate dielectric plate 22 and a second gate electrode material plate 24 overlying a second active region of the semiconductor material layer. The first stack (22, 24) and the second stack (22, 24) can be located within a same field effect transistor region such as the first n-type field effect transistor region 200. The trench isolation structure 8 comprises a frame portion 8F that laterally surrounds the first active region and the second active region continuously. A laterally-extending portion 8L of the trench isolation structure 8 can be located between the first active region and the second active region. Optionally, masked ion implantation processes can be performed to dope any portion of the gate electrode material plates 24 with suitable conductivity types.
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A stack of a first gate dielectric 12 and a first gate electrode 14 overlies a first channel region within the first active region 51 in a first field effect transistor region (100 or 200) and contacts a first sidewall of the laterally-extending portion 8F of the trench isolation structure 8. A stack of a second gate dielectric 12 and a second gate electrode 14 overlies a second channel region within the second active region 52 and contacts a second sidewall of the laterally-extending portion 8F of the trench isolation structure 8. A first conductive gate connection structure comprising the semiconductor gate cap structure 236 and the conductive gate cap structure 240 contacts a top surface of the first gate electrode 14, a top surface of the second gate electrode 14, and a portion of a top surface of the laterally-extending portion 8F of the trench isolation structure 8. The first conductive gate connection structure comprising the first conductive gate cap structure 240 comprises a pair of widthwise sidewalls that laterally extend along a first horizontal direction hd1 and a pair of lengthwise sidewalls that laterally extend along a second horizontal direction hd2. An entirety of a top surface of the first gate electrode 14 and an entirety of a top surface of the second gate electrode 14 contact a bottom surface of the conductive gate connection structure (236, 240), such as the bottom surface of the semiconductor gate cap structure 236.
The trench isolation structure 8 comprises a frame portion 8F that laterally surrounds the first active region 51 and the second active region 52 continuously. The first conductive gate connection structure comprising as a stack of a semiconductor gate cap structure 236 and a conductive gate cap structure 240 comprises a first end portion and a third end portion that overlies and contacts a respective segment of a top surface of the frame portion 8F of the trench isolation structure 8, as shown in
A first widthwise sidewall (extending along the first horizontal direction hd1) of the first gate dielectric 12 and a first widthwise sidewall (extending along the first horizontal direction hd1) of the first gate electrode 14 are vertically coincident with each other and contact a first sidewall of the laterally-extending portion 8L of the trench isolation structure 8. A first widthwise sidewall (extending along the first horizontal direction hd1) of the second gate dielectric 12 and a first widthwise sidewall (extending along the first horizontal direction hd1) of the second gate electrode 14 are vertically coincident with each other and contact a second sidewall of the laterally-extending portion 8L of the trench isolation structure 8.
A second widthwise sidewall (extending along the first horizontal direction hd1) of the first gate dielectric 12 and a second widthwise sidewall (extending along the first horizontal direction hd1) of the first gate electrode 14 are vertically coincident with each other and contact a first sidewall of the frame portion 8F of the trench isolation structure 8. A second widthwise sidewall (extending along the first horizontal direction hd1) of the second gate dielectric 12 and a second widthwise sidewall (extending along the first horizontal direction hd1) of the second gate electrode 14 are vertically coincident with each other and contact a second sidewall of the frame portion 8F of the trench isolation structure 8.
In one embodiment, the first conductive gate connection structure comprises a metallic gate connection structure includes the conductive gate cap structure 240 having a uniform thickness over the entirety of the first gate electrode 14 (which includes a predominant segment of the first gate electrode 14), over the laterally-extending portion 8L of the trench isolation structure 8, and over the entirety of the second gate electrode 14.
In one embodiment, the first conductive gate connection structure further comprises a semiconductor gate connection structure comprising the semiconductor gate cap structure 236 having a uniform thickness throughout and contacting top surfaces of the first gate electrode 14, the laterally-extending portion of the trench isolation structure 8L, and the second gate electrode 14. In one embodiment, the first conductive gate connection structure also comprises a metallic gate connection structure comprising the conductive gate cap structure 240 contacting an entirety of a top surface of the semiconductor gate connection structure and having a same area as the semiconductor gate structure.
According to an aspect of the present disclosure, second conductive gate connection structure can be provided within the second field effect transistor region (300 and/or 400). The second conductive gate connection structure comprises a stack of a second semiconductor gate cap structure 236 and a second conductive gate cap structure 240. The second semiconductor gate cap structure 236 comprises a first segment that contacts portion of the top surface of an underlying gate electrode 14; a second segment that overlies a planar dielectric spacer plate 34; and a connecting segment that contacts a first sidewall of the planar dielectric spacer plate 34 and connecting the first segment and the second segment.
Referring to
The anisotropic etch process may be extended to etch unmasked portions of the dielectric materials of the first gate dielectrics 12, the second gate dielectric plates 20 and the trench isolation structures 8 selective to the materials of the gate electrodes 14. The planar dielectric spacer plates 30 in the second field effect transistor regions (300, 400) can be collaterally etched during the anisotropic etch process. In this case, the second gate dielectric plates 20 in the third field effect transistor regions (500, 600) can be patterned into second gate dielectrics 10, and the physically exposed top surfaces of the trench isolation structures 8 can be vertically recessed. In one embodiment, an outer sidewall of each second gate dielectric 10 can be vertically coincident with an outer sidewall of a respective one of the dielectric gate spacers 56. In one embodiment, the recessed portions of the top surfaces of the trench isolation structure 8 may be at, or about, the height of the top surfaces of the third doped wells (5C, 6C) in the third field effect transistor regions (500, 600).
In one embodiment, a first dielectric gate spacer 56 located within a first field effect transistor region (100 or 200) comprises an upper portion laterally surrounding the conductive gate connection structure (comprising the stack of the semiconductor gate cap structure 236 and the conductive gate cap structure 240), and four lower portions vertically extending between a horizontal plane including a top surface of frame portion 8F of the trench isolation structure 8 and a horizontal plane including top surfaces of the first active region and the second active region and contacting a respective lengthwise sidewall of one of the first gate electrode 14 and the second gate electrode 14 and contacting a top surface of a respective one of the first active region and the second active region.
Referring to
In one embodiment, configurations for increasing the breakdown voltage of field effect transistors may be employed in device regions in which high-voltage field effect transistors are formed such as the third field effect transistor regions (500, 600). In this case, the p-doped source/drain regions 65 may include inner p-doped source/drain regions 651 and outer p-doped source/drain regions 650 that are laterally spaced apart by an additional trench isolation structure 8, which may be disjoined from the trench isolation structure 8 in the first field effect transistor regions (100, 200). Further, the n-doped source/drain regions 66 may include inner n-doped source/drain regions 661 and outer n-doped source/drain regions 660 that are laterally spaced apart by another additional trench isolation structure 8. Optionally, a well contact source/drain region 65W may be employed to facilitate biasing of a doped well.
Referring to
The contact via structures (76A, 76G, 86A, 86G, 96A, 96G, 96R, 96C) comprise first source/drain region contact via structures 76A contacting source/drain regions (65, 66) within the first field effect transistor regions (100 or 200), first gate contact via structures 76G contacting top surfaces of conductive gate cap structures 240 within the first field effect transistor regions (100 or 200), second source/drain region contact via structures 86A contacting source/drain regions (65, 66) within the second field effect transistor regions (300 or 400), second gate contact via structures 86G contacting the second gate electrodes (25, 26), third source/drain region contact via structures 96A contacting source/drain regions (65, 66) within the third field effect transistor regions (500, 600), and third gate contact via structures 96G contacting top surfaces of conductive gate cap structures 240 within the third field effect transistor regions (500, 600). Further, the contact via structures (76A, 76G, 86A, 86G, 96A, 96G, 96R, 96C) can comprise first passive device contact via structures 96R that contact first passive devices such as resistors, and second passive device contact via structures 96C that contact second passive devices such as capacitors.
Generally, various field effect transistors having different gate dielectric thicknesses, different gate lengths (i.e., different lateral distances between a source region and a drain region), and different configurations can be formed in the various field effect transistor regions (100, 200, 300, 400, 500, 600). A dielectric gate spacer 56 may overlie a periphery region of a source/drain region (65, 66) of field effect transistors in the second field effect transistor regions (300 or 400), and contact sidewalls of a respective portion of the trench isolation structure 8.
The third exemplary structure can include a combination of a first field effect transistor and a second field effect transistor located in a first field effect transistor region (100 or 200). The first field effect transistor and the second field effect transistor comprise a first active region 51 and a second active region 52, respectively. The first active region and the second active region contact sidewalls of, and are laterally surrounded by, a trench isolation structure 8. A laterally-extending portion 8L of the trench isolation structure 8 is located between the first active region 51 and the second active region 52.
The third exemplary structure may comprise a third field effect transistor located in a second field effect transistor region (300 or 400). The third field effect transistor comprises: a third active region that is laterally surrounded by an additional portion of the trench isolation structure 8, a stack of a third gate dielectric 12 and a third gate electrode 14 having widthwise sidewalls contacting sidewalls of the additional portion of the trench isolation structure 8 and laterally extending along the first horizontal direction hd1, additional dielectric gate spacers 56 having a respective opening therethrough and contacting a respective subset of sidewalls of the additional portion of the trench isolation structure 8 and a respective lengthwise sidewall (which laterally extends along the second horizontal direction hd2) of the third gate electrode 14.
A portion of the top surface of third gate electrode 14 of the third field effect transistor can be contacted by the contact-level dielectric material layer 70. An additional conductive gate cap structure comprising a stack of a semiconductor gate cap structure 236 and a conductive gate cap structure 240 can contact another portion of the top surface of the third gate electrode 14. The additional conductive gate cap structure can comprise a same set of materials as the conductive gate connection structure in the first field effect transistor region (100 and/or 200). At least one gate contact structure (such as a first gate contact via structure 76G) can vertically extend through the contact-level dielectric layer 70 and can contact a top surface of a conductive gate connection structure (236, 240) in the first field effect transistor region (100 and/or 200), and at least one additional gate contact structure (such as a second gate contact via structure 86G) can vertically extend through the contact-level dielectric layer 70 and can contact a top surface of the additional conductive gate cap structure (236, 240).
The first gate electrode 14 and the second gate electrode 14 do not contact the contact-level dielectric layer 70, and are spaced from the contact-level dielectric layer 70 by a first dielectric gate spacer 56 and a conductive gate connection structure comprising the conductive gate cap structure 240). The third gate electrode 14 can have a same thickness as the first gate electrode 14 and the second gate electrode 14. A portion of a top surface of the third gate electrode 14 is in direct contact with the contact-level dielectric layer 70.
At least one gate contact structure (such as a first gate contact via structure 76G) extends through the contact-level dielectric layer 70 and contacts a top surface of the conductive gate connection structure comprising the conductive gate cap structure 240, and at least one additional gate contact structure (such as a second gate contact via structure 86G) extends through the contact-level dielectric layer 70 and contacts a portion of a top surface of the third gate electrode 14. An entirety of the top surface of the third gate electrode 14 is in contact with the at least one additional gate contact structure or the contact-level dielectric layer 70.
The third exemplary structure can comprise an additional field effect transistor such as a fourth field effect transistor formed in a third field effect transistor region (500 or 600). The additional field effect transistor comprises an additional active region having a pair of lengthwise sidewalls and a pair of widthwise sidewalls that contact sidewalls of, and are laterally surrounded by, an additional portion of the trench isolation structure 8. The additional field effect transistor comprises an additional gate structure (10, 14, 236, 240) overlies the additional active region. The additional gate structure (10, 14, 236, 240) can include an additional gate dielectric 10 having a greater thickness than the first gate dielectric 12, an additional gate electrode 14 (which may have a same thickness as the first gate electrode 14, an additional semiconductor gate cap structure 236 having a same thickness and a same material composition as the first semiconductor gate cap structures 236, and an additional conductive gate cap structure 240 having a same thickness and a same material composition as the first conductive gate cap structure 240. An entirety of a top surface of the additional gate electrode 14 is in contact with a bottom surface of the additional semiconductor gate cap structure 236.
In one embodiment, the third exemplary structure may comprise a passive device, which may be selected from a capacitor, a resistor, or any other passive device known in the art. The passive device comprises a layer stack including, from bottom to top, a first dielectric layer (such as another instance of a gate dielectric 12), a first semiconductor plate (such as a gate electrode 14), a second dielectric layer (such as a planar dielectric spacer plate 30), a second semiconductor plate (such as a planar semiconductor spacer plate 34), a third semiconductor plate (such as a semiconductor gate cap structure 236), and a metallic plate (such as a conductive gate cap structure 240). The first dielectric layer has a same material composition and a same thickness as the first gate dielectric 12. The first semiconductor plate may a same thickness as the first gate electrode 14. The second dielectric layer has a same material composition and a same thickness as the first planar dielectric spacer plate 30. The third semiconductor plate has the same material composition and the same thickness as the first semiconductor gate cap structure 236 in the first field effect transistor region (100 and/or 200). The metallic plate has a same material composition and a same thickness as the first conductive gate cap structure 240 in the first field effect transistor region (100 and/or 200).
The polysilicon gate electrode 14 and semiconductor gate cap structure 236 resistance is reduced by including respective silicide regions 25S and 240 on their upper surfaces. The semiconductor gate cap structure 236 extends along the second horizontal direction hd2 between two adjacent transistor structures and acts as the common gate contact via structure 76G tap area. Furthermore, since both the underlying gate electrodes 14 and the overlying semiconductor gate cap structures 236 comprise polysilicon with a silicide cap structure, it becomes easier to tune the characteristics of the fringeless transistors which include only the underlying gate electrode 14 and the fringed transistors which include both the underlying gate electrodes 14 and the overlying semiconductor gate cap structures 236.
The transistor structures may be formed closer to each other (e.g., be separated by relatively small distance d2 along the second horizontal direction) and take up relatively less chip space. Thus, the overall chip size may be reduced.
Referring to
In an illustrative example, the fifth exemplary structure may comprise a first doped well 5E and a second doped well 5F, each of which may independently have a doping of a first conductivity type or a doping of a second conductivity type. Each of the first doped well 5E and the second doped well 5F may be formed in an upper portion of a substrate semiconductor layer 4 in the same manner as the p-type wells (5A, 5B, 5C) or the n-type wells (6A, 6B, 6C, 6D) illustrated in
A silicon oxide pad dielectric layer and a hardmask material layer can be sequentially deposited over a top surface of the semiconductor substrate including the doped wells (5E, 5F). A photoresist layer (not shown) can be applied over the top surface of the hardmask material layer, and can be lithographically patterned to form a plurality of discrete photoresist material portions. In one embodiment, the plurality of discrete photoresist material portions may comprise photoresist material portion having a respective rectangular horizontal cross-sectional shape and located entirely within the area of a respective one of the doped wells (5E, 5F). In one embodiment, the rectangular horizontal cross-sectional shapes may have a pair of lengthwise edges that are parallel to a first horizontal direction hd1 and a pair of widthwise edges that are parallel to a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1.
A first anisotropic etch process can be performed to transfer the pattern of the photoresist material portions through the hardmask material layer and the silicon oxide pad dielectric layer. Vertical stacks of a silicon oxide pad dielectric 120 and a hardmask plate 21 can be formed underneath each patterned photoresist material portion. Each silicon oxide pad dielectric 120 is a patterned portion of the silicon oxide pad dielectric layer, and each hardmask plate 21 is a patterned portion of the hardmask material layer. In one embodiment, the silicon oxide pad dielectrics 120 may consist essentially of silicon oxide, and may have a thickness in a range from 3 nm to 30 nm, such as from 6 nm to 15 nm, although lesser and greater thicknesses may also be employed. In one embodiment, the hardmask plates 21 may consist essentially of silicon nitride, and may have a thickness in a range from 60 nm to 300 nm, such as from 100 nm to 200 nm, although lesser and greater thicknesses may also be employed. The photoresist layer may be removed, for example, by ashing, or alternatively, may be collaterally removed during a subsequent anisotropic etch process.
A second anisotropic etch process can be performed to transfer the pattern of the hardmask plates 21 into an upper portion of the semiconductor substrate. The upper portion of the semiconductor substrate that is not masked by the hardmask plates 21 is anisotropically etched by the second anisotropic etch process to form a shallow isolation trench 7. The shallow isolation trench 7 laterally surrounds active regions 51 of the semiconductor substrate, which are patterned upper portions of the semiconductor substrate that are laterally surrounded by the shallow isolation trench 7. The active regions 51 comprise a first active region 51A that underlies a first hardmask plate 21A of the hardmask plates 21 and comprises a portion of the first doped well 5E, and a second active region 51B that underlies a second hardmask plate 21B of the hardmask plates 21 and comprises a portion of the second doped well 5F.
In one embodiment, each active region 51 may have a respective rectangular top surface. In one embodiment, a top surface of the first active region 51A has a first active region length ARL1 along the first horizontal direction hd1 and has a first active region width ARW1 along the second horizontal direction hd2. In one embodiment, a top surface of the second active region 51B has a second active region length ARL2 along the first horizontal direction hd1 and has a second active region width ARW2 along the second horizontal direction hd2. The depth of the shallow isolation trench 7 may be in a range from 200 nm to 800 nm, such as from 300 nm to 600 nm, although lesser and greater depths may also be employed. The thickness of each active region 51 can be the same as the depth of the shallow isolation trench 7.
Referring to
The remaining portions of the at least one dielectric fill material filling the trenches 7 constitute a trench isolation structure 8, which may be a continuous structure contacting the semiconductor material of the semiconductor substrate with dielectric surfaces and providing electrical isolation between active regions 51 of adjacent semiconductor devices to be subsequently formed. The trench isolation structures 8 may comprise shallow trench isolation structures located in the shallow isolation trenches 7. Each device active region 51 may comprise a patterned portion of a respective doped well (5E, 5F) that is laterally surrounded by a respective portion of the trench isolation structure 8. Each of the hardmask plates 21 may comprise a respective horizontal bottom surface located within a horizontal plane and a respective horizontal top surface located within another horizontal plane.
Referring to
According to an aspect of the present disclosure, at least one region of the area between the sidewalls of the first hardmask plate 21A and the periphery of the opening in the patterned photoresist layer 27 that surrounds the first hardmask plate 21A may be wide enough to accommodate at least one gate contact via structure. In other words, a gap region 32 between the sidewalls of the first hardmask plate 21A and the periphery of the opening in the patterned photoresist layer 27 can continuously extend around the first hardmask plate 21A, and includes an area in which at least one gate contact via structure can be subsequently formed without areal overlap with the first hardmask plate 21A or the patterned photoresist layer 27.
An etch process that etches the material of the trench isolation structure 8 selective to the material of the hardmask plates 21 can be performed to vertically recess the gap region 32 of the trench isolation structure 8 that laterally surrounds the first active region 51A (i.e., the portion of the first doped well 5E that underlies the first hardmask plate 21A) while masking the second hardmask plate 21B, the second active region 5F and a field region of the trench isolation structure 8 that laterally surrounds the gap region 32. The etch process may comprise an anisotropic etch process (such as a reactive ion etch process). The field region of the trench isolation structure 8 can include the portion of the portion of the trench isolation structure 8 that is covered by the photoresist layer 27. A recessed horizontal surface of the trench isolation structure 8 is formed in a portion of the trench isolation structure 8 located in the gap region 32. The recessed horizontal surface is vertically recessed relative to a topmost surface of the trench isolation structure 8 located in the field region and contained with the second horizontal plane.
Generally, the gap region 32 of the trench isolation structure 8 is vertically recessed by performing the etch process, which etches unmasked portions of the trench isolation structure 8 while the hardmask plates 21 are present over the semiconductor substrate. The recessed horizontal surface is formed above the horizontal plane including the bottom surfaces of the hardmask plates 21, and below the horizontal plane including the top surfaces of the hardmask plates 21. In one embodiment, the recess horizontal surface may be located within a horizontal plane. The patterned photoresist layer 27 can be subsequently removed, for example, by ashing.
Referring to
An optional second etch process can be performed to remove the silicon oxide pad dielectrics 120 selective to the materials of the semiconductor substrate. For example, the second etch process may comprise an anisotropic etch process (such as a reaction ion etch process) or an isotropic etch process (such as a wet etch process). The silicon oxide pad dielectrics 120, if present, can be removed, and the top surfaces of the active regions can be physically exposed around openings through the trench isolation structure 8.
A gate dielectric layer 20L can be formed on the physically exposed surfaces of the doped wells (5E, 5F), for example, by thermal oxidation of the surface portions of the doped wells (5E, 5F) and/or by conformal deposition of a gate dielectric material layer. The conformally deposited gate dielectric material layer, if employed, may comprise silicon oxide and/or a dielectric metal oxide material (such as aluminum oxide, hafnium oxide, tantalum oxide, lanthanum oxide, yttrium oxide, etc.). The thickness of the gate dielectric layer 20L may be in a range from 2 nm to 50 nm, such as from 6 nm to 30 nm, although lesser and greater thicknesses may also be employed.
Alternatively, second etch process may be omitted and the pad dielectrics 120 may be retained. In this case, the pad dielectrics 120 function as the gate dielectric layer 20L.
The top surface of the gate dielectric layer 20L may be located within a first horizontal plane HP1. The topmost surfaces of the trench isolation structure 8 may be located within a second horizontal plane HP2. The recessed horizontal surface of the trench isolation structure 8 in the gap region 32 may be located within a third horizontal plane HP3. The vertical distance between the first horizontal plane HP1 and the second horizontal plane HP2 may be in a range from 60 nm to 300 nm, although lesser and greater vertical distances may also be employed. In one embodiment, the vertical distance between the third horizontal plane HP3 and the first horizontal plane HP1 may be in a range from 10% to 90%, such as from 20% to 80% and/or from 30% to 70%. of the vertical distance between the second horizontal plane HP2 and the first horizontal plane HP1.
Referring to
A planarization process, such as a chemical mechanical polishing (CMP) process, can be performed to remove portions of the at least one gate electrode material from above the second horizontal plane HP2, i.e., the horizontal plane including the topmost surfaces of the trench isolation structure 8. A thermal anneal may be performed as needed to convert any amorphous semiconductor material in the at least one gate electrode material into a heavily doped polycrystalline semiconductor material that is electrically conductive. Remaining portions of the at least one gate electrode material constitute gate electrode material portions 24′, which comprise a first gate electrode material portion 24E′ and a second gate electrode material portion 24F′. The first gate electrode material portion 24E′ can overlie the first active region 51A (i.e., a portion of the first doped well 5E), and the second gate electrode material portion 24F′ can overlie the second active region 51B (i.e., a portion of the second doped well 5F). The first gate electrode material portion 24E′ can be formed over and on the gate dielectric layer 20L and the recessed horizontal surface of the trench isolation structure 8 located within the third horizontal plane HP3.
Referring to
An anisotropic etch process can be performed to etch portions of the gate electrode material portions 24′ and the gate dielectric layers 20L that are not masked by the patterned photoresist layer 57. The anisotropic etch process may include a first etch step that etches the material(s) of the gate electrode material portions 24′ selective to the materials of the trench isolation structure 8 and the gate dielectric layers 20L, and a second etch step that etches the material of the gate dielectric layers 20L selective to the material of the semiconductor substrate (which is the material of the doped wells (5E, 5F)). Patterned portions of the gate electrode material portion 24′ constitute gate electrodes 24, which comprise first gate electrodes 24E that overlie the first action region 51A in the first doped well 5E, and second gate electrodes 24F that overlie the second active region 51B in the second doped well 5F. Patterned portions of the gate dielectric layers 20L constitute gate dielectrics 20, which comprise first gate dielectrics 20E and second gate dielectrics 20F.
Generally, at least one first gate electrode 24E can be formed by patterning the first gate electrode material portion 24E′, and at least one second gate electrode 24F can be formed by patterning the second gate electrode material portion 24F′. The at least one first gate electrode 24E comprises a respective lower gate electrode portion contacting a top surface of a respective first gate dielectric 20E and a pair of sidewall segments of the trench isolation structure 8, and comprises a respective upper gate electrode portion contacting top surfaces respective first segments of the recessed horizontal surface of the trench isolation structure 8 and having sidewalls exposed in the gap region 32. Each lower gate electrode portion is located entirely between the first horizontal plane HP1 and the third horizontal plane HP3, and each upper gate electrode portion is located entirely between the second horizontal plane HP2 and the third horizontal plane HP3.
In one embodiment, a top surface of the first active region 51A has an active region length ARL along a first horizontal direction hd1 and has an active region width ARW along a second horizontal direction hd2. In one embodiment, the lower gate electrode portion of each first gate electrode 24E has a lower electrode width LEW along the second horizontal direction hd2 that is the same as the active region width ARW. The upper gate electrode portion has an upper electrode width UEW along the second horizontal direction hd2 that is greater than the active region width ARW. The patterned photoresist layer 57 can be subsequently removed, for example, by ashing.
Referring to
Electrical dopants can be implanted into exposed surface portions of the active regions (51A, 51B) to form source/drain extension regions 64. Each source/drain extension region 64 can form a p-n junction with a respective underlying doped well (5E, 5F). The source/drain extension regions 64 may include electrical dopants of a respective conductivity type at an atomic concentration in a range from 1.0×1017/cm3 to 1.0×1020/cm3, although lower and higher atomic concentrations may also be employed. The depth of each source/drain extension region 64 may be in a range from 5 nm to 100 nm, such as from 10 nm to 50 nm, although lesser and greater depths may also be employed.
Referring to
An anisotropic etch process can be performed to remove horizontally-extending portions of the at least one dielectric spacer material layer. Generally, at least one dielectric spacer material layer can be conformally formed over and around the first gate electrodes 24E, the second gate electrodes 24F, and over the recessed horizontal surface and the topmost surface of the trench isolation structure 8. Remaining portions of the at least one dielectric spacer material layer comprise dielectric gate spacers (55, 56) laterally surrounding, and contacting, a respective one of the gate electrodes 24, and a dielectric isolation spacer (55′, 56′) contacting sidewalls of the trench isolation structure 8 that are located between the second horizontal plane HP2 and the third horizontal plane HP3.
In one embodiment, each dielectric gate spacer (55, 56) may be a composite dielectric gate spacer including at least two different components (which may have different dielectric compositions), and the dielectric isolation spacer (55′, 56′) may be a composite dielectric isolation spacer including at least two different components. In one embodiment, each dielectric gate spacer (55, 56) may comprise a main dielectric gate spacer 56 (which is a patterned portion of the main dielectric spacer layer) and an optional liner dielectric gate spacer 55 (which is a patterned portion of the dielectric liner layer 55L). In one embodiment, the dielectric isolation spacer (55′, 56′) may comprise a main dielectric isolation spacer 56′ (which is a patterned portion of the main dielectric spacer layer) and an optional liner dielectric isolation spacer 55′ (which is a patterned portion of the dielectric liner layer 55L).
The dielectric gate spacers (55, 56) comprise at least one first dielectric gate spacer (55, 56) laterally surrounding a respective first gate electrode 24E and contacting respective second segments of the recessed horizontal surface of the trench isolation structure 8. The dielectric isolation spacer (55′, 56′) contacts sidewalls of the trench isolation structure 8 in the gap region 32 that connect the recessed horizontal surface of the trench isolation structure 8 to the topmost surface of the trench isolation structure 8.
In one embodiment, the dielectric isolation spacer (55′, 56′) comprises a same set of materials as the dielectric gate spacers (55, 56). In one embodiment, a lateral dimension between an inner periphery of a bottom surface of the dielectric isolation spacer (55′, 56′) and an outer periphery of the bottom surface of the dielectric isolation spacer (55′, 56′) may be the same as a lateral dimension between an inner periphery of a bottom surface of a dielectric gate spacer (55, 56) and an outer periphery of the bottom surface of the dielectric gate spacer (55, 56).
In one embodiment, the dielectric isolation spacer (55′, 56′) is not in direct contact with the semiconductor substrate, and the entirety of the dielectric isolation spacer (55′, 56′) is located above a horizontal plane including the recessed horizontal surface of the trench isolation structure 8 (i.e., above the third horizontal plane HP3). In one embodiment shown in
In one embodiment, the dielectric gate spacer (55, 56) is laterally spaced from sidewalls of the trench isolation structure 8 that connect the recessed horizontal surface of the trench isolation structure 8 to the topmost surface of the trench isolation structure 8.
Electrical dopants can be implanted into surface portions of the doped regions 64 and the source/drain extension regions 64 to form deep source/drain regions 66. Each deep source/drain region 66 can form a p-n junction with a respective active region (51A, 51B) in a respective underlying doped well (5E, 5F). Implanted portions of the source/drain extension regions 64 can be incorporated into a respective one of the deep source/drain regions 66, and can have a doping of the same conductivity type as the respective one of the deep source/drain regions 66. The deep source/drain regions 66 may include electrical dopants of a respective conductivity type at an atomic concentration in a range from 5.0×1018/cm3 to 2.0×1021/cm3, although lower and higher atomic concentrations may also be employed. The depth of each deep source/drain region 66 may be in a range from 30 nm to 600 nm, such as from 60 nm to 300 nm, although lesser and greater depths may also be employed. Each continuous combination of a source/drain extension region 64 and a deep source/drain region 66 constitutes a source/drain region (64, 66), which may function as a source region or as a drain region. A p-n junction may be formed between each source/drain region (64, 66) and a respective active region (51A, 51B) in the underlying doped well (5E, 5F).
A first field effect transistor 902 and a second field effect transistor 904 can be formed. The first field effect transistor 902 may comprise peripheral transistor that is not a sense amplifier transistor. The first field effect transistor 902 comprises a first active region 51A including a portion of the semiconductor substrate located within a first opening through the trench isolation structure 8, and a first gate structure (20E, 24E) that includes a first gate dielectric 20E and a first gate electrode 24E. The first gate electrode 24E comprises a lower gate electrode portion contacting a top surface of the first gate dielectric 20E and a pair of sidewall segments of the trench isolation structure 8, and comprises an upper gate electrode portion contacting first segments of the recessed horizontal surface of the trench isolation structure 8. The lower gate electrode portion can be located below the third horizontal plane HP3 including the recessed horizontal surface of the trench isolation structure 8, and the upper gate electrode portion can be located above the third horizontal plane HP3. A first dielectric gate spacer (55, 56) laterally surrounds the first gate electrode 24E and contacts second segments of the recessed horizontal surface of the trench isolation structure 8. The first field effect transistor 902 includes the above described fringe region.
The second field effect 904 comprises a fringeless sense amplifier transistor. The second field effect transistor 904 includes a second active region 51B including another portion of the semiconductor substrate located within a second opening through the trench isolation structure 8, and comprises a second gate structure (20F, 24F) including a second gate dielectric 20F and a second gate electrode 24F. The second gate electrode 24F comprises a pair of sidewalls vertically extending straight from a respective edge of the top surface of the second gate electrode 24F to a respective edge of a top surface of a second gate dielectric 20F that underlies the second gate electrode 24F. In one embodiment, an entirety of the pair of sidewalls of the second gate electrode 24F is in contact with a respective sidewall of the trench isolation structure 8. In one embodiment, the second gate electrode 24F comprises first sidewalls in contact with sidewall segments of the trench isolation structure 8 and second sidewalls in contact with a pair of second dielectric gate spacers (55, 156) that includes a respective main dielectric gate spacer 156 and an optional liner dielectric gate spacer 55. Each second dielectric gate spacer (55, 156) contacts the second gate electrode 24F and sidewalls of the trench isolation structure 8.
Referring to
In one embodiment, a first gate metal-semiconductor alloy region 58 can have a bottom surface that contacts a top surface of the first gate electrode 24E within a horizontal plane located below a horizontal plane including the topmost surface of the trench isolation structure 8 (i.e., below the second horizontal plane HP2), and can have a top surface located above the horizontal plane including the topmost surface of the trench isolation structure 8. In one embodiment, the second gate electrode 24F comprises a top surface located within a same horizontal plane as a top surface of the first gate electrode (20E, 24E).
Referring to
A contact-level dielectric layer 70 can be deposited over the at least one dielectric liner (172, 174). The contact-level dielectric layer 70 includes a dielectric material such as undoped silicate glass, a doped silicate glass, or organosilicate glass. Optionally, a planarization process may be performed to planarize the top surface of the contact-level dielectric layer 70.
Referring to
In one embodiment, each of the first gate contact via structures 176G can be located entirely outside an area of a top surface of the first active region MA in a plan view, and can be located entirely within the gap region 32, i.e., the region laterally bounded by the inner periphery of the recessed horizontal surface of the trench isolation structure 8 and the outer periphery of the recessed horizontal surface of the trench isolation structure 8. In other words, the first gate contact via structure 176G may be located entirely inside an area of the recessed horizontal surface of the trench isolation structure 8 in the plan view. Each of the second gate contact via structures 186G can be located entirely inside an area of a top surface of the second active region MB in a plan view.
Referring the fifth embodiment, a semiconductor structure comprising a first field effect transistor is provided. The semiconductor structure comprises a trench isolation structure 8 located in an upper portion of a semiconductor substrate and comprising a first opening therethrough. The trench isolation structure 8 comprises a gap region having a recessed horizontal surface, laterally surrounding the first opening, and laterally surrounded by a field region of the trench isolation structure 8 including a topmost surface of the trench isolation structure 8. The first field effect transistor comprises a first active region including a portion of a semiconductor substrate located within the first opening through the trench isolation structure 8. The first field effect transistor comprises a first gate structure (24E, 20E) that includes a first gate dielectric 20E and a first gate electrode 24E. The first gate electrode 24E comprises a lower gate electrode portion contacting a top surface of the first gate dielectric 20E and a pair of sidewall segments of the trench isolation structure 8, and comprises an upper gate electrode portion contacting first segments of the recessed horizontal surface of the trench isolation structure 8. A first dielectric gate spacer (55, 56) laterally surrounds the first gate electrode 24E and contacts second segments of the recessed horizontal surface of the trench isolation structure 8.
In the embodiments of the present disclosure, the high voltage non-sense amplifier peripheral transistor 902 (which is located outside the sense amplifier circuit) may be formed with a gate fringe area to improve the stability of its electrical characteristics, since its gate electrode 24E length in the first horizontal direction hd1 is narrow and the contact process has a large impact on its gate dielectric layer. In contrast, the low or very low voltage sense amplifier transistor 904 (which operates at a lower voltage than transistor 902) may be formed with a larger gate electrode 24F length and without the gate fringe area. The gate contact 186G for the transistor 904 is located over the active region 51B. Thus, the device area is reduced. Furthermore, both transistors 902 and 904 can be made in parallel using the same processing steps, which reduces the number of processing steps and the cost of the process.
Referring to
Referring to
Referring to
In one embodiment, each sidewall of the gate semiconductor material portions 241 may have a respective taper angle relative to a vertical direction. In one embodiment, sidewalls of the gate semiconductor material portions 241 that laterally extend along a first horizontal direction hd1 may have a first taper angle with respective to vertical planes that are parallel to the first horizontal direction hd1 and perpendicular to a second horizontal direction hd2. Sidewalls of the gate semiconductor material portions 241 that laterally extend along the second horizontal direction hd2 may have a second taper angle with respective to vertical planes that are parallel to the second horizontal direction hd2 and perpendicular to the first horizontal direction hd1. The first taper angle and the second taper angle may be in a range from 0.1 degree to 15 degrees, such as from 0.3 degrees to 10 degrees, and/or from 0.6 degrees to 6 degrees, although lesser and greater taper angles may also be employed. Generally, each of the gate semiconductor material portions 241 may have a first variable lateral extent along the first horizontal direction hd1 that decreases with a vertical distance from a horizontal plane including a topmost surface of the semiconductor substrate 2, and may have a second variable lateral extent along the second horizontal direction hd2 that decreases with the vertical distance from the horizontal plane including the topmost surface of the semiconductor substrate 2.
Referring to
Referring to
In summary, shallow trench isolation structures 8 may be formed around the patterned stacks {20L, 241, 21} in an upper portion of the semiconductor substrate 2. In one embodiment, a first patterned stack (20L, 241, 21) comprising a first hardmask plate 21 and a first gate semiconductor material portion 241 can be formed in one device region, such as a first transistor region (e.g., a first n-type field effect transistor region 200), and a second patterned stack (20L, 241, 21) comprising a second hardmask plate 21 and a second gate semiconductor material portion 241 can be formed in another device region such as a third n-type field effect transistor region 600.
Referring to
Referring to
Referring to
An etch process can be performed to remove unmasked portions of the dielectric capping layer 18L. A dielectric capping plate 18P is formed over at least one device region, such as the first p-type field effect transistor region 100, the first transistor region (e.g., a first n-type field effect transistor region 200), the second p-type field effect transistor region 300, and the second n-type field effect transistor region 400. A patterned portion of the dielectric capping layer 18L that remains in the second passive device region 800 may comprise a dielectric material layer 18. Generally, a portion of the dielectric capping layer 18L may be removed from above the top surface of at least one gate semiconductor material portion 241 (such as the second gate semiconductor material portion 241 located in the third n-type field effect transistor region 600). The photoresist layer 19 can be subsequently removed, for example, by ashing.
Referring to
Referring to
An anisotropic etch process can be performed to etch portions of the second semiconductor material layer 242L that are not covered by the second photoresist layer 27. A remaining portion of the second semiconductor material layer 242L underlying the second photoresist layer 27 comprises a second semiconductor material plate 242P located in at least one device region, such as the third p-type field effect transistor region 500 and the third n-type field effect transistor region 600. Another remaining portion of the second semiconductor material layer 242L underlying the second photoresist layer 27 is located another device region, such as in the second passive device region 800, may comprise a second semiconductor plate 247. Remaining portions of the second semiconductor material layer 242L in recessed areas that are not covered by the second photoresist layer 27 may comprise semiconductor spacers 248. A top surface of a first semiconductor material plate 246 may be exposed in a device region, such as the first passive device region 700. The top surface of the dielectric capping plate 18P may be exposed in some other device regions, such as the first p-type field effect transistor region 100, the first transistor region (e.g., a first n-type field effect transistor region 200), the second p-type field effect transistor region 300, and the second n-type field effect transistor region 400. The second photoresist layer 27 can be removed, for example, by ashing.
Referring to
Referring to
Referring to
In summary, the gate pattern is transferred through the second semiconductor material layer 242L, the dielectric material layer 18, and the first semiconductor material layer 241L. The semiconductor capping plate 242P and the first semiconductor material layer 241L are patterned into various semiconductor gate electrode portions (251, 252), which include first semiconductor gate electrode portions 251 and second semiconductor gate electrode portions 252. In one embodiment, each first semiconductor gate electrode portion 251 contacts sidewall surface segments of a respective trench isolation structure 8. Each lower semiconductor gate electrode portion 251W is a subset of the first semiconductor gate electrode portions 251, and as such, may have a same material composition and a same thickness as other first semiconductor gate electrode portions 251. In one embodiment, each upper semiconductor gate electrode portion 252 comprises a bottom surface contacting a respective lower semiconductor gate electrode portion 251W and top surface segments of a respective second shallow trench isolation structure 8.
In one embodiment, a first gate electrode 2511 of a first field effect transistor (which may comprise, for example, a field effect transistor to be formed in the first transistor region (e.g., a first n-type field effect transistor region 200)) may consist of only the first semiconductor gate electrode portion 251. In one embodiment, a maximum lateral dimension of the first gate electrode 2511 along a first gate electrode direction (which is the lateral extension direction of the first gate electrode 2511 such as the second horizontal direction hd2) equals a lateral dimension of a top surface of the first active region (e.g., 5A) along the first gate electrode direction (such as the second horizontal direction hd2). Generally, a gate electrode direction of a field effect transistor can be perpendicular to the channel direction of the field effect transistor.
In one embodiment, a maximum lateral dimension of the lower semiconductor gate electrode portion 251W along a second gate electrode direction (which is the lateral extension direction of a second gate electrode 2522 such as the second horizontal direction hd2) equals a lateral dimension of a top surface of the second active region (e.g., 5C) along the second gate electrode direction (such as the second horizontal direction hd2). In one embodiment, a lateral dimension of upper semiconductor gate electrode portion 252 along the second gate electrode direction (such as the second horizontal direction hd2) is greater than the third lateral dimension. In one embodiment, the upper semiconductor gate electrode portion 252 and the lower semiconductor gate electrode portion 251W have a same width along the second channel direction (such as the first horizontal direction hd1).
First field effect transistors including a respective first gate electrode 2511 can be formed in transistor region 200. In one embodiment, each sidewall of a first semiconductor gate electrode portion 251 that contacts sidewall surface segments of a trench isolation structure 8 has a respective taper angle relative to a vertical plane that is perpendicular to a first gate electrode direction (such as the second horizontal direction hd2) of a respective first field effect transistor. The first gate electrode 2511 has a variable lateral dimension along the first gate electrode direction (such as the second horizontal direction hd2) that decreases with a vertical distance from a horizontal plane including a top surface of a respective first active region (e.g., 5A). Thus, each first gate electrode 2511 may have a vertical cross-sectional shape of a trapezoid as illustrated in
Second field effect transistors including a respective second gate electrode 2522 can also be formed in another transistor region 600. Each lower semiconductor gate electrode portion 251W has a variable lateral dimension along the second gate electrode direction (such as the second horizontal direction hd2) that decreases with a vertical distance from a horizontal plane including a top surface of the second active region (e.g., 5C). In one embodiment, each upper semiconductor gate electrode portion 252 has a uniform lateral dimension along the second gate electrode direction (such as the second horizontal direction hd2) that is invariant with the vertical distance from the horizontal plane including the top surface of the second active region (e.g., 5C).
Referring to
Referring to
Subsequently, an anisotropic etch process can be performed to etch unmasked portions of the various gate dielectric layers 20L. First gate dielectrics 20 can be formed, which overlie first active regions (such as a portion of a first p-doped well 5A or a portion of a first n-doped well 6A that is laterally surrounded by a respective first trench isolation structure 8), for example, in the first p-type field effect transistor region 100 and in the first transistor region (e.g., a first n-type field effect transistor region 200). A lateral dimension of a first gate dielectric 20 along a first channel direction (such as the first horizontal direction hd1) equals a width of a respective overlying first gate electrode 2511 along the first channel direction.
Second gate dielectrics 20 can be formed, which overlie second active region (such as a portion of a third p-doped well 5C or a portion of a third n-doped well 6C), for example, in the third p-type field effect transistor region 500 and in the third n-type field effect transistor region 600. Each second gate dielectric 20 underlies a respective lower semiconductor gate electrode portion 251W. A lateral dimension of the second gate dielectric 20 along a second channel direction (such as the first horizontal direction hd1) equals a width of the second gate electrode 2522 along the second channel direction. The second gate dielectrics may be thicker than the first gate dielectrics.
Referring to
Referring to
Top surfaces of the upper semiconductor gate electrode portion 252 and the first semiconductor gate electrode portions 251 and top surfaces of the source/drain extension regions (63, 64) can be physically exposed after the anisotropic etch process. Remaining portions of the dielectric gate spacer layer 56L comprise dielectric gate spacers 56. In this case, a pair of gate spacers 56 can be formed on each gate structure including a respective gate dielectric 20 and a respective gate electrode (2511 or 2522). In one embodiment, the two first dielectric gate spacers 56 are not in direct contact with each other, and have a maximum height that is less than a sum of a thickness of the first gate dielectric 20 and a thickness of the first gate electrode 2511.
In one embodiment, first dielectric gate spacers 56 can be formed on sidewalls of a first gate electrode 2511, and second dielectric gate spacers 56 can be formed on sidewalls of the second gate electrode 2522. In one embodiment, second dielectric gate spacers 56 contact the lower semiconductor gate electrode portion 251W (which is a remaining portion of a second gate semiconductor material portion 241) and do not contact the upper semiconductor gate electrode portion 252 (which is a remaining portion of the second semiconductor material layer 242L), as illustrated in
Referring to
A first field effect transistor can be provided in transistor region 200 by forming a first source region (such as one of the n-type source/drain regions (64, 66)) and a first drain region (such as one of the n-type source/drain regions (64, 66)) in portions of the semiconductor substrate 2 adjacent to the first gate electrode 2511. A second field effect transistor can be provided in transistor region 600 by forming a second source region (such as one of the n-type source/drain regions (64, 66)) and a second drain region (such as one of the n-type source/drain regions (64, 66)) in portions of the semiconductor substrate 2 adjacent to the second gate electrode 2522. The first field effect transistor in transistor region 200 comprises a first active region (e.g., (5A, 64, 66)) and a first gate electrode 2511 which comprises a first semiconductor gate electrode portion 251. The upper portion of the well 5A located between the source and drain regions (64, 66) functions as the channel of the first field effect transistor. A first trench isolation structure 8 laterally surrounds the first active region (e.g., (5A, 64, 66)). The second field effect transistor comprises a second active region (e.g., (5C, 64, 66)) and a second gate electrode 2522 that comprises a stack of a lower semiconductor gate electrode portion 251W and an upper semiconductor gate electrode portion 252. The upper portion of the well 5C located between the source and drain regions (64, 66) functions as the channel of the second field effect transistor. A second trench isolation structure 8 laterally surrounds the second active region (e.g., (5C, 64, 66)).
In one embodiment, the first active region (e.g., (5A, 64, 66)) comprises a first source region (such as one of the n-type source/drain regions (64, 66)) and a first drain region (such as one of the n-type source/drain regions (64, 66)) that are laterally spaced from each other by the first channel 5A along a first channel direction (such as the first horizontal direction hd1). In one embodiment, the first gate electrode 2511 laterally extends along a first gate electrode direction (such as the second horizontal direction hd2) that is perpendicular to the first channel direction (such as the first horizontal direction hd1). In one embodiment, the second active region (e.g., (5C, 64, 66)) comprises a second source region (such as one of the n-type source/drain regions (64, 66)) and a second drain region (such as one of the n-type source/drain regions (64, 66)) that are laterally spaced from each other by the second channel 5C along a second channel direction (such as the first horizontal direction hd1). In one embodiment, the second gate electrode 2522 laterally extends along a second gate electrode direction (such as the second horizontal direction hd2) that is perpendicular to the second channel direction (such as the first horizontal direction hd1).
Referring to
In the sixth embodiment of the disclosure, the fringeless low voltage transistors (100, 200) and very low voltage transistors (300, 400) include gate electrode 2511 comprising a single semiconductor layer portion 251. The single semiconductor layer portion 251 gate electrode 2511 has a lower resistance because it lacks an interface between lower and upper gate electrode portions. A low gate resistance is advantageous in low and very low voltage transistors. In contrast, the high voltage transistors (500, 600) include a gate electrode 2522 comprising two semiconductor layer portions (251W, 252). Such gate electrodes prevent ion implant penetration and are suitable for forming metal silicide contacts 58, such as NiPtSi type contacts. Furthermore, parasitic transistor threshold voltage decrease and off current degradation at the trench isolation structures 8 is decreased or avoided.
Referring collectively to
In one embodiment, the first gate electrode 2511 does not include any additional semiconductor gate electrode portion which contacts the first semiconductor gate electrode portion 251, and the first gate electrode 2511 lacks an interface between two semiconductor gate portions. In one embodiment, the first active region (e.g., (5A, 64, 66)) comprises a first source region (such as one of the n-type source/drain regions (64, 66)) and a first drain region (such as one of the n-type source/drain regions (64, 66)) that are laterally spaced from each other by a first channel 5A along a first channel direction (such as the first horizontal direction hd1); the first gate electrode 2511 laterally extends along a first gate electrode direction (such as the second horizontal direction hd2) that is perpendicular to the first channel direction (such as the first horizontal direction hd1); the second active region (e.g., (5C, 64, 66)) comprises a second source region (such as one of the n-type source/drain regions (64, 66)) and a second drain region (such as one of the n-type source/drain regions (64, 66)) that are laterally spaced from each other by a second channel 5C along a second channel direction (such as the first horizontal direction hd1); and the second gate electrode 2522 laterally extends along a second gate electrode direction (such as the second horizontal direction hd2) that is perpendicular to the second channel direction (such as the first horizontal direction hd1).
In one embodiment, a maximum lateral dimension of the first gate electrode 2511 along the first gate electrode direction (such as the second horizontal direction hd2) equals a lateral dimension of a top surface of the first active region (e.g., (5A, 64, 66)) along the first gate electrode direction (such as the second horizontal direction hd2). In one embodiment, a maximum lateral dimension of the lower semiconductor gate electrode portion 251W along the second gate electrode direction (such as the second horizontal direction hd2) equals a lateral dimension of a top surface of the second active region (e.g., (5C, 64, 66)) along the second gate electrode direction (such as the second horizontal direction hd2). In one embodiment, a lateral dimension of upper semiconductor gate electrode portion along the second gate electrode direction (such as the second horizontal direction hd2) is greater than the third lateral dimension.
In one embodiment, the upper semiconductor gate electrode portion and the lower semiconductor gate electrode portion 251W have a same width along the second channel direction (such as the first horizontal direction hd1). In one embodiment, the first field effect transistor 200 comprises a first gate dielectric 20 overlying the first active region (e.g., (5A, 64, 66)) and underlying the first gate electrode 2511, and two first dielectric gate spacers 56 contacting a respective sidewall of the first gate electrode 2511; and a lateral dimension of the first gate dielectric 20 along the first channel direction (such as the first horizontal direction hd1) equals a width of the first gate electrode 2511 along the first channel direction (such as the first horizontal direction hd1).
In one embodiment, the second field effect transistor 600 comprises a second gate dielectric 20 overlying the second active region (e.g., (5C, 64, 66)) and underlying the lower semiconductor gate electrode portion 251W, and two second dielectric gate spacers 56 contacting a respective sidewall of the lower semiconductor gate electrode portion 251W; the second gate dielectric 20 is thicker than the first gate dielectric 20; and a lateral dimension of the second gate dielectric 20 along the second channel direction (such as the first horizontal direction hd1) equals a width of the second gate electrode 2522 along the second channel direction (such as the first horizontal direction hd1). In one embodiment, the two first dielectric gate spacers 56 are not in direct contact with each other, and have a maximum height that is less than a sum of a thickness of the first gate dielectric 20 and a thickness of the first gate electrode 2511.
In one embodiment, each sidewall of the first semiconductor gate electrode portion 251 that contacts the sidewall surface segments of the first trench isolation structure 8 has a respective taper angle relative to a vertical plane that is perpendicular to the first gate electrode direction (such as the second horizontal direction hd2). In one embodiment, the first gate electrode 2511 has a variable lateral dimension along the first gate electrode direction (such as the second horizontal direction hd2) that decreases with a vertical distance from a horizontal plane including a top surface of the first active region (e.g., (5A, 64, 66)). In one embodiment, the lower semiconductor gate electrode portion 251W has a variable lateral dimension along the second gate electrode direction (such as the second horizontal direction hd2) that decreases with a vertical distance from a horizontal plane including a top surface of the second active region (e.g., (5C, 64, 66)). In one embodiment, the upper semiconductor gate electrode portion 252 has a uniform lateral dimension along the second gate electrode direction (such as the second horizontal direction hd2) that is invariant with the vertical distance from the horizontal plane including the top surface of the second active region (e.g., (5C, 64, 66)).
In one embodiment, semiconductor structure comprises: a first gate metal-semiconductor alloy region 58 in contact with a top surface segment of the first semiconductor gate electrode portion 251; and a second gate metal-semiconductor alloy region 58 in contact with a top surface segment of the upper semiconductor gate electrode portion 252, wherein the lower semiconductor gate electrode portion 251W is not in direct contact with any metal-semiconductor alloy material.
Referring to
Referring to
A second anisotropic etch process can be performed to transfer the pattern of the hardmask plates 21 through the semiconductor gate electrode material layer 24L, the gate dielectric layer 20L, and an upper portion of the semiconductor substrate 2, such as unmasked portions of the first doped well 5E and the second doped well 5F. Patterned portions of the semiconductor gate electrode material layer 24L comprise gate semiconductor material portions 24′, which comprises a first gate semiconductor material portion 24E′ underlying the first hardmask plate 21A and a second gate semiconductor material portion 24F′ underlying the second hardmask plate 21B. Patterned portions of the gate dielectric layer 20L may have the same area as a respective overlying gate semiconductor material portion 24′. Shallow trenches 7 are formed in volumes from which the material of the semiconductor substrate 2 is removed, such as the volumes from which the materials of first doped well 5E and the second doped well 5F are removed. Active regions 51 laterally surrounded by a respective shallow trench 7 can be formed. The active regions 51 may comprise a first active region 51E that is formed underneath the first hardmask plate 21A and a second active region 51F that is formed underneath the second hardmask plate 21B.
A first patterned stack (20L, 24E′, 21A) including a first gate dielectric layer 20L, a first gate semiconductor material portion 24E′, and a first hardmask plate 21A can be formed over a first portion of a semiconductor substrate 2. A second patterned stack (20L, 24F′, 21B) including a second gate dielectric layer 20L, a second gate semiconductor material portion 24F′, and a second hardmask plate 21B can be formed over a second portion of the semiconductor substrate 2.
Referring to
The remaining portions of the at least one dielectric fill material filling the trenches 7 constitute trench isolation structures 8. The trench isolation structures 8 may form a continuous structure contacting the semiconductor material of the semiconductor substrate 2 with dielectric surfaces and providing electrical isolation between active regions 51 of adjacent semiconductor devices to be subsequently formed. The trench isolation structures 8 may comprise shallow trench isolation structures located in the shallow isolation trenches 7. Each device active region 51 may comprise a patterned portion of a respective doped well (5E, 5F) that is laterally surrounded by a respective trench isolation structure 8. Each of the hardmask plates 21 may comprise a respective horizontal bottom surface located within a horizontal plane and a respective horizontal top surface located within another horizontal plane. In one embodiment, the trench isolation structures 8 may have a top surface that is formed within a horizontal plane including the top surfaces of the hardmask plates 21. The trench isolation structures 8 may comprise a first trench isolation structure 8 that is formed around the first patterned stack (20L, 24E′, 21A) and into the first portion of the semiconductor substrate 2, and a second trench isolation structure 8 that is formed around the second patterned stack (20L, 24F′, 21B) and into the second portion of the semiconductor substrate 2.
Referring to
According to an aspect of the present disclosure, at least one region of the area between the sidewalls of the first hardmask plate 21A and the periphery of the opening in the patterned photoresist layer 27 that surrounds the first hardmask plate 21A may be wide enough to accommodate at least one gate contact via structure. In other words, a gap region 32 between the sidewalls of the first hardmask plate 21A and the periphery of the opening in the patterned photoresist layer 27 can continuously extend around the first hardmask plate 21A, and includes an area in which at least one gate contact via structure can be subsequently formed without areal overlap with the first hardmask plate 21A or the patterned photoresist layer 27. The gap region 32 is also referred to as a peripheral recess region.
An etch process that etches the material of the trench isolation structure 8 selective to the material of the hardmask plates 21 can be performed to vertically recess the gap region 32 of the trench isolation structure 8 that laterally surrounds the first active region 51A (i.e., the portion of the first doped well 5E that underlies the first hardmask plate 21A) while masking the second hardmask plate 21B, the second active region 5F and a field region of the trench isolation structure 8 that laterally surrounds the gap region 32 are not recessed. The etch process may comprise an anisotropic etch process (such as a reactive ion etch process). The field region of the trench isolation structure 8 can include the portion of the trench isolation structure 8 that is covered by the photoresist layer 27. A recessed horizontal surface 8H of the trench isolation structure 8 is formed in a portion of the trench isolation structure 8 located in the gap region 32. The recessed horizontal surface 8H is vertically recessed relative to a topmost surface of the trench isolation structure 8 located in the field region and contained with the second horizontal plane.
In summary, the gap region 32 of the trench isolation structure 8 is vertically recessed by performing the etch process, which etches unmasked portions of the trench isolation structure 8 while the hardmask plates 21 are present over the semiconductor substrate. The recessed horizontal surface 8H is formed above the horizontal plane including the bottom surfaces of the hardmask plates 21, and below the horizontal plane including the top surfaces of the hardmask plates 21. In one embodiment, the recess horizontal surface 8H may be located within a horizontal plane that is located above the horizontal plane including the bottom surfaces of the hardmask plates 21. The patterned photoresist layer 27 can be subsequently removed, for example, by ashing. Generally, the gap region 32 (i.e., the peripheral recess region) may be formed around the first patterned stack (20L, 24E′, 21A) in a portion of the first trench isolation structure 8 that is proximal to the first hardmask plate 21A by vertically recessing a portion of the first trench isolation structure 8.
Referring to
A stepped cavity 21S can be formed by removing the first hardmask plate 21A. The stepped cavity comprises a volume from which the first hardmask plate 21A is removed and a volume of the peripheral recess region, i.e., the volume of the gap region 32. A recess cavity 21R can be formed in the volume from which the second hardmask plate 21B is removed. Interfaces between the gate dielectric layers 20L and the gate semiconductor material portions 24′ can be located within a first horizontal plane HP1. Topmost surfaces of the trench isolation structures 8 can be located within a second horizontal plane HP2. Recessed horizontal surfaces 8H of the trench isolation structures 8 can be located within a third horizontal plane HP3 that overlies the top surfaces of the gate semiconductor material portions 24′.
Referring to
Referring to
Referring to
Referring to
Each contiguous combination of a semiconductor gate electrode portion 24 and a metallic gate electrode (35, 36) constitutes a gate electrode (24, 35, 36). Generally, a stepped metallic plate 360S and a first semiconductor gate semiconductor material portion 24E′ that overlie a first active region 51E can be patterned into a first gate electrode (24, 35, 36), and a planar metallic plate 360P and a second semiconductor gate semiconductor material portion 24F′ that overlie a second active region 51F can be patterned into a second gate electrode (24, 35, 36).
In one embodiment, the first gate electrode (24, 35, 36) laterally extends along a first gate electrode direction (such as the second horizontal direction hd2) that is perpendicular to a first channel direction (such as the first horizontal direction hd1). A maximum lateral extent of the first metallic gate electrode portion (35, 36) along the first gate electrode direction (such as the second horizontal direction hd2) is greater than a maximum lateral extent of the first semiconductor gate electrode portion 24 along the first gate electrode direction (such as the second horizontal direction hd2) as illustrated, for example, in
In one embodiment, the second gate electrode (24, 35, 36) laterally extends along a second gate electrode direction (such as the second horizontal direction hd2) that is perpendicular to the second channel direction (such as the first horizontal direction hd1). A maximum lateral extent of the second metallic gate electrode portion (35, 36) along the second gate electrode direction (such as the second horizontal direction hd2) is the same as a maximum lateral extent of the second semiconductor gate electrode portion 24 along the second gate electrode direction (such as the second horizontal direction hd2) as illustrated in
In one embodiment, the first metallic gate electrode portion (35, 36) comprises a center segment having a first thickness t1 and peripheral segments having a second thickness t2 that is less than the first thickness t1. In one embodiment, an entirety of the center segment of the first metallic gate electrode portion (35, 36) has an areal overlap with the first semiconductor gate electrode portion 24 in a plan view (such as a top-down view of
In one embodiment, top surfaces of the peripheral segments and a top surface of the center segment are located entirely within a horizontal plane such as the second horizontal plane HP2. In one embodiment, the semiconductor structure comprises: a first trench isolation structure 8 laterally surrounding the first active region 51E; and a second trench isolation structure 8 laterally surrounding the second active region 51F. The first metallic gate electrode portion (35, 36) comprises peripheral segments that overlie first trench isolation structure 8. In one embodiment, a center segment of the first metallic gate electrode portion (35, 36) having an areal overlap with the first active region 51E has a first thickness t1; and peripheral segments of the first metallic gate electrode portion (35, 36) having an areal overlap with the first trench isolation structure 8 have a second thickness t2 that is less than the first thickness t1. In one embodiment, the peripheral segments of the first metallic gate electrode portion (35, 36) do not have any areal overlap with the first semiconductor gate electrode portion 24 in a plan view.
In one embodiment, the first semiconductor gate electrode portion 24 has an areal overlap with the first active region 51E and does not have any areal overlap with the first trench isolation structure 8 in a plan view. In one embodiment, the first trench isolation structure 8 comprises: a top surface 8T that is located within a same horizontal plane as a top surface of the first metallic gate electrode portion (35, 36); a first widthwise sidewall 8S that connects an edge of the top surface 8T to an edge of the recessed horizontal surface 8H; the recessed horizontal surface 8H that is adjoined to a bottom edge of the first widthwise sidewall 8S and contacting a first bottom surface of the first metallic gate electrode portion (35, 36); and a second widthwise sidewall 8W that contacts a lower widthwise sidewall of the first metallic gate electrode portion (35, 36). The patterned photoresist layer 57 may be subsequently removed, for example, by ashing.
Referring to
Referring to
In one embodiment, a first dielectric gate spacer 56 around the first gate electrode (24, 35, 36) and on sidewalls of the first trench isolation structure 8. The first dielectric gate spacer 56 comprises at least three openings therethrough, and the first gate electrode (24, 35, 36) can be located in a first opening of the at least three openings. In one embodiment, a first source region (such as one of the source/drain regions (64, 66)) of the first field effect transistor 902 underlies a second opening of the at least three openings; and a first drain region (such as one of the source/drain regions (64, 66)) of the first field effect transistor 902 underlies a third opening of the at least three openings. The first dielectric gate spacer 56 can contact lengthwise sidewalls of the first semiconductor gate electrode portion 24, lengthwise sidewalls of the first metallic gate electrode portion (35, 36), and sidewalls of the first trench isolation structure 8.
In one embodiment, the first shallow trench isolation structure 8 comprises a top surface 8T and a recessed horizontal surface 8H that is recessed relative to the top surface 8T; the recessed horizontal surface 8H laterally surrounds the first active region 51E; and an outer dielectric spacer 56′ having a same material composition as the first dielectric gate spacer 56 overlies the recessed horizontal surface 8H and the second widthwise sidewall 8W of the first trench isolation structure 8.
In one embodiment, the first active region 51E comprises a first source region (such as one of the source/drain regions (64, 66)) and a first drain region (such as one of the source/drain regions (64, 66)) that are laterally spaced from each other by a first channel region comprising an upper portion of the doped well 5E along a first channel direction (such as the first horizontal direction hd1). The second active region 51F comprises a second source region (such as one of the source/drain regions (64, 66)) and a second drain region (such as one of the source/drain regions (64, 66)) that are laterally spaced from each other by a second channel region comprising an upper portion of the doped well 5F along a second channel direction (such as the first horizontal direction hd1).
The first field effect transistor 902 and a second field effect transistor 904 are formed on the substrate 2. The first field effect transistor 902 can be provided by forming a first source region (such as one of the source/drain regions (64, 66)) and a first drain region (such as one of the source/drain regions (64, 66)) in the first portion of the semiconductor substrate 2 (e.g., in doped well 5E) adjacent to the first gate electrode (24, 35, 36). The second field effect transistor 904 can be provided by forming a second source region (such as one of the source/drain regions (64, 66)) and a second drain region (such as one of the source/drain regions (64, 66)) in the second portion of the semiconductor substrate 2 (e.g., in doped well 5F) adjacent to the second gate electrode (24, 35, 36).
The first field effect transistor 902 may comprise a peripheral transistor that is not a sense amplifier transistor. The first field effect transistor 902 comprises a first active region 51F including a portion of the semiconductor substrate 2 located within a first opening through the trench isolation structures 8, and a first gate structure (20, 24, 35, 36) that includes a first gate dielectric 20 and a first gate electrode (24, 35, 36). A first dielectric gate spacer 56 laterally surrounds the first gate electrode (24, 35, 36) and contacts second segments of the recessed horizontal surface 8H of the trench isolation structure 8.
The second field effect 904 comprises a fringeless sense amplifier transistor. The second field effect transistor 904 includes a second active region 51F including another portion of the semiconductor substrate 2 located within a second opening through the trench isolation structures 8, and comprises a second gate structure (20, 24, 35, 36) including a second gate dielectric 20 and a second gate electrode (24, 35, 36). The second gate electrode 24F comprises a pair of sidewalls vertically extending straight from a respective edge of the top surface of the second gate electrode (24, 35, 36) to a respective edge of a top surface of a second gate dielectric 20 that underlies the second gate electrode (24, 35, 36). In one embodiment, an entirety of the pair of sidewalls of the second gate electrode (24, 35, 36) is in contact with a respective sidewall of the trench isolation structure 8. In one embodiment, shown in
Referring to
Referring to
Referring to
In the seventh embodiment, a fringeless sense amplifier transistor 904 can be formed during the same process steps as a peripheral transistor 902 which includes a gate electrode extending into the fringe region. A metal gate electrode portion 36, such as tungsten gate electrode portion, may be formed by a damascene type process in which the metal layer is deposited into recesses formed by selective removal of the hardmask plates 21 followed a CMP step to planarize the top of the metal gate electrode portion 36 with a top surface of the trench isolation structures 8. Thus, a simplified method of simultaneously forming both fringeless and fringe type transistors during the same steps is provided.
Referring collectively to
In one embodiment, the second active region 51F comprises a second source region (such as one of the source/drain regions (64, 66)) and a second drain region (such as one of the source/drain regions (64, 66)) that are laterally spaced from each other by a second channel 5F along a second channel direction (such as the first horizontal direction hd1); the second gate electrode (24, 35, 36) laterally extends along a second gate electrode direction (such as the second horizontal direction hd2) that is perpendicular to the second channel direction (such as the first horizontal direction hd1); and a maximum lateral extent of the second metallic gate electrode portion (35, 36) along the second gate electrode direction (such as the second horizontal direction hd2) is the same as a maximum lateral extent of the second semiconductor gate electrode portion 24 along the second gate electrode direction (such as the second horizontal direction hd2).
In one embodiment, the first metallic gate electrode portion (35, 36) comprises a center segment having a first thickness t1 and peripheral segments having a second thickness t2 that is less than the first thickness t1. In one embodiment, an entirety of the center segment of the first metallic gate electrode portion (35, 36) has an areal overlap with the first semiconductor gate electrode portion 24 in a plan view. In one embodiment, an entirety of the peripheral segments of the first metallic gate electrode portion (35, 36) does not have any areal overlap with the first semiconductor gate electrode portion 24 in a plan view.
In one embodiment, top surfaces of the peripheral segments and a top surface of the center segment are located entirely within a horizontal plane. In one embodiment, the semiconductor structure comprises: a first trench isolation structure 8 laterally surrounding the first active region 51E; and a second trench isolation structure 8 laterally surrounding the second active region 51F. The first metallic gate electrode portion (35, 36) comprises peripheral segments that overlie first trench isolation structure 8. In one embodiment, a center segment of the first metallic gate electrode portion (35, 36) having an areal overlap with the first active region 51E has a first thickness t1; and peripheral segments of the first metallic gate electrode portion (35, 36) having an areal overlap with the first trench isolation structure 8 have a second thickness t2 that is less than the first thickness t1. In one embodiment, the peripheral segments of the first metallic gate electrode portion (35, 36) do not have any areal overlap with the first semiconductor gate electrode portion 24 in a plan view.
In one embodiment, the first semiconductor gate electrode portion 24 has an areal overlap with the first active region 51E and does not have any areal overlap with the first trench isolation structure 8 in a plan view. In one embodiment, the first trench isolation structure 8 comprises: a top surface 8T that is located within a same horizontal plane as a top surface of the first metallic gate electrode portion (35, 36); a recessed horizontal surface 8H that contacts bottom surfaces of the peripheral segments of the first metallic gate electrode portion (35, 36); and a first widthwise sidewall 8S that connects an edge of the top surface 8T to an edge of the recessed horizontal surface 8H. In one embodiment, the first trench isolation structure 8 further comprises a second widthwise sidewall 8W that contacts a lower widthwise sidewall of the first metallic gate electrode portion (35, 36).
In one embodiment, the semiconductor structure comprises a first dielectric gate spacer 56 contacting lengthwise sidewalls of the first semiconductor gate electrode portion 24, lengthwise sidewalls of the first metallic gate electrode portion 35, 36, and sidewalls of the first trench isolation structure 8. In one embodiment, the first dielectric gate spacer 56 comprises at least three openings therethrough, wherein: the first gate electrode (24, 35, 36) is located in a first opening of the at least three openings; a first source region (such as one of the source/drain regions (64, 66)) of the first field effect transistor underlies a second opening of the at least three openings; and a first drain region (such as one of the source/drain regions (64, 66)) of the first field effect transistor underlies a third opening of the at least three openings. In one embodiment, the first shallow trench isolation structure 8 comprises a top surface and a recessed horizontal surface that is recessed relative to the top surface; the recessed horizontal surface laterally surrounds the first active region 51E; and an outer dielectric spacer 56′ having a same material composition as the first dielectric gate spacer 56 overlies the recessed horizontal surface and sidewalls of the first trench isolation structure 8 that connect the top surface and the recessed horizontal surface.
Referring to
A gate dielectric layer 20L, a first semiconductor material layer 241L, and a hardmask layer 21L can be formed over the semiconductor substrate 2. The first semiconductor material layer 241L comprises a first semiconductor material, such as polysilicon. The first semiconductor material is also referred to as a first semiconductor gate electrode material. The first semiconductor material layer 241L may have a thickness in a range from 50 nm to 200 nm, although lesser and greater thicknesses may also be employed. The hardmask layer 21L comprises a hardmask material, such as silicon nitride, and may have a thickness in a range from 50 nm to 200 nm, although lesser and greater thicknesses may also be employed.
A patterned photoresist layer 107 can be formed over the hardmask layer 21L. The patterned photoresist layer 107 comprises patterned photoresist material portions. Each of the patterned photoresist material portions may have an area of a respective active region to be subsequently patterned in the semiconductor substrate 2. In one embodiment, a subset of the patterned photoresist material portions in the transistor array region 1200 may be arranged as a periodic one-dimensional array or as a periodic two-dimensional array, such as a rectangular array. The patterned photoresist material portions in the transistor array region 1200 may be elongated along a second horizontal direction hd2, which can be channel directions for the field effect transistors to be formed therein.
Referring to
A second anisotropic etch process can be performed to transfer the pattern of the hardmask plates 21 through the a first semiconductor material layer 241L, the gate dielectric layer 20L, and an upper portion of the semiconductor substrate 2, such as unmasked portions of substrate portion 4, the first doped well 5A and the second doped well 5F. Patterned portions of the a first semiconductor material layer 241L comprise lower gate material portions 241. One of the lower gate material portions 241 that is formed in the second passive device region 800 is herein referred to as a lower semiconductor plate 241P. A patterned portion of the gate dielectric layer 20L that underlies the lower semiconductor plate 241P is herein referred to as a first dielectric plate 20′.
Shallow trenches 7 are formed in volumes from which the material of the semiconductor substrate 2 is removed, such as the volumes from which the materials of the portion 4, the first doped well 5A and the second doped well 5F are removed. Active regions laterally surrounded by a respective shallow trench 7 can be formed. The active regions may comprise a first active region that is formed in the first transistor region (e.g., a first n-type field effect transistor region 200), a second active region that is formed in the transistor array region 1200.
Patterned stacks (20L, 241, 21) can be formed. Each of the patterned stacks (20L, 241, 21) may include a gate dielectric layer 20L, a lower gate material portion 241, and a hardmask plate 21. The lower gate material portions 241 may comprise a first-transistor lower gate material portion 241 that is formed in the first transistor region (e.g., a first n-type field effect transistor region 200), and second-transistor lower gate material portions 241 that are formed in the transistor array region 1200. A first patterned stack (20L, 241, 21) can be formed in the first transistor region (e.g., a first n-type field effect transistor region 200), and a second patterned stack (20L, 241, 21) can be formed in the transistor array region 1200. A patterned stack that is formed in the second passive device region 800 is herein referred to as a device-region patterned stack (20′, 241P, 21), which includes a first dielectric plate 20′, a lower semiconductor plate 241P, and a hardmask plate 21.
Referring to
Referring to
A second semiconductor material layer 242L including a second semiconductor material can be deposited over the node dielectric layer 38L. The second semiconductor material layer 242L comprises a semiconductor material such as polysilicon, and may have a thickness in a range from 50 nm to 200 nm, although lesser and greater thicknesses may also be employed.
Referring to
Referring to
A dielectric capping layer 48L can be deposited over the third semiconductor material layer 243L. The dielectric capping layer 48L comprises a dielectric material such as silicon oxide. The thickness of the dielectric capping layer 48L may be in a range from 50 nm to 200 nm, although lesser and greater thicknesses may also be employed.
Referring to
Referring to
Referring to
Referring to
A passive semiconductor device, such as a capacitor, is formed in the second passive device region 800. The passive semiconductor device comprises a layer stack including a first dielectric plate 20′, a lower semiconductor plate 241P comprising a first portion of the first semiconductor material and having a first thickness, a second dielectric plate 38, a middle semiconductor plate 242P comprising a first portion of the second semiconductor material, and an upper semiconductor plate 243P comprising a first portion of the third semiconductor material.
Referring to
Referring to
Referring to
A portion of the third semiconductor material layer 243L located in the first transistor region (e.g., a first n-type field effect transistor region 200) can be patterned into a first-transistor upper gate material portion 253A. The first-transistor lower gate material portion 241 (i.e., a lower gate material portion 241 located in the first n-type field effect transistor region 200) can be patterned into a first-transistor lower gate electrode portion 251A. A first gate electrode (251A, 253A) including a stack of a first-transistor lower gate electrode portion 251A and a first-transistor upper gate material portion 253A can be formed in the first transistor region (e.g., a first n-type field effect transistor region 200). The first lower semiconductor gate electrode 251A includes a patterned portion of the first semiconductor material. The first upper semiconductor gate electrode portion 253A includes a patterned portion of the third semiconductor material.
Each second-transistor gate material portion 241 (i.e., a lower gate material portion 242 located in the transistor array region 1200) can be patterned into a second gate electrode which consists of a second semiconductor gate electrode portion 251B, and into a third gate electrode which comprises a stack of a third-transistor lower gate electrode portion 251F and a third-transistor upper gate material portion 253F.
The eighth exemplary structure comprises a semiconductor device comprising a layer stack including a first dielectric plate 20′, a lower semiconductor plate 241P comprising a first portion of a first semiconductor material and having a first thickness, a second dielectric plate 38, a middle semiconductor plate 242P comprising a first portion of a second semiconductor material, and an upper semiconductor plate 243P comprising a first portion of a third semiconductor material in the second passive device region 800.
The eighth exemplary structure further comprises a first field effect transistor comprising a first gate electrode (251A, 253A) that comprises a second portion of the first semiconductor material and having the first thickness, and a second portion of the third semiconductor material that contacts a top surface of the second portion of the first semiconductor material in the first transistor region 200.
In addition, the eighth exemplary structure also comprises a second field effect transistor in the transistor array region 1200 which comprise an active region which may comprise an upper portion of a second doped well 5F in the semiconductor substrate 2 and a second gate electrode which includes a single second semiconductor gate electrode portion 251B including an additional patterned portion of the first semiconductor material. In one embodiment, the second gate electrode 251B comprises and/or consists of a third portion of the first semiconductor material. In one embodiment, a maximum lateral extent of the second gate electrode 251B along a gate length direction (such as the first horizontal direction hd1) that is perpendicular to a channel direction (such as the second horizontal direction hd2) is the same as a maximum lateral extent of a top surface of the active region (which may comprise a portion of a second doped well 5F) along the gate length direction, i.e., the same as the width of the active region as illustrated in
Further, the eighth exemplary structure also comprises a third field effect transistor in the transistor array region 1200 comprising a third gate electrode (251F, 253F) that comprises a fourth portion of the first semiconductor material and a third portion of the third semiconductor material that contacts a top surface of the fourth portion of the first semiconductor material. In one embodiment, a maximum lateral extent of the third gate electrode (251F, 253F) along the second horizontal direction hd2 is greater than the width of the active region (which may comprise a portion of a second doped well 5F). Thus, the third field effect transistor is not a fringeless transistor and includes a gate electrode including two semiconductor layers. At least one additional third field effect transistor may be located adjacent to the third field effect transistor. The third gate electrode (251F, 253F) extends over an active region (which may comprise a portion of a second doped well 5F) of the at least one additional third field effect transistor and constitutes a gate electrode of the additional third field effect transistor. In other words, the third gate electrode (251F, 253F) may be a common gate electrode for a plurality of third field effect transistors as illustrated in
Referring to
Referring to
Electrical dopants can be implanted into portions of the semiconductor substrate 2 that are not masked by gate structures (i.e., gate dielectrics 20 and gate electrodes) and dielectric gate spacers 56. Deep source/drain regions 66 can be formed in implanted portions of the semiconductor substrate 2 in the field effect transistor regions (200, 1200). A deep doped semiconductor region 65B can be formed in the second passive device region 800.
Each active region in the field effect transistor regions (200, 1200) comprises a respective active region including a respective pair of a source region (64, 66) and a drain region (64, 66) separated by a channel region (e.g., upper portion of a respective doped well 5). A first field effect transistor can be formed in the first transistor region (e.g., a first n-type field effect transistor region 200). Second field effect transistors and third field effect transistors can be formed in the transistor array region 1200.
A pair of a second field effect transistor and a third field effect transistor in the transistor array region 1200 may share an active region 5F. The pair of the second field effect transistor and the third field effect transistor may comprise a shared source/drain region (64, 66), and may be laterally surrounded by a same trench isolation structure 8. In one embodiment, all source/drain regions (64, 66) of the second field effect transistor and the third field effect transistor including the shared source/drain region (64, 66) can be located within an active region (which may comprise a portion of a second doped well 5F) having a width along a first horizontal direction hd1 having a length along a second horizontal direction hd2 along which the third gate electrode (251F, 253F) is laterally spaced from the second gate electrode 251B.
In one embodiment, the first field effect transistor in region 200 comprises a first dielectric gate spacer 56 that laterally surrounds the first gate electrode (251A, 253A). In one embodiment, the first dielectric gate spacer 56 comprises at least three openings therethrough; the first gate electrode (251A, 253A) is located in a first opening of the at least three openings; a first source region (64, 66) of the first field effect transistor underlies a second opening of the at least three openings; and a first drain region (64, 66) of the first field effect transistor underlies a third opening of the at least three openings.
In one embodiment, the second field effect transistor in region 1200 comprises two second dielectric gate spacers 56 that are not in contact with each other, and are laterally spaced by the second gate electrode 251B from each other, as shown in
In one embodiment, the first field effect transistor in region 200 comprises a first active region (which may comprise a portion of the first doped well 5A) that is laterally surrounded by a first trench isolation structure 8; and the first dielectric gate spacer 56 comprises a first portion that overlies and contacts a top surface of the first trench isolation structure 8, as shown in
In one embodiment, a source region (64, 66) and a drain region (64, 66) of the third field effect transistor in region 1200 are laterally spaced from each other by a channel (e.g., upper portion of the second doped well 5F) along a channel direction of the third field effect transistor; and a maximum lateral dimension of the third gate electrode (251F, 253F) along a horizontal direction that is perpendicular to the channel direction of the third field effect transistor is the same as a width of the second active region (which may comprise a portion of a second doped well 5F) along the horizontal direction that is perpendicular to the channel direction of the third field effect transistor.
Referring to
Subsequently, at least one dielectric material layer such as a contact-level dielectric layer 70 can be formed over the metal-semiconductor alloy regions (58, 68) and the trench isolation structures 8. Various contact via cavities can be formed through the contact-level dielectric layer 70, and various contact via structures 88 can be formed on a respective one of the metal-semiconductor alloy regions (58, 68).
Referring collectively to
In one embodiment, the semiconductor structure further comprises a semiconductor device, such as a capacitor located in region 4, comprising a layer stack including a first dielectric plate 20′, a lower semiconductor plate 241P comprising a first portion of a first semiconductor material and having a first thickness, a second dielectric plate 38, a middle semiconductor plate 242P comprising a first portion of a second semiconductor material, and an upper semiconductor plate 243P comprising a first portion of a third semiconductor material. In one embodiment, the first field effect transistor 200T comprises a first gate electrode (58, 251A, 253A) that comprises a second portion of the first semiconductor material and having the first thickness, and a second portion of the third semiconductor material that contacts a top surface of the second portion of the first semiconductor material.
In one embodiment, the semiconductor device comprises a first metal-semiconductor alloy region 59 contacting a top surface of the first portion of the third semiconductor material; and the first field effect transistor 200T comprises a first gate metal-semiconductor alloy region 58 contacting a top surface of the second portion of the third semiconductor material.
In one embodiment, the second gate electrode (58, 251B) comprises a third portion of the first semiconductor material, and a second gate metal-semiconductor alloy region 58 contacting a top surface of the third portion of the first semiconductor material. In one embodiment, the third gate electrode (58, 251F, 253F) comprises a fourth portion of the first semiconductor material and a third portion of the third semiconductor material that contacts a top surface of the fourth portion of the first semiconductor material.
In one embodiment, the second field effect transistor 1200S and the third field effect transistor 1200T are laterally surrounded by a common trench isolation structure 8. In one embodiment, the first field effect transistor 200T is located within a first active region (which may comprise a portion of a first doped well 5A) which is separated from the second active region 5F by the common trench isolation structure 8.
In one embodiment, the semiconductor structure comprises an additional third field effect transistor 1200U that is located adjacent to the third field effect transistor 1200T, in the second active region 5F, wherein the third gate electrode (58, 251F, 253F) comprises a continuous common gate electrode of the third field effect transistor 1200T and the additional third field effect transistor 1200U.
In one embodiment, the third gate electrode further comprises a third gate metal-semiconductor alloy region 58 contacting a top surface of the third portion of the third semiconductor material. In one embodiment, the first field effect transistor 200T further comprises a first dielectric gate spacer 56 that laterally surrounds the first gate electrode (251A, 253A); and the second field effect transistor 1200S comprises two second dielectric gate spacers 56 that are not in contact with each other, and are laterally spaced by the second gate electrode 251B from each other. In one embodiment, the first dielectric gate spacer 56 comprises at least three openings therethrough; the first gate electrode (251A, 253A) is located in a first opening of the at least three openings; a first source region of the first field effect transistor underlies a second opening of the at least three openings; and a first drain region of the first field effect transistor underlies a third opening of the at least three openings.
In one embodiment, one of the two second dielectric gate spacers 56 comprises exactly one opening therethrough; and a source/drain region (64, 66) of the second field effect transistor underlies the one opening of the two second dielectric gate spacers 56. In one embodiment, the first field effect transistor comprises a first active region (which may comprise a portion of a second doped well 5F) that is laterally surrounded by a first trench isolation structure 8; and the first dielectric gate spacer 56 comprises a first portion that overlies, and contacts a top surface of, the first trench isolation structure 8 and a second portion that overlies the first active region (which may comprise a portion of a second doped well 5F) and contacts sidewalls of the first trench isolation structure 8.
In one embodiment, the second active region (which may comprise a portion of a second doped well 5F) is laterally surrounded by a second trench isolation structure 8; and one of the second dielectric gate spacers 56 does not have any areal overlap with the second trench isolation structure 8 in a plan view.
Referring to
Generally, the ninth exemplary structure illustrated in
Referring to
The first trench isolation structure 8 can be formed around a first-transistor lower gate material portion 241 in the first transistor region (e.g., a first n-type field effect transistor region 200), and a second trench isolation structure 8 can be formed around the second-transistor lower gate material portion 241 in the transistor array region 1200. The first trench isolation structure 8 laterally surrounds a first active region 5A of the semiconductor substrate 2. The second trench isolation structure 8 laterally surrounds a second active region 5F of the semiconductor substrate 8.
Referring to
Optionally, the corners of the protruding upper portions of the trench isolation structures 8 may be rounded after removal of the hardmask plates 21. The trench isolation structures 8 may be subjected to a timed wet etch which rounds upper corners of the trench isolation structures 8 without entirely removing the protruding upper portions of the trench isolation structures 8 which extend above the top surfaces of the lower gate material portions 241. If the trench isolation structures 8 comprise silicon oxide, then the wet etch may comprise a dilute hydrofluoric acid wet etch.
Referring to
Referring to
In one embodiment, the portion of the second semiconductor material layer 242L overlying a first-transistor lower gate material portion 241 located in a transistor region (such as the first n-type field effect transistor region 200) is not thinned during the processing steps of
Referring to
Referring to
Patterned portions of the second semiconductor material layer 242L comprise a first upper semiconductor gate electrode portion 252A that is formed in a first transistor region (such as the first n-type field effect transistor region 200), second upper semiconductor gate electrode portions 252B that are formed in the transistor array region 1200, and third upper semiconductor gate electrode portions 252F that are formed in the transistor array region 1200. Patterned portions of the first-transistor lower gate material portion 241 comprise a first lower semiconductor gate electrode portion 251A that is formed in a first transistor region (such as the first n-type field effect transistor region 200), second lower semiconductor gate electrode portions 251B that are formed in the transistor array region 1200, and third lower semiconductor gate electrode portions 251F that are formed in the transistor array region 1200.
A first gate electrode (251A, 252A) is formed in the first transistor region 200. The first gate electrode (251A, 152A) comprises the first upper semiconductor gate electrode portion 252A (which is a patterned portion of the second portion of the second semiconductor material layer 242L) and the first lower semiconductor gate electrode portion 251A (which is a patterned portion of the first-transistor lower gate material portion 241). Second gate electrodes (251B, 252B) can be formed in the transistor array region 1200. Each second gate electrode (251B, 252B) comprises a second upper semiconductor gate electrode portion 252B (which is a patterned portion of the thinned portion of the second semiconductor material layer 242L) and a second lower semiconductor gate electrode portion 251B (which is a patterned portion of the second-transistor lower gate material portion 241). Third gate electrodes (251F, 252F) can be formed in the transistor array region 1200. Each third gate electrode (251F, 252F) comprises a third upper semiconductor gate electrode portion 252F (which is a patterned portion of the thinned portion of the third semiconductor material layer 242L) and a third lower semiconductor gate electrode portion 251F (which is a patterned portion of the third-transistor lower gate material portion 241).
The first gate electrode (251A, 252A) extends laterally along a first gate electrode length direction (such as the first horizontal direction hd1) and comprises a first lower semiconductor gate electrode portion 251A and a first upper semiconductor gate electrode portion 252A. In one embodiment, the first gate electrode (251A, 252A) laterally extends along the first gate electrode length direction (such as the first horizontal direction hd1) by a lateral distance that is greater than a lateral dimension of a top surface of the first active region 5A.
Each second gate electrode (251B, 252B) overlies a first portion of a second active region 5F. Each second gate electrode (251B, 252B) extends laterally along a second gate electrode length direction (such as the second horizontal direction hd2) normal to the first gate length direction hd1 and comprises a second lower semiconductor gate electrode portion 251B and a second upper semiconductor gate electrode portion 252B. In one embodiment, a maximum lateral dimension of the second gate electrode (251B, 252B) along a second gate electrode length direction (such as the second horizontal direction hd2) is the same as a lateral dimension of a top surface of the second active region 5F along the second gate electrode length direction (such as the second horizontal direction hd2).
In one embodiment, each second gate electrode (251B, 252B) has a variable lateral extent along the second gate electrode length direction (such as the second horizontal direction hd2) extent that decreases with a vertical distance from the top surface of the second active region. In one embodiment, the second active region is laterally surrounded by a trench isolation structure 8 comprising a dielectric fill material; and each second gate electrode (251B, 252B) has tapered widthwise sidewalls that are perpendicular to the second gate electrode length direction (such as the second horizontal direction hd2), and are tilted along the second gate electrode direction (such as the second horizontal direction hd2), and are in contact with the trench isolation structure 8. The tilt angle of the tapered widthwise sidewalls may be in a range from 0.1 degree to 10 degrees, such as from 0.3 degrees to 5 degrees, and/or from 0.6 degrees to 3 degrees.
In one embodiment, for each second gate electrode (251B, 252B), an entirety of two widthwise sidewalls of the second lower semiconductor gate electrode portion 251B is in contact with the trench isolation structure 8; a lower portion of each of two widthwise sidewalls of the second upper semiconductor gate electrode portion 252B is in contact with the trench isolation structure 8; and an upper portion of each of the two widthwise sidewalls of the second upper semiconductor gate electrode portion 252B overlies a top surface of the trench isolation structure 8.
In one embodiment, the first lower semiconductor gate electrode portion 251A has a maximum lateral extent along the first gate electrode length direction (such as the first horizontal direction hd1) that is the same as a lateral extent of a top surface of the first active region 5A along the first gate electrode length direction (such as the first horizontal direction hd1). In one embodiment, the first upper semiconductor gate electrode portion 252A comprises a lower portion having a lateral extent along the first gate electrode length direction (such as the first horizontal direction hd1) that is not greater than the lateral extent of the top surface of the first active region 5A along the first gate electrode length direction (such as the first horizontal direction hd1), and further comprises an upper portion having a lateral extent along the first gate electrode length direction that is greater than the lateral extent of the top surface of the first active region 5A along the first gate electrode length direction, as shown in
In one embodiment, the semiconductor structure comprises: a first trench isolation structure 8 laterally surrounding the first active region 5A; and a second trench isolation structure 8 laterally surrounding the second active region 5F. The first gate electrode (251A, 252A) contacts a top surface of the first trench isolation structure 8; and the second gate electrode (251B, 252B) does not contact a top surface of the second trench isolation structure 8. In one embodiment, the first upper semiconductor gate electrode portion 252A includes a first uniform thickness region and two variable thickness regions having an areal overlap with the first active region 5A in a plan view, as shown in
Third gate electrodes (251F, 252F) are formed in the transistor array region 1200. Each third gate electrode (251F, 252F) overlies a second portion of a respective second active region. Each third gate electrode (251F, 252F) comprises a third upper semiconductor gate electrode portion 252F having a variable thickness that is greater than the uniform thickness in the uniform thickness regions of the first upper semiconductor gate electrode portion 252A.
In one embodiment, a maximum lateral extent of the second gate electrode (251B, 252B) along the second gate electrode length direction (such as the second horizontal direction hd2) is the same as a lateral dimension of a top surface of the second active region 5F along the second gate electrode length direction (such as the second horizontal direction hd2); and the third gate electrode (251F, 252F) extends laterally along the second gate electrode length direction (such as the second horizontal direction hd2) by a lateral distance that is greater than the lateral dimension of the top surface of the second active region 5F along the second gate electrode length direction (such as the second horizontal direction hd2).
Generally, an entirety of the first lower semiconductor gate electrode portion 251A (i.e., the patterned portion of the first-transistor lower gate material portion 241) may be formed below a horizontal plane including a top surface of the first trench isolation structure 8. In one embodiment, the first upper semiconductor gate electrode portion 252A (i.e., the patterned portion of the second portion of the second semiconductor material layer 242L that is not thinned from the initial thickness) comprises a segment that overlies the top surface of the first trench isolation structure 8.
Each third gate electrode (251F, 252F) comprises a third upper semiconductor gate electrode portion 252F (which is a patterned portion of the third portion of the second semiconductor material layer 242L) and a third lower semiconductor gate electrode portion 251F (which is another patterned portion of the second-transistor lower gate material portion 241) that are located over an active region 5F that is laterally surrounded by the second trench isolation structure 8. The third gate electrode (251F, 252F) overlies and contacts a top surface of the second trench isolation structure 8 and extends over an additional active region to function as a gate electrode of an additional field effect transistor. The photoresist layer 77 can be subsequently removed, for example, by ashing.
Referring to
Referring to
Subsequently, deep source/drain regions 66 can be formed by implanting additional electrical dopants. A first field effect transistor 200T can be formed in the first transistor region (such as the first n-type field effect transistor region 200) by forming a first source region (64, 66) and a first drain region (64, 66) in the first active region 5A. The first source region (64, 66) and the first drain region (64, 66) are laterally spaced from each other by a first channel (i.e., upper portion of the region 5A) along a first channel direction (such as the second horizontal direction hd2). Second field effect transistors 1200S and third field effect transistors 1200T can be formed in the transistor array region 1200 by forming second source regions (64, 66) and second drain regions (64, 66) in the second active region 5F. Each pair of a second source region (64, 66) and a second drain region (64, 66) in a second field effect transistor 1200S can be laterally spaced from each other along a second channel direction (such as the first horizontal direction hd1). Each pair of a third source region (64, 66) and a third drain region (64, 66) in a third field effect transistor 1200T can be laterally spaced from each other along a third channel direction, which can be the same as the second channel direction (such as the first horizontal direction hd1).
Referring to
Subsequently, at least one dielectric material layer such as a contact-level dielectric layer 70 can be formed over the metal-semiconductor alloy regions (58, 68) and the trench isolation structures 8. Various contact via cavities can be formed through the contact-level dielectric layer 70, and various contact via structures 88 can be formed on a respective one of the metal-semiconductor alloy regions (58, 68).
The process of the ninth embodiment reduces the cost of fabrication while providing a more compact fringeless transistors to increase the device density.
Referring to
In one embodiment, the first field effect transistor 200T comprises a first gate electrode (58, 251A, 252A) overlying a first active region 5A that contains a first source region 66 and a first drain region 66 that are laterally spaced from each other along a first channel direction hd2. The first gate electrode (58, 251A, 252A) extends laterally along a first gate electrode length direction hd1 that is perpendicular to the first channel direction hd2, and comprises a first lower semiconductor gate electrode portion 251A and a first upper semiconductor gate electrode portion 252A including a uniform-thickness region having a first thickness t1 throughout. The second field effect transistor overlies a first portion of a second active region 5F that contains a second source region 66 and a second drain region 66 that are laterally spaced from each other along a second channel direction hd1. The second gate electrode (251B, 252B) extends laterally along a second gate electrode length direction hd2 that is perpendicular to the second channel direction hd1. The second upper semiconductor gate electrode portion 252B has a variable second thickness that that is less than the first thickness t1,
In one embodiment, the first channel direction hd2 is perpendicular to the second channel direction hd1. In one embodiment, the second active region 5F is laterally surrounded by a trench isolation structure 8 comprising a dielectric fill material; and the second gate electrode (251B, 252B) has tapered widthwise sidewalls that are in contact with the trench isolation structure 8. In one embodiment, the second gate electrode (251B, 252B) has a variable lateral extent along the second gate electrode length direction hd2 extent that decreases with a vertical distance from the top surface of the second active region 5F.
In one embodiment, the second lower semiconductor gate electrode portion 251B has a uniform thickness throughout; and a second upper semiconductor gate electrode portion 252B has a minimum thickness at a midpoint between a pair of sidewalls of the trench isolation structure 8 that contact the tapered widthwise sidewalls of the second gate electrode (251B, 252B). In one embodiment, an entirety of two widthwise sidewalls of the second lower semiconductor gate electrode portion 251B is in contact with the trench isolation structure 8; a lower portion of each of two widthwise sidewalls of the second upper semiconductor gate electrode portion 252B is in contact with the trench isolation structure 8; and an upper portion of each of the two widthwise sidewalls of the second upper semiconductor gate electrode portion 252B overlies a top surface of the trench isolation structure 8.
In one embodiment, the first lower semiconductor gate electrode portion 251A has a maximum lateral extent along the first gate electrode length direction hd1 that is the same as a lateral extent of a top surface of the first active region 5A along the first gate electrode length direction; and the first upper semiconductor gate electrode portion 252A comprises a lower portion having a lateral extent along the first gate electrode length direction hd1 that is not greater than the lateral extent of the top surface of the first active region along the first gate electrode length direction, and further comprises an upper portion having a lateral extent along the first gate electrode length direction that is greater than the lateral extent of the top surface of the first active region along the first gate electrode length direction.
In one embodiment, the semiconductor structure comprises: a first trench isolation structure 8 laterally surrounding the first active region; and a second trench isolation structure 8 laterally surrounding the second active region, wherein: the first gate electrode (251A, 252A) contacts a top surface of the first trench isolation structure 8; and the second gate electrode (251B, 252B) does not contact a top surface of the second trench isolation structure 8. In one embodiment, the first upper semiconductor gate electrode portion 252A includes a variable thickness region having an areal overlap with the first active region in a plan view and having a minimum thickness not less than the first thickness t1. In one embodiment, the first upper semiconductor gate electrode portion comprises an additional uniform-thickness region overlying the top surface of the first trench isolation structure 8 and having the first thickness t1 throughout.
In one embodiment, the first trench isolation structure 8 comprises: a recessed horizontal surface that is recessed relative to the top surface of the first trench isolation structure 8; and a sidewall surface connecting the recessed horizontal surface and the top surface of the first trench isolation structure 8 and vertically coincident with a sidewall of the first upper semiconductor gate electrode portion 252A.
In one embodiment, the third field effect transistor overlies a second portion of the second active region 5F that contains a third source region 66. The shared source/drain region 66S comprises the second drain region which is a common drain region 66S of the second field effect transistor 1200S and the third field effect transistor 1200T. The third gate electrode (251F, 252F) comprises an additional upper semiconductor gate electrode portion (such as a third upper semiconductor gate electrode portion 252F) having a variable thickness that is not less than the first thickness t1. In one embodiment, the minimum thickness of the third upper semiconductor gate electrode portion 252F may be a third thickness t3, which is greater than the first thickness t1.
In one embodiment, a maximum lateral extent of the second gate electrode (251B, 252B) along the second gate electrode length direction hd2 is the same as a lateral dimension of a top surface of the second active region 5F along the second gate electrode length direction; and the third gate electrode (251F, 252F) extends laterally along the second gate electrode length direction hd2 by a lateral distance that is greater than the lateral dimension of the top surface of the second active region 5F along the second gate electrode length direction.
In one embodiment, the third gate electrode (251F, 252F) comprises an additional lower gate electrode portion 251F having a same material composition and a same thickness as the first lower gate electrode portion, and further comprises an additional upper gate electrode portion 252F having a variable thickness which is the same as or greater than the first thickness t1. In one embodiment, a minimum thickness of a first segment of the additional upper gate electrode portion 252F having an areal overlap with the second active region in a plan view is a third thickness t3 that is greater than the first thickness t1; and a second segment of the additional upper gate electrode portion having an areal overlap with the second trench isolation structure 8 has a uniform thickness that equals the first thickness t1.
In one embodiment, the semiconductor structure comprises additional third field effect transistors that are located adjacent to the third field effect transistor, wherein the third gate electrode (251F, 252F) extends over active regions of the additional third field effect transistors and functions as a common gate electrode (251F, 252F) for each of the third field effect transistor and the additional third field effect transistor, and wherein a minimum thickness of the common gate electrode (251F, 252F) is greater than a maximum thickness of the second electrode of the second field effect transistor.
Although the foregoing refers to particular preferred embodiments, it will be understood that the disclosure is not so limited. It will occur to those of ordinary skill in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the disclosure. Where an embodiment employing a particular structure and/or configuration is illustrated in the present disclosure, it is understood that the present disclosure may be practiced with any other compatible structures and/or configurations that are functionally equivalent provided that such substitutions are not explicitly forbidden or otherwise known to be impossible to one of ordinary skill in the art. All of the publications, patent applications and patents cited herein are incorporated herein by reference in their entirety.
This application is a continuation-in-part (CIP) application of U.S. application Ser. No. 17/501,163 filed on Oct. 14, 2021, which is a CIP application of U.S. application Ser. No. 17/316,015 filed on May 10, 2021, the entire contents of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17501163 | Oct 2021 | US |
| Child | 18500721 | US | |
| Parent | 17316015 | May 2021 | US |
| Child | 17501163 | US |
