Patent Application
20230029955
The semiconductor industry has grown due to continuous improvements in integration density of various electronic components (e.g., transistors, diodes, resistors, inductors, capacitors, etc.). For the most part, these improvements in integration density have come from successive reductions in minimum feature size, which allow more components to be integrated into a given area. In this regard, individual transistors, interconnects, and related structures have become increasingly smaller and there is an ongoing need to develop new materials, processes, and designs of semiconductor devices and interconnects to allow further progress.
Thin-film transistors made of oxide semiconductors are an attractive option for back-end-of-line (BEOL) integration since thin-film transistors may be processed at low temperatures and thus, may not damage previously fabricated devices. For example, the fabrication conditions and techniques may not damage previously fabricated front-end-of-line (FEOL) and middle end-of-line (MEOL) devices. Circuits based on thin-film transistor devices may further include other components that may be fabricated in a BEOL process, such as capacitors, inductors, resistors, and integrated passive devices.
Aspects of this disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, this disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Unless explicitly stated otherwise, each element having the same reference numeral is presumed to have the same material composition and to have a thickness within a same thickness range.
According to various embodiments of this disclosure, a transistor structure (e.g., a thin-film transistor) is provided that may be formed in a BEOL process and may be incorporated with other BEOL circuit components such as capacitors, inductors, resistors, and integrated passive devices. As such, the disclosed transistor structure may include materials that may be processed at low temperatures and thus, may not damage previously fabricated devices (e.g., FEOL and MEOL devices).
Existing BEOL compatible thin-film transistors often suffer degradation of the on-current due to high Schottky barrier heights respectively between the source electrode the active region, and between drain electrode and the active region. Metal contacts for source and drain electrodes of existing systems typically include pure metals (e.g., W, Cu, etc.) or materials deposited using PVD (TiN, W, etc.). Both such materials tend to have low amounts of hydrogen in the material and therefore often result in a high contact resistance and degraded device performance. Hydrogen is known to act has a donor-like dopant in oxide semiconductor materials used in thin-film transistors. By using a metal compound rich in hydrogen the source and drain region can be selectively doped to have high carrier concentration which may reduce the Schottky barrier height and the contact resistance and thereby improve device performance.
Various embodiment transistor structures include a gate electrode, an active layer, a gate dielectric layer separating the active layer from the gate electrode, a source electrode, a drain electrode, and a hydrogen-rich material layer separating the source electrode and the drain electrode from the active layer.
Shallow trench isolation structures 106 including a dielectric material such as silicon oxide may be formed in an upper portion of the semiconductor material layer 104. Suitably doped semiconductor wells, such as p-type wells and n-type wells, may be formed within each area that is laterally enclosed by a portion of the shallow trench isolation structures 106. Field effect transistors 108 may be formed over a top surface of the semiconductor material layer 104. For example, each of the field effect transistors 108 may include a source electrode 110, a drain electrode 112, a semiconductor channel 114 that includes a surface portion of the substrate 102 extending between the source electrode 110 and the drain electrode 112, and a gate structure 116. The semiconductor channel 114 may include a single crystalline semiconductor material.
Each gate structure 116 may include a gate dielectric layer 118, a gate electrode 120, a gate cap dielectric 122, and a dielectric gate spacer 124. A source-side metal-semiconductor alloy region 126 may be formed on each source electrode 110, and a drain-side metal-semiconductor alloy region 128 may be formed on each drain electrode 112. The devices formed on the top surface of the semiconductor material layer 104 may include complementary metal-oxide-semiconductor (CMOS) transistors and optionally additional semiconductor devices (such as resistors, diodes, capacitors, etc.), and are collectively referred to as CMOS circuitry 134.
The semiconductor structure 100 of
Devices (such as field effect transistors 108) in the peripheral region 132 may provide functions that operate the array of memory cells to be subsequently formed. Specifically, devices in the peripheral region may be configured to control the programming operation, the erase operation, and the sensing (read) operation of the array of memory cells. For example, the devices in the peripheral region may include a sensing circuitry and/or a programming circuitry.
One or more of the field effect transistors 108 in the CMOS circuitry 134 may include a semiconductor channel 114 that contains a portion of the semiconductor material layer 104 in the substrate 102. If the semiconductor material layer 104 includes a single crystalline semiconductor material such as single crystalline silicon, the semiconductor channel 114 of each of the field effect transistors 108 in the CMOS circuitry 134 may include a single crystalline semiconductor channel such as a single crystalline silicon channel. In one embodiment, a plurality of field effect transistors 108 in the CMOS circuitry 134 may include a respective node that is subsequently electrically connected to a node of a respective memory cell to be subsequently formed. For example, a plurality of field effect transistors 108 in the CMOS circuitry 134 may include a respective source electrode 110 or a respective drain electrode 112 that is subsequently electrically connected to a node of a respective memory cell to be subsequently formed.
In one embodiment, the CMOS circuitry 134 may include a programming control circuit configured to control gate voltages of a set of field effect transistors 108 that may be used for programming a respective memory cell (e.g., a ferroelectric memory cell) and to control gate voltages of transistors (e.g., thin-film transistors) to be subsequently formed. In this embodiment, the programming control circuit may be configured to provide a first programming pulse that programs a respective ferroelectric dielectric material layer in a selected ferroelectric memory cell into a first polarization state in which electrical polarization in the ferroelectric dielectric material layer points toward a first electrode of the selected ferroelectric memory cell, and to provide a second programming pulse that programs the ferroelectric dielectric material layer in the selected ferroelectric memory cell into a second polarization state in which the electrical polarization in the ferroelectric dielectric material layer points toward a second electrode of the selected ferroelectric memory cell.
In one embodiment, the substrate 102 may include a single crystalline silicon substrate, and the field effect transistors 108 may include a respective portion of the single crystalline silicon substrate as a semiconducting channel. As used herein, a “semiconducting” element refers to an element having electrical conductivity in the range from 1.0×10−6 S/cm to 1.0×105 S/cm. As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1.0×10−6 S/cm to 1.0×105 S/cm in the absence of electrical dopants therein, and is capable of producing a doped material having electrical conductivity in a range from 1.0 S/cm to 1.0×105 S/cm upon suitable doping with an electrical dopant.
According to an embodiment, the field effect transistors 108 may be subsequently electrically connected to drain electrodes and gate electrodes of access transistors including semiconducting metal oxide plates to be formed above the field effect transistors 108. In one embodiment, a subset of the field effect transistors 108 may be subsequently electrically connected to at least one of the drain electrodes and the gate electrodes. For example, the field effect transistors 108 may include first word line drivers configured to apply a first gate voltage to first word lines through a first subset of lower-level metal interconnect structures to be subsequently formed, and second word line drivers configured to apply a second gate voltage to second word lines through a second subset of the lower-level metal interconnect structures. Further, the field effect transistors 108 may include bit line drivers configured to apply a bit line bias voltage to bit lines to be subsequently formed, and sense amplifiers configured to detect electrical current that flows through the bit lines during a read operation.
Various metal interconnect structures formed within dielectric material layers may be subsequently formed over the substrate 102 and the semiconductor devices thereupon (such as field effect transistors 108). In an illustrative example, the dielectric material layers may include, for example, a first dielectric material layer 136 that may be a layer that surrounds the contact structure connected to the source and drains (sometimes referred to as a contact-level dielectric material layer), a first interconnect-level dielectric material layer 138, and a second interconnect-level dielectric material layer 140. The metal interconnect structures may include device contact via structures 142 formed in the first dielectric material layer 136 and contact a respective component of the CMOS circuitry 134, first metal line structures 144 formed in the first interconnect-level dielectric material layer 138, first metal via structures 146 formed in a lower portion of the second interconnect-level dielectric material layer 140, and second metal line structures 148 formed in an upper portion of the second interconnect-level dielectric material layer 140.
Each of the dielectric material layers (136, 138, 140) may include a dielectric material such as undoped silicate glass, a doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (142, 144, 146, 148) may include at least one conductive material, which may be a combination of a metallic liner (such as a metallic nitride or a metallic carbide) and a metallic fill material. Each metallic liner may include TiN, TaN, WN, TiC, TaC, and WC, and each metallic fill material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, TiN, alloys thereof, and/or combinations thereof.
Other suitable metallic liner and metallic fill materials within the contemplated scope of disclosure may also be used. In one embodiment, the first metal via structures 146 and the second metal line structures 148 may be formed as integrated line and via structures by a dual damascene process. The dielectric material layers (136, 138, 140) are herein referred to as lower-lower-level dielectric material layers. The metal interconnect structures (142, 144, 146, 148) formed within in the lower-level dielectric material layers are herein referred to as lower-level metal interconnect structures.
While the disclosure is described using an embodiment in which an array of memory cells may be formed over the second line-and-via-level dielectric material layer 140, embodiments are expressly contemplated herein in which the array of memory cells may be formed at a different metal interconnect level.
An array of thin-film transistors and an array of ferroelectric memory cells (or other types of memory cells) may be subsequently deposited over the dielectric material layers (136, 138, 140) that have formed therein the metal interconnect structures (142, 144, 146, 148). The set of all dielectric material layer that are formed prior to formation of an array of thin-film transistors or an array of ferroelectric memory cells is collectively referred to as lower-level dielectric material layers (136, 138, 140). The set of all metal interconnect structures that is formed within the lower-level dielectric material layers (136, 138, 140) is herein referred to as first metal interconnect structures (142, 144, 146, 148). Generally, first metal interconnect structures (142, 144, 146, 148) formed within at least one lower-level dielectric material layer (136, 138, 140) may be formed over the semiconductor material layer 104 that is located in the substrate 102.
According to an embodiment, thin-film transistors may be subsequently formed in a metal interconnect level that overlies that metal interconnect levels that contain the lower-level dielectric material layers (136, 138, 140) and the first metal interconnect structures (142, 144, 146, 148). In one embodiment, a planar dielectric material layer having a uniform thickness may be formed over the lower-level dielectric material layers (136, 138, 140). The planar dielectric material layer is herein referred to as an insulating matrix layer 150. The insulating matrix layer 150 may include a dielectric material such as undoped silicate glass, a doped silicate glass, organosilicate glass, or a porous dielectric material, and may be deposited by chemical vapor deposition. The thickness of the insulating matrix layer 150 may be in a range from 20 nm (i.e., 200 angstrom) to 300 nm (i.e., 3000 angstrom), although lesser and greater thicknesses may also be used.
Generally, interconnect-level dielectric layers (such as the lower-level dielectric material layer (136, 138, 140)) containing therein the metal interconnect structures (such as the first metal interconnect structures (142, 144, 146, 148)) may be formed over semiconductor devices. The insulating matrix layer 150 may be formed over the interconnect-level dielectric layers. Other passive devices may be formed in BEOL processes. For example various capacitors, inductors, resistors, and integrated passive devices may be utilized with other BEOL devices.
The substrate 202 may include, for example, undoped silicate glass, a doped silicate glass (e.g., deposited by decomposition of tetraethylorthosilicate (TEOS)), organosilicate glass, silicon oxynitride, or silicon carbide nitride. Other dielectric materials are within the contemplated scope of disclosure. The dielectric material of the substrate 202 may be deposited by a conformal deposition process (such as a chemical vapor deposition process) or a self-planarizing deposition process (such as spin coating). The thickness of the substrate 202 may each be in a range from approximately 15 nm to approximately 60 nm, such as from approximately 20 nm to approximately 40 nm, although smaller and larger thicknesses may also be used.
The intermediate structure 200 of
The first inter-layer dielectric layer 206L may include, but is not limited to, silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina, or various other insulating structures such as a multi-layer stack structure including alternating insulating layers. The first inter-layer dielectric layer 206L may be deposited by any suitable technique as CVD, ALD, PVD, plasma enhanced chemical vapor deposition (PECVD), etc.
In this example, the first inter-layer dielectric layer 206L may be formed as a planar blanket (i.e., un-patterned) layer having a planar top surface and a planar bottom surface. Excess portions of the first inter-layer dielectric layer 206L may be removed from above the top surface of the intermediate structure 200 by a planarization process, for example, by chemical mechanical planarization (CMP). A thickness of the first inter-layer dielectric layer 206L may be in a range from approximately 5 nm to approximately 50 nm, such as from approximately 20 nm to approximately 40 nm, although other embodiments may include smaller and larger thicknesses.
The patterned photoresist may then be used as a mask for patterning the first inter-layer dielectric layer 206L. In this regard, an anisotropic etch process may be performed to remove a region the first inter-layer dielectric layer 206L to thereby generate a via cavity 302. As shown in
The metallic liner material and metallic fill materials may be formed by suitable deposition process, which may include one or more of a CVD process, a PVD process, an ALD process, an electroplating process, etc. Other suitable deposition processes are within the contemplated scope of disclosure. Excess portions of the conductive material may be removed from above a horizontal plane including the top surface of the first patterned inter-layer dielectric layer 206 by a planarization process. The planarization process may include use of a CMP process although other suitable planarization processes may be used.
The gate dielectric layer 502 may be formed by any suitable technique as ALD, CVD, PECVD, PVD, etc. Excess portions of the gate dielectric layer 502 may be removed from above a horizontal plane of the intermediate structure 500 including a top surface of the gate dielectric layer 502 by a planarization process. The planarization process may include use of a CMP process although other suitable planarization processes may be used. A thickness of the gate dielectric layer 502 may be in a range from approximately 3 nm to approximately 15 nm, such as from approximately 5 nm to approximately 12 nm, although other embodiments may include smaller and larger thicknesses. Following the deposition of the gate dielectric layer 502, the intermediate structure 500 may optionally be annealed. The optional annealing process may be performed at a temperature in a range from 200° C. to 400° C. using a rapid thermal annealing or furnace annealing process. The annealing may be performed in an environment of nitrogen, oxygen, or a mixture thereof.
In this example, the oxide semiconductor layer 602L may be formed as a planar blanket (i.e., un-patterned) layer having a planar top surface and a planar bottom surface. Excess portions of the oxide semiconductor layer 602L may be removed from above the top surface of the intermediate structure 600 by a planarization process, for example, by CMP. A thickness of the first inter-layer dielectric layer 206L may be in a range from approximately 3 nm to approximately 20 nm, such as from approximately 5 nm to approximately 15 nm, although other embodiments may include smaller and larger thicknesses. Following the deposition of the oxide semiconductor layer 602L, the intermediate structure 600 may optionally be annealed. The optional annealing process may be performed at a temperature in a range from 200° C. to 400° C. using a rapid thermal annealing or furnace annealing process. The annealing may be performed in an environment of nitrogen, oxygen, or a mixture thereof.
The patterned photoresist may then be used as a mask for patterning the oxide semiconductor layer 602L. In this regard, an anisotropic etch process may be performed to remove a region the oxide semiconductor layer 602L having a first portion 702a and a second portion 702b. As shown, in
In this example, the second inter-layer dielectric layer 802L may be formed as a planar blanket (i.e., un-patterned) layer having a planar top surface and a planar bottom surface. Excess portions of the second inter-layer dielectric layer 802L may be removed from above the top surface of the intermediate structure 800 by a planarization process, for example, by CMP. A thickness of the second inter-layer dielectric layer 802L may be in a range from approximately 5 nm to approximately 50 nm, such as from approximately 20 nm to approximately 40 nm, although other embodiments may include smaller and larger thicknesses.
The patterned photoresist may then be used as a mask for patterning the second inter-layer dielectric layer 802L. An anisotropic etch process may be performed to remove respective first and second regions of the second inter-layer dielectric layer 802L to thereby generate a first via cavity 902a and a second via cavity 902b. As shown in
The first hydrogen-rich material layer 1002a and the second hydrogen-rich material layer 1002b may include, but are not limited to, TiN, WN, WCN Co, PdCo, Mo, etc., and alloys of W, Mo, Co, Pd, Ti, and mixtures thereof, with or without N and/or O, and may be deposited using CVD, ALD, or by other processes that include hydrogen precursors/reactants. A thickness of the first hydrogen-rich material layer 1002a and the second hydrogen-rich material layer 1002b may be in a range from approximately 1 nm to approximately 50 nm, such as from approximately 20 nm to approximately 40 nm, although other embodiments may include smaller and larger thicknesses.
The source electrode 1102 and drain electrode 1104 may formed by depositing a conductive material into the first via cavity 902a and the second via cavity 902b, respectively. The conductive material deposited may include a metallic liner material and a metallic fill material. The metallic liner material may include a conductive metallic nitride or a conductive metallic carbide such as TiN, TiN/W, Ti/Al/Ti, TaN, WN, TiC, TaC, and/or WC. A thickness of the metallic liner material may be in a range from approximately 1 nm to approximately 10 nm, such as from approximately 3 nm to approximately 8 nm, although smaller and larger thicknesses may also be used.
The metallic fill material may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, TiN, alloys thereof, and/or combinations thereof. Other suitable metallic liner and metallic fill materials within the contemplated scope of this disclosure may also be used. A thickness of the metallic fill material may be in a range from approximately 10 nm to approximately 50 nm, such as from approximately 20 nm to approximately 40 nm, although smaller and larger thicknesses may also be used.
The metallic liner material and metallic fill materials may be formed by suitable deposition process, which may include one or more of a CVD process, a PVD process, an ALD process, an electroplating process, etc. Other suitable deposition processes are within the contemplated scope of disclosure. Excess portions of the conductive material may be removed from above a horizontal plane including the top surface of the interlayer dielectric layer (802a, 802b, 802c) by a planarization process such as CMP, although other suitable planarization processes may be used.
As shown in
The presence of hydrogen in the first hydrogen-rich material layer 1002a and the second hydrogen-rich material layer 1002b may act to reduce Schottky barriers between the source electrode 1102 and the active layer 602, and between the drain electrode 1104 and the active layer 602, respectively. In this regard, the hydrogen in the first hydrogen-rich material layer 1002a and the second hydrogen-rich material layer 1002b may act as a doner dopant that may increase a carrier concentration in the source electrode 1102, the drain electrode 1104, and the active layer 602. Reduction of the Schottky barriers may lead to an increase in on-current and a decrease of contact resistance relative to comparable devices that do not include the first hydrogen-rich material layer 1002a and the second hydrogen-rich material layer 1002b.
As mentioned above, the active layer 602 may include a semiconducting material including, but not limited to, amorphous silicon, InGaZnO, InGaO, InWO, InZnO, InSnO, ZnO, GaO, InO, and alloys thereof. Other suitable semiconducting materials are within the contemplated scope of disclosure. For example, in various embodiments, the oxide semiconductor layer 602L may include a composition given by InxGayZnzMO, wherein 0<x<1; 0≤y≤1; 0≤z≤1; and M is one of Ti, Al, Ag, Ce, and Sn.
The gate dielectric layer 502 may include a high-k dielectric material including one or more of hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, and hafnium dioxide-alumina. In other embodiments, the gate dielectric layer 502 may include an alternating multi-layer structure including silicon oxide and silicon nitride. Other suitable dielectric materials are within the contemplated scope of disclosure.
In still further embodiments, the gate dielectric layer 502 may include a ferroelectric (FE) material. As such, with the inclusion of a ferroelectric material for the gate dielectric layer 502, the transistor structure 1100 may be configured as a ferroelectric field-effect transistor (FeFET) structure. FeFETs are emerging devices, in which a FE layer is utilized as a gate dielectric layer 502 between a gate electrode 402 and an active layer 602 (also known as a “channel region”). A permanent electrical field polarization in the FE layer causes this type of device to retain the transistor's state (on or off) in the absence of any electrical bias.
A ferroelectric material is a material that may have spontaneous nonzero electrical polarization (i.e., non-zero total electrical dipole moment) when the external electrical field is zero. The spontaneous electrical polarization may be reversed by a strong external electric field applied in the opposite direction. The electrical polarization is dependent not only on the external electrical field at the time of measurement, but also on the history of the external electrical field, and thus, has a hysteresis loop. The maximum of the electrical polarization is referred to as saturation polarization. The electrical polarization that remains after an external electrical field that induces saturation polarization is no longer applied (i.e., turned off) is referred to as remnant polarization. The magnitude of the electrical field that needs to be applied in the opposite direction of the remnant polarization in order to achieve zero polarization is referred to as coercive electrical field.
In some embodiments, a ferroelectric structure, such as a FeFET structure, may form a memory cell of a memory array. In a FeFET-based memory cell, the FE material located between the gate electrode and the channel region of the semiconductor material layer may have two stable remnant polarization states. In one remnant polarization state, the FeFET may be permanently in an “on” state, and in the other remnant polarization state, the FeFET may be permanently in an “off” state. Thus, the polarization state of the FE layer may be used to encode information (i.e., bits) in a non-volatile manner.
The logic state of the FeFET-based memory cell may be read non-destructively by sensing the resistance across the terminals (e.g., source and drain terminals) of the FeFET. The difference between the threshold voltage of the FeFET in the “on” state and in the “off” state may be referred to as the “memory window” (MW) of the FeFET-based memory cell. To re-program the FeFET-based memory cell, a sufficiently high voltage may be applied to the FeFET to induce the polarization state of the FE material to reverse and thereby change the logic state of the FeFET memory cell.
In various embodiments, the gate dielectric layer 502 may include a ferroelectric material, which may include, but may not be limited to a hafnium oxide-based ferroelectric material, such as HfxZr1-xOy where 0≤x≤1 (e.g., Hf0.5Zr0.5O2), HfO2, HfSiO, HfLaO, etc. In various embodiments, the gate dielectric layer 502 may include hafnium zirconium oxide (HZO) doped with atoms having a smaller ionic radius than hafnium (e.g., Al, Si, etc.) and/or doped with atoms having a larger ionic radius than hafnium (e.g., La, Sc, Ca, Ba, Gd, Y, Sr, etc.).
The dopant(s) may be at a concentration configured to improve a ferroelectric property of the gate dielectric layer 502, such as increasing the remnant polarization. In various embodiments, dopants having a smaller ionic radius than hafnium and/or dopants having a larger ionic radius than hafnium may have a doping concentration that is between about 1 mol. % and about 20 mol. %. In some embodiments, the FE material may include oxygen vacancies. Oxygen vacancies in the FE material may promote the formation of orthorhombic (o-phase) crystal phases in the FE material. Other suitable materials for the gate dielectric layer 502 are within the contemplated scope of disclosure, including, without limitation, ZrO2, PbZrO3, Pb[ZrxTi1-x]O3, (0≤x≤1) (PZT), Pb1-xLaxZr1-yTiyO3 (PLZT), BaTiO3, PbTiO3, PbNb2O6, LiNbO3, LiTaO3, PbMg⅓Nb⅔O3 (PMN), PbSc½Ta½O3 (PST), SrBi2Ta2O9 (SBT), Bi½Na½TiO3, and combinations thereof.
The patterned photoresist may then be used as a mask for patterning the second inter-layer dielectric layer 802L. An anisotropic etch process may be performed to remove respective first and second regions of the second inter-layer dielectric layer 802L to thereby generate a first etched region 1202a and a second etched region 1202b. As shown in
The first hydrogen-rich material layer 1302a and the second hydrogen-rich material layer 1302b may include, but are not limited to, TiN, WN, WCN Co, PdCo, Mo, etc., and alloys of W, Mo, Co, Pd, Ti, and mixtures thereof, with or without N and/or 0, and may be deposited using CVD, ALD, or by other processes that include hydrogen precursors/reactants. A thickness of the first hydrogen-rich material layer 1302a and the second hydrogen-rich material layer 1302b may be in a range from approximately 1 nm to approximately 50 nm, such as from approximately 20 nm to approximately 40 nm, although other embodiments may include smaller and larger thicknesses.
The source electrode 1102 and drain electrode 1104 may include a metallic liner material and a metallic fill material. The metallic liner material may include a conductive metallic nitride or a conductive metallic carbide such as TiN, TiN/W, Ti/Al/Ti, TaN, WN, TiC, TaC, and/or WC. A thickness of the metallic liner material may be in a range from approximately 1 nm to approximately 10 nm, such as from approximately 3 nm to approximately 8 nm, although smaller and larger thicknesses may also be used.
The metallic fill material may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, TiN, alloys thereof, and/or combinations thereof. Other suitable metallic liner and metallic fill materials within the contemplated scope of this disclosure may also be used. A thickness of the metallic fill material may be in a range from approximately 10 nm to approximately 50 nm, such as from approximately 20 nm to approximately 40 nm, although smaller and larger thicknesses may also be used.
The metallic liner material and metallic fill materials may be formed by suitable deposition process, which may include one or more of a CVD process, a PVD process, an ALD process, an electroplating process, etc. Other suitable deposition processes are within the contemplated scope of disclosure. Excess portions of the conductive material may be removed from above a horizontal plane including the top surface of the second patterned inter-layer dielectric layer 802 by a planarization process such as CMP, although other suitable planarization processes may be used.
As shown in
As with the embodiment transistor structure 1100 of
The above-described embodiment transistor structures (1100, 1400) are described as including a substrate 202, an etch stop layer 204, a first patterned inter-layer dielectric layer 206, a gate electrode 402, a gate dielectric layer 502, an active layer 602, a hydrogen-rich material layer (1102a, 1102b, 1302a, 1302b), a source electrode 1102, a drain electrode 1104, and a second patterned inter-layer dielectric layer 802. Further, the source electrode 1102 and the drain electrode 1104 are described as including a metallic liner and metallic fill materials. Various other embodiments may include additional layers or fewer layers. For example, in some embodiments, the metallic fill material may be deposited directly on the hydrogen-rich material layer (1102a, 1102b, 1302a, 1302b) without depositing an additional metallic liner material.
In further embodiments, an additional metallic layer (i.e., a “glue layer”) may be deposited between the second patterned inter-layer dielectric layer 802 and the hydrogen-rich material layer (1102a, 1102b, 1302a, 1302b). The additional metallic layer may include materials similar to those used in the metallic liner material described above (e.g., TiN, TaN, WN, TiC, TaC, and WC) and may have a thickness in a range from approximately 1 nm to approximately 10 nm, such as such as from approximately 3 nm to approximately 8 nm, although smaller and larger thicknesses may also be used.
In further embodiments, the metallic fill material of the source electrode 1102 and the drain electrode 1104 may be replaced with a volume of the hydrogen-rich material. In still further embodiments, a capping layer may be formed between the active layer 602 and the second patterned inter-layer dielectric layer 802. The capping layer may include a material that is similar to materials used for the inter-layer dielectric layers (206, 802) and may have a thickness in a range from approximately 1 nm to 20 nm, such as from approximately 5 nm to 15 nm, although smaller and larger thicknesses may also be used. The above-described additional embodiments including greater or fewer layers may be mixed and matched in various ways to form multiple different embodiment transistor structures (1100, 1400). All such alternative embodiments are considered to be within the contemplated scope of this disclosure and no specific embodiment described above should be interpreted as limiting.
In certain embodiments, the capping layer 1502 may include the same or similar materials as those materials that form the inter-layer dielectric layer (802a, 802b, 802c). However, the capping layer may be deposited using a deposition technique or tool settings that are different from the technique/tool settings used to deposit the inter-layer dielectric layer (802a, 802b, 802c) For example, the capping layer 1502 may be deposited using low plasma power ALD or CVD or low bias PVD to thereby avoid damage to the active layer 602.
The thickness of the capping layer 1502 may be in a range from approximately 1 nm to approximately 20 nm, such as from approximately 5 nm to approximately 15 nm, although smaller and larger thicknesses may also be used.
The capping layer 1502 may include, but is not limited to, silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina, or various other insulating structures such as a multi-layer stack structure including alternating insulating layers.
As shown in
As shown in
In operation 1804, the method 1800 may further include forming an active layer 602, and in operation 1806, the method 1800 may include forming a gate dielectric layer 502 that is in contact with the gate electrode 402 and the active layer 602 and separating the gate electrode 402 from the active layer 602. As described above, the gate dielectric layer 502 may be formed by depositing a high-k dielectric material over the gate electrode 402. In this regard, the gate dielectric layer 502 may include, but is not limited to, one or more of hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, and hafnium dioxide-alumina. In further embodiments, forming the gate dielectric layer 502 may include forming an alternating multi-layer structure including silicon oxide and silicon nitride over the gate electrode, or forming a ferroelectric material over the gate electrode 402.
The active layer 602 may be formed by depositing and patterning one of amorphous silicon, InGaZnO, InGaO, InWO, InZnO, InSnO, ZnO, GaO, InO, InZnO, and alloys thereof over the gate dielectric layer 502. Forming the active layer 602 may alternatively include depositing a material having a composition given by InxGayZnz MO, wherein 0<x<1; 0≤y≤1; 0≤z≤1; and M is one of Ti, Al, Ag, Ce, and Sn.
In operation 1808, the method 1800 may include forming a source electrode 1102 and in operation 1810, the method 1800 may include forming a drain electrode 1104. In operation 1812, the method 1800 may further include forming a hydrogen-rich material layer (1002a, 1002b, 1302a, 1302b) separating the source electrode 1102 and the drain electrode 1104 from the active layer 602. In this regard, forming the source electrode 1102, forming the drain electrode 1104, and forming the hydrogen-rich material layer (1002a, 1002b, 1302a, 1302b) further includes forming an inter-layer dielectric layer 802L (e.g., see
The method 1800 may further include performing a chemical vapor deposition process or an atomic layer deposition process to deposit TiN, WN, WCN Co, PdCo, Mo, etc., and alloys of W, Mo, Co, Pd, Ti, and mixtures thereof, with or without N and/or O on the surfaces of the first via cavity 902a (or the first etched region 1202a) and the second via cavity 902b (or the second etched region 1202b) to thereby form the hydrogen-rich material layer (1102a, 1102b, 1302a, 1302b) that is contact with the surfaces of the active layer 602 and the gate dielectric layer 502. The method 1800 may further include depositing a conductive material over the hydrogen-rich material layer (1102a, 1102b, 1302a, 1302b) in the first via cavity 902a (or the first etched region 1202a) and the second via cavity 902b (or the second etched region 1202b) to thereby form the source electrode 1102 and the drain electrode 1104, respectively.
As described above, the method 1800 may include forming various embodiment transistor structures (1100, 1400) in a BEOL process over one of a plurality of metal interconnect level structures (such as the first metal interconnect structures (142, 144, 146, 148)) in an existing semiconductor structure (e.g., the semiconductor structure 100 of
Referring to all drawings and according to various embodiments of the present disclosure, a transistor structure (1100, 1400) is provided. The transistor structure (1100, 1400) may include a gate electrode 402, an active layer 602, a gate dielectric layer 502 separating the active layer 602 from the gate electrode 402, a source electrode 1102, a drain electrode 1104; and a hydrogen-rich material layer (1102a, 1102b, 1302a, 1302b) separating the source electrode 1102 and the drain electrode 1104 from the active layer 602. In this regard, the first hydrogen-rich material layer (1002a, 1302a) separates the source electrode 1102 from the active layer 602, and the second hydrogen-rich material layer (1002b, 1302b) separates the drain electrode 1104 from the active layer 602. As described above, the transistor structure (1100, 1400) may be a thin-film transistor that may be formed in a BEOL process.
The active layer 602 may include a semiconducting material including, but not limited to, amorphous silicon, InGaZnO, InGaO, InWO, InZnO, InSnO, ZnO, GaO, InO, and alloys thereof. Other suitable materials are within the contemplated scope of disclosure. For example, in various embodiments, the oxide semiconductor layer 602L may include a composition given by Inx Gay Znz MO, wherein 0<x<1; 0≤y≤1; 0≤z≤1; and M is one of Ti, Al, Ag, Ce, and Sn.
The gate dielectric layer 502 may include a high-k dielectric material including one or more of hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, and hafnium dioxide-alumina. In other embodiments, the gate dielectric layer 502 may include an alternating multi-layer structure including silicon oxide and silicon nitride. In still further embodiments, the gate dielectric layer 502 may include a ferroelectric material.
In various embodiments, the hydrogen-rich material layer (1102a, 1102b) may include TiN, WN, WCN Co, PdCo, Mo, etc., and alloys of W, Mo, Co, Pd, Ti, and mixtures thereof, with or without N and/or O, deposited by chemical vapor deposition or by atomic layer deposition.
Further embodiments include a transistor structure (1100, 1400) may be provided. The transistor structure (1100, 1400) may include a gate electrode 402, an active layer 602, a gate dielectric layer 502 separating the active layer 602 from the gate electrode 402, a source electrode 1102 and a drain electrode 1104, wherein each of the source electrode 1102 and the drain electrode 1104 include a hydrogen-rich fill material layer.
In one embodiment, the active layer may include one of amorphous silicon, InGaZnO, InGaO, InWO, InZnO, InSnO, ZnO, GaO, InO, InZnO, and alloys thereof. In one embodiment, the active layer may include a composition given by Inx Gay Znz MO, wherein 0<x<1; 0≤y≤1; 0≤z≤1; and M is one of Ti, Al, Ag, Ce, and Sn. In one embodiment, the gate dielectric layer comprises a high-k dielectric material may include one or more of hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, and hafnium dioxide-alumina. In one embodiment, the transistor structure may also include a glue layer separating the source electrode from the active layer and separating the drain electrode from the active layer. In one embodiment, the transistor structure may also include a capping layer formed over the active layer. In one embodiment, the hydrogen-rich fill material may include TiN, WN, WCN Co, PdCo, Mo, etc., and alloys of W, Mo, Co, Pd, Ti, and mixtures thereof, with or without N and/or O, deposited by chemical vapor deposition or by atomic layer deposition.
Various disclosed transistor structures and methods of making the same provide advantages over existing transistor structures. In this regard, a transistor structure (1100, 1400) is provided that may be formed in a BEOL process and may be incorporated with other BEOL circuit components such as capacitors, inductors, resistors, and integrated passive devices. As such, the disclosed transistor structure (1100, 1400) may include materials that may be processed at low temperatures and thus, may not damage previously fabricated devices (e.g., FEOL and MEOL devices). The disclosed transistor structure (1100, 1400) may include a substrate 202 that may be formed in a BEOL process.
The disclosed transistor structures (1100, 1400) may further have improved device performance characteristics relative to existing BEOL compatible transistor structures. In this regard, existing compatible thin-film transistors often suffer degradation of the on-current due to high Schottky barrier heights respectively between the source electrode the active region, and between drain electrode and the active region. Metal contacts for source and drain electrodes of existing systems typically include pure metals (e.g., W, Cu, etc.) or materials deposited using PVD (TiN, W, etc.). Both such materials tend to have low amounts of hydrogen in the material and therefore often result in a high contact resistance and degraded device performance. Hydrogen is known to act has a donor-like dopant in oxide semiconductor materials used in thin-film transistors.
In contrast to existing BEOL compatible transistor structures, disclosed embodiment transistor structures (1100, 1400) include a hydrogen-rich material layer (1002a, 1002b, 1302a, 1302b) separating the source electrode 1102 from the active layer 602, and separating the drain electrode 1104 from the active layer 602. The presence of hydrogen in the hydrogen-rich material layer (1002a, 1002b, 1302a, 1302b) may reduce the contact resistance of the transistor structures (1100, 1400) and may act to reduce Schottky barriers respectively between the source electrode and the active layer, and between the drain electrode and the active layer, and may reduce contact resistances, thus leading to improved device performance.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of this disclosure. Those skilled in the art should appreciate that they may readily use this disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of this disclosure.
This application claims priority to U.S. Provisional Patent Application No. 63/227,075 entitled “Back-End-Of-Line (BEOL) Thin Film Transistor (TFT) having reduced contact resistance through hydrogen-storage in Source/Drain (S/D) metal module and Methods of forming the same” filed on Jul. 29, 2021, the entire contents of which are hereby incorporated by reference for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| 63227075 | Jul 2021 | US |
