Patent Application
20130246709
Architectural-level instructions for microprocessors may be translated between an instruction set architecture (ISA) and a native architecture. In some microprocessors, software optimizations of the ISA instructions may execute comparatively more efficiently than the ISA instructions upon which those software optimizations were based. Some past approaches chained software optimizations to pass control from one software optimization to another. However, such approaches may be challenged by indirectly-branched processes because it may be difficult to determine the target of an indirect branch.
In modern microprocessors, architectural-level instructions may be translated between a source instruction set architecture (ISA), such as an advanced RISC machine (ARM) architecture or an x86 architecture, and an alternate ISA that achieves the same observable functionality as the source. For example, a set of one or more instructions of a source ISA may be translated into one or more micro-operations of a native architecture that perform the same function as the source ISA instruction. In some settings, the native micro-operation(s) may provide enhanced or optimized performance relative to the source ISA instruction.
Some past approaches attempted to chain software optimizations of source instructions so that control passed from one software optimization to another software optimization via direct native branches. However, such approaches may be challenged by branched processes. Because the branch source may be dynamic during program execution, chain-wise handoff between software optimizations may not be feasible. For example, should an indirect branch occur, the indeterminate target of the branch may make it difficult to ascertain which software optimization should be retrieved at the time the optimization is created. Consequently, the microprocessor may stall while the branch and software optimization for that branch are determined from potentially thousands of candidate optimizations.
Accordingly, various embodiments are disclosed herein that are related to fetching source information and alternate versions of the source information that achieve the same observable functionality (referred to herein as the same functionality) of the source information within an acceptable tolerance (e.g., within an acceptable tolerance of architecturally observable effect). It will be appreciated that virtually any suitable source information and any alternate version thereof may be employed without departing from the scope of the present disclosure. In some embodiments, a source may include an instruction, such as an instruction for an ISA architecture. In addition to or instead of instructions, the source information may include source data, and the alternate version may include an alternative form or version of the source data. Likewise, it will be appreciated that any suitable manner of transforming a source into an alternate version thereof (e.g., a software approach and/or a hardware approach) may be contemplated as being within the scope of the present disclosure. For illustrative purposes, the descriptions and figures presented herein refer to source instructions and translations of the source instructions, respectively, as source information and alternate versions of the source information, though such embodiments are not limiting.
One example method includes, upon being directed to retrieve an instruction, hashing an address for that instruction so that it may be determined if there exists an alternate version for that instruction. The hashing is performed to determine whether there exists an alternate version of the instruction which achieves the same functionality, such as a native translation (e.g., translations between a source instruction set architecture and a native micro-operation set architecture for various instructions that may be fetched for execution by the microprocessor). The example method further includes, if hashing results in a determination that such an alternate version exists, aborting retrieving of the instruction and retrieving and executing the alternate version.
The discussion herein will frequently refer to “retrieving” an instruction and then aborting that retrieval if certain conditions exist. In some embodiments, “retrieving” an instruction may include fetching an instruction. Further, when such aborting occurs, the retrieval process is terminated. The termination typically occurs prior to completion of the retrieval process. For example, in one scenario, aborting retrieval may occur while the physical address for an instruction is being retrieved. In another scenario, aborting retrieval may occur after the physical address for an instruction is retrieved but before the instruction is retrieved from memory. Aborting retrieval prior to completion of the retrieval process may save time spent accessing and retrieving the source from memory. It will be appreciated that, as used herein, retrieval is not limited to fetch scenarios, where fetch is typically completed prior to decode. For example, an instruction may be retrieved but aborted during decode, before decode, or at any suitable point.
A wide range of possibilities exist for mapping and translating between source information and translated versions of that information. By determining whether the alternate version exists and aborting retrieving the instruction, for example, an ISA instruction, if the alternate version does exist, the microprocessor may offer enhanced performance relative to microprocessors that decode source ISA instructions by avoiding decode operations. Additional performance enhancement may be realized in settings where the alternate version provides optimized performance by changes to the operations which allow the alternate version to proceed through execution more quickly than the source ISA instruction.
A memory controller 110H may be used to handle the protocol and provide the signal interface required of main memory 110D and to schedule memory accesses. Memory controller 110H can be implemented on the processor die or on a separate die. It is to be understood that the memory hierarchy provided above is non-limiting and other memory hierarchies may be used without departing from the scope of this disclosure.
Microprocessor 100 also includes a pipeline, illustrated in simplified form in
As shown in
Instruction translation lookaside buffer 122 may perform virtually any suitable manner of translating linear addresses into physical addresses for those instructions. For example, in some embodiments, instruction translation lookaside buffer 122 may include content-addressable memory that stores a portion of a page table that maps linear addresses for instructions to physical addresses for those instructions.
Fetch logic 120 also determines whether a native translation for the selected instruction exists. If such a native translation exists, the system aborts the instruction fetch and sends the native translation for execution instead. In the embodiment depicted in
Almost any suitable data storage architecture and logic may be used for translation address cache 124. For example,
Continuing with
The embodiment depicted in
Pipeline 102 may also include mem logic 138 for performing load and/or store operations and writeback logic 140 for writing the result of operations to an appropriate location such as register 109. Upon writeback, the microprocessor enters a state modified by the instruction or instructions, so that the result of the operations leading to the committed state may not be undone.
It should be understood that the above stages shown in pipeline 102 are illustrative of a typical RISC implementation, and are not meant to be limiting. For example, in some embodiments, VLIW-techniques may be implemented upstream of certain pipelined stages. In some other embodiments, the scheduling logic may be included in the fetch logic and/or the decode logic of the microprocessor. More generally a microprocessor may include fetch, decode, and execution logic, with mem and write back functionality being carried out by the execution logic. The present disclosure is equally applicable to these and other microprocessor implementations.
In the described examples, instructions may be fetched and executed one at a time or more than one at a time, possibly requiring multiple clock cycles. During this time, significant parts of the data path may be unused. In addition to or instead of single instruction fetching, pre-fetch methods may be used to improve performance and avoid latency bottlenecks associated with read and store operations (i.e., the reading of instructions and loading such instructions into processor registers and/or execution queues). Accordingly, it will be appreciated that virtually any suitable manner of fetching, scheduling, and dispatching instructions may be used without departing from the scope of the present disclosure.
Turning to
In some embodiments, fetching the selected instruction may include fetching a physical address for the selected instruction from an instruction translation lookaside buffer. In such embodiments, a linear address for the selected instruction may be received upon direction to the target instruction pointer. In turn, the linear address may be translated into a physical address for the selected instruction by the instruction translation lookaside buffer by searching, with reference to the linear address, physical addresses stored in the instruction lookaside buffer. If the search does not hit upon the physical address for the selected instruction, the physical address may be determined via a page walk or via lookup in a higher-level translation lookaside buffer. Regardless of how the physical address is determined, once the physical address for the selected instruction is determined, it is provided to an instruction cache so that the selected instruction may be obtained.
At 304, method 300 comprises hashing the linear address for the selected instruction to generate a hash index from the linear address while the physical address for the selected instruction is being obtained. The hash index may then be used when determining whether a native translation for the selected instruction exists, as described in more detail below.
For example, direction to the target instruction pointer may cause the linear address to be hashed concurrently (within a suitable tolerance) with distribution of the linear address to an instruction translation lookaside buffer. However, it will be appreciated that any suitable manner of performing the hash may be employed at any suitable position within the process flow without departing from the scope of the present disclosure.
In some embodiments, the linear address may be hashed by a suitable hardware structure included in the microprocessor. For example, the linear address may be hashed by the fetch logic and/or the native translation address cache, though virtually any suitable hardware structure may be used to hash the linear address without departing from the scope of the present disclosure.
A wide variety of hash techniques may be employed. For example, in some embodiments, the hash index may be generated using an XOR hash function. A hash index can also be generated by hashing a plurality of portions of the linear address. In some other embodiments, a hash index may be generated by using a single portion of the linear address.
In some embodiments, a disambiguation tag may be generated when the linear address is hashed. The disambiguation tag may be used to discriminate various translation address entries for alternate versions (for example, address entries for native translations of instructions) from one another when more than one translation address entry in the translation address cache has the same index value. Thus, in some embodiments, the disambiguation tag may be used to disambiguate a plurality of translation address entries having identical translation address indices stored in the translation address cache. For example,
While the discussion above relates to hashing a linear address to obtain one or more translation address entries from a translation address cache, so that the translation address entries are indexed according to linear addresses, it will be appreciated that the translation address cache may be indexed according to any suitable address. For example, in some embodiments, a suitably-configured translation address cache may be indexed according to physical addresses. Indexing a translation address cache according to physical addresses may save space within the translation address cache when two processes map to a shared library at different linear addresses. In some of such scenarios, only one version of the shared library may be physically loaded into memory. By indexing according to a physical address, a shared mapping may lead to a single entry being obtained, while an unshared mapping may lead to different entries being obtained.
Turning to
Regardless of when the validity determination is performed, if it is determined that a valid native translation exists, fetching the source instruction may be aborted, by aborting retrieval of the physical address for the source instruction, for example. In turn, processing efficiency may be enhanced by avoiding decode steps and by permitting use of the alternate version.
In the embodiment shown in
A translation address entry stores a physical address where a native translation is stored. Translation address entries may be looked up according to a translation address index associated therewith. For example, a hash index generated when hashing an address may be used to look up a particular translation address index in a translation address cache.
In some embodiments, more than one translation address entry may be obtained via lookup of a particular translation address index. For example, a hashed address used to look up a translation address index for a 4-way associative cache may result in the retrieval of up to four translation address entries. In such embodiments, each translation address entry has a respective translation address disambiguation tag that disambiguates that entry from other entries having identical translation address indices. Comparing the disambiguation tag generated by hashing the address with disambiguation tags retrieved with respective translation address entries may determine whether any of the entries obtained represents a physical address for a valid native translation. In some embodiments, comparison of the disambiguation tags may include a comparison of a valid bit. In such embodiments, agreement between tags being compared may be found only if the valid bit is set to a preselected value, such as a value of 1.
In some embodiments, a translation address entry may include bits representative of the physical address for a native translation and bits representative of an assumed context for the native translation. Additionally, in some embodiments, a translation address entry may include one or more other bits related to the translation and/or aspects of the translation.
Continuing with
As introduced above, in some embodiments, a translation address entry may include an assumed context for the native translation. As used herein, a current context describes a current working state of the microprocessor and an assumed context describes a state of the microprocessor for which the native translation is valid. Thus, in some embodiments, even if a valid disambiguation tag for an entry is identified, the entry associated with that disambiguation tag may not include a valid native translation for the current context. In some examples, issuing a native translation for which the current context and assumed context do not agree may cause an execution error or hazard.
It will be appreciated that the context may be included in any suitable part of the translation address entry and/or the translation address. In the example shown in
Additionally or alternatively, in some embodiments, bits for the assumed context may be included in the translation address, such as in the disambiguation tag and/or the hash. In such embodiments, inclusion of the assumed context in one or more parts of the address may allow concurrent storage of two or more entries with different contexts and otherwise identical linear addresses within the translation address cache. It will be appreciated that implementation of such embodiments may depend upon application-specific considerations. For example, in some embodiments where set associativity is low, such as in a scenario where the addresses are directly mapped, the assumed context may be included in the hash may avoid a conflict miss. For example, the assumed context may be XOR'ed into the hash during hashing. In some other embodiments, such as those where a cycle time for hashing additional bits affects processing time more than a time for processing a comparatively wider disambiguation tag, the assumed context may be added to the disambiguation tag to avoid potential processing delays. As an example, the assumed context may be appended to the disambiguation tag. In still other embodiments, the assumed context may be included in the hash and in the disambiguation tag.
Once it is determined that a valid native translation exists, method 300 comprises, at 320, aborting fetching the instruction. When aborting occurs, the fetch process is terminated. While the termination may occur after fetch of the instruction, in some embodiments the termination may occur prior to completion of the fetch process. For example, in embodiments where fetching the instruction includes retrieving the physical address for an instruction from an instruction translation lookaside buffer, aborting fetching the instruction may include aborting retrieving the physical address from the instruction translation lookaside buffer.
At 322, method 300 includes sending the physical address for the native translation to the instruction cache, and, at 324, receiving the selected native translation from the instruction cache. In some embodiments, once the selected native translation is received from the instruction cache, it may be forwarded to a native translation buffer in preparation for eventual distribution to scheduling logic where it is to be scheduled for execution.
Alternatively, in the embodiment shown in
Consequently, by determining the existence of alternate versions for the source material, (in the examples described above, native translations that provide the same functionality as the source instructions) while fetching the source material, the methods described herein may offer enhanced processing relative to processing based on the source material alone. Further, by utilizing hardware structures to perform the concurrent determination, the methods described herein may be comparatively more efficient relative to software optimization-based schemes, particularly in branched processing scenarios.
This written description uses examples to disclose the invention, including the best mode, and also to enable a person of ordinary skill in the relevant art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples as understood by those of ordinary skill in the art. Such other examples are intended to be within the scope of the claims.
