Claims
- 1. A trench DMOS transistor cell, comprising:
a substrate of a first conductivity type; a body region on the substrate, said body region having a second conductivity type; at least one trench extending through the body region and the substrate; an insulating layer that lines the trench; a conductive electrode in the trench overlying the insulating layer; a source region of the first conductivity type in the body region adjacent to the trench; and wherein said trench has sidewalls that define a polygon in the plane of the substrate so that adjacent sidewalls contact one another at an angle greater than 90 degrees.
- 2. The DMOS transistor cell of claim 1 wherein said trench has a generally rectangular cross-sectional shape in at least two orthogonal planes.
- 3. The DMOS transistor cell of claim 1 further comprising a drain electrode disposed on a surface of the substrate opposing the body region.
- 4. The DMOS transistor cell of claim 1 wherein said insulating layer is an oxide layer.
- 5. The DMOS transistor cell of claim 1 wherein said conductive electrode includes polysilicon.
- 6. The DMOS transistor cell of claim 5 wherein said polysilicon includes a dopant material.
- 7. The DMOS transistor cell of claim 5 wherein said polysilicon includes a layer of undoped polysilicon and a layer of doped polysilicon.
- 8. The DMOS transistor cell of claim 1 wherein said polygon is a hexagon and said angle is equal to 135 degrees
- 9. The DMOS transistor cell of claim 7 wherein said polygon is a hexagon and said angle is equal to 135 degrees.
- 10. A trench DMOS transistor structure that includes a plurality of individual trench DMOS transistor cells formed on a substrate of a first conductivity type, each of said individual trench DMOS transistor cells comprising:
a body region on the substrate, said body region having a second conductivity type; at least one trench extending through the body region and the substrate; an insulating layer that lines the trench; a conductive electrode in the trench overlying the insulating layer; a source region of the first conductivity type in the body region adjacent to the trench; and wherein said trench has sidewalls that define a polygon in the plane of the substrate so that adjacent sidewalls contact one another at an angle greater than 90 degrees.
- 11. The DMOS transistor structure of claim 10 wherein said trench has a generally rectangular cross-sectional shape in at least two orthogonal planes.
- 12. The DMOS transistor structure of claim 10 further comprising a drain electrode disposed on a surface of the substrate opposing the body region.
- 13. The DMOS transistor structure of claim 10 wherein said insulating layer is an oxide layer.
- 14. The DMOS transistor structure of claim 10 wherein said conductive electrode includes polysilicon.
- 15. The DMOS transistor structure of claim 14 wherein said polysilicon includes a dopant material.
- 16. The DMOS transistor structure of claim 14 wherein said polysilicon includes a layer of undoped polysilicon and a layer of doped polysilicon.
- 17. The DMOS transistor structure of claim 10 wherein at least one of said trench DMOS transistor cells have a closed cell geometry.
- 18. The DMOS transistor structure of claim 10 wherein at least one of said trench DMOS transistor cells have an open cell geometry.
- 19. The DMOS transistor structure of claim 10 further comprising a plurality of polysilicon contacts respectively connected to transistor cells located along the periphery of the structure.
- 20. The DMOS transistor structure of claim 19 further comprising a polysilicon trench guard ring coupling together said plurality of polysilicon contacts.
- 21. The DMOS transistor structure of claim 17 further comprising a plurality of polysilicon contacts respectively connected to transistor cells located along the periphery of the structure.
- 22. The DMOS transistor structure of claim 21 further comprising a polysilicon trench guard ring coupling together said plurality of polysilicon contacts.
- 23. The DMOS transistor structure of claim 18 further comprising a plurality of polysilicon contacts respectively connected to transistor cells located along the periphery of the structure.
- 24. The DMOS transistor structure of claim 23 further comprising a polysilicon trench guard ring coupling together said plurality of polysilicon contacts.
- 25. The DMOS transistor structure of claim 10 wherein said polygon is a hexagon and said angle is equal to 135 degrees.
- 26. The DMOS transistor structure of claim 16 wherein said polygon is a hexagon and said angle is equal to 135 degrees.
STATEMENT OF RELATED APPLICATIONS
[0001] The present invention is related to U.S. application Ser. No. 09/395,832, entitled “Trench DMOS Transistor Having Improved Trench Structure,” filed in the United States Patent and Trademark Office Sep. 14, 1999, now abandoned.