Trench MOS barrier schottky rectifier with a planar surface using CMP techniques

Description

BACKGROUND

The present invention relates to semiconductor power device technology and more particularly to improved trench MOS (metal oxide semiconductor) barrier Schottky rectifiers with planar surfaces and fabrication processes for forming the same.

Trench MOS barrier Schottky (TMBS) rectifiers are Schottky diodes that have been integrated with trench gate shielding structures (e.g., TMBS rectifiers or monolithically integrated trench gate FET and Schottky diode devices). An integrated TMBS, which typically includes a Schottky diode array that has been interspersed between MOS trenches, generally comprises a mesa structure formed in a semiconductor epitaxial layer of a semiconductor substrate. The mesa is defined by the region between one or more trenches, which are disposed in the epitaxial layer. In TMBS devices, charge coupling between majority charge carriers in a mesa disposed between trenches in the epitaxial/drift region and conductors on the sidewalls of the trenches changes the electric field profile under the Schottky contact which reduces reverse leakage current and improves breakdown properties.

Existing techniques used to fabricate TMBS rectifiers produce topographies between device structures. For example, in an active array the tops of the polysilicon gates, silicon mesa and field dielectric are irregular and not substantially flat. This irregular topography can include abrupt changes which can significantly affect device performance by increasing reverse leakage current. Further, topographies which are created between the polysilicon gates and the mesa regions or the field dielectric to the active array propagate to layers that are subsequently formed on top of the polysilicon gates and mesa regions or the field dielectric and active array. These topographies propagate to the top surfaces of the TMBS rectifiers which end up having similar topographies. The top surfaces of the TMBS rectifier can include layers such as nitride layers and solderable top metal (STM) layers which are prone to developing cracks when they have substantially non-planar topographies. The cracks that develop in the nitride and STM layers on the top of the TMBS rectifiers can propagate to the bottom part of the nitride and STM layers and reach the metal pad layer. These cracks can then increase the reverse leakage current in the TMBS rectifier which make the TMBS rectifier inoperable or reduce its performance.

These topographies can also reduce the effectiveness of solder connections made with the STM to the package. The topographies can reduce the integrity of the solder connection because the non-coplanar surface on the STM layer on top of the TMBS rectifier is not as conducive to soldering as a planar surface. Since these topographies reduce the integrity of the solder connection, the topographies also reduce the reliability of the TMBS rectifier because the solder connections on the STM surface having non-coplanar topography are not as reliable.

Further, variations in topographies which are created between the polysilicon gates and mesa can increase the chances of inducing plasma damage to the structure (shield dielectric). The damage is caused by plasma etching the polysilicon gates, which has a non-planar surface between the polysilicon and mesa regions. This plasma induced damage can further damage the TMBS rectifier while it is being fabricated. The non-uniform topographies can increase the chances of damage occurring during processes such as plasma etching. Non-uniform contours can cause charge build up during processes such as etching which can cause arcing and damage to the TMBS rectifier as it is being fabricated. Damages that occur during fabrication can reduce yields which can increase the cost of manufacturing TMBS rectifiers. Variations in the topography can also make it difficult to uniformly deposit onto or etch material from the surface. For example, variations in topography make it difficult to bring the entire surface of the substrate in the depth of field of photolithography systems, or selectively remove material based on position. These variations that occur during fabrication can lead to variations in the electrical performance of the TMBS rectifier.

Therefore, there is a need for cost effective fabrication processes and substrate structures that reduce variations in the topography surface between termination and active cells and assists in reducing reverse leakage current and improves solderability properties.

SUMMARY

Embodiments of the present invention provide techniques for fabricating High Efficiency Diode (HED) rectifiers that reduce variations in the topography surface between termination and active cells and assists in reducing reverse leakage current and improves solderability properties. Embodiments of the invention also provide embodiments of HED rectifiers structures made using these techniques.

In one embodiment, a method of forming a semiconductor device includes forming a field oxide region in an epitaxial layer, forming a plurality of trenches that have sidewalls and a bottom in the epitaxial layer separated by mesas, forming a shield dielectric that lines the sidewalls and bottom of the trenches and substantially covers the mesas and field oxide region, depositing polysilicon to substantially fill the plurality of trenches and substantially cover the shield dielectric, and planarizing the polysilicon using chemical mechanical planarization (CMP) to generate a substantially planar surface including substantially planar regions of polysilicon, shield dielectric, and mesa regions. The field oxide region extends into the epitaxial layer and above the epitaxial layer. The regions of polysilicon, shield dielectric and mesa regions can be formed by planarization to form a substantially flat contiguous surface.

In another embodiment, the method further includes forming a top metal layer, a dielectric layer, and a solderable top metal (STM) layer over the top metal. The tops of the dielectric layer and the STM layer are substantially coplanar. The top metal can include a Schottky contact. The top metal can be formed over a portion of a NiSi layer and over a portion of the shield dielectric layer deposited on the field oxide layer. The dielectric layer can include polyimide. The dielectric layer can also be selected from the group consisting of polyimide and deposited silicon nitride, polyimide and deposited silicon dioxide, polyimide and deposited silicon oxy-nitride, silicon nitride, silicon oxy-nitride, and silicon dioxide. A portion of the dielectric layer can be a street which is used to separate the semiconductor devices made on a single wafer.

In another embodiment of the method, forming the STM metal includes depositing Ti/NiV/Ag or Ta/Cu over the top metal.

In another embodiment, a second method of forming a semiconductor device includes forming a field oxide in an epitaxial layer, planarizing the field oxide using chemical mechanical planarization (CMP) to generate a substantially planar surface that includes substantially planar regions of field oxide and epitaxial layer, forming a plurality of trenches that have sidewalls and a bottom in the epitaxial layer separated by mesas, forming a shield dielectric that lines the sidewalls and bottom of the trenches and substantially covers the mesas and field oxide region, and depositing polysilicon to substantially fill the plurality of trenches and substantially cover the shield dielectric. The field oxide extends into the epitaxial layer and above the epitaxial layer. The polysilicon can be planarized using chemical mechanical planarization (CMP) to generate a substantially planar surface that includes substantially planar regions of polysilicon, shield dielectric, and mesas.

In yet another embodiment of the second method, forming the field oxide includes forming a pad oxide layer over a substrate, forming a nitride layer over the pad oxide layer, etching the pad oxide layer and nitride layer according to a pattern, gowning the field oxide in the pattern and recessed into the substrate, and removing the pad oxide layer and nitride layer from active areas.

In another embodiment, a third method of forming a semiconductor device includes forming a field oxide in an epitaxial layer, forming a plurality of trenches that have sidewalls and a bottom in the epitaxial layer separated by mesas, forming a shield dielectric that lines the sidewalls and bottom of the trenches and substantially covers the mesas and field oxide region, depositing polysilicon to substantially fill the plurality of trenches and substantially cover the shield dielectric, forming a top metal over the polysilicon and over a portion of the shield dielectric layer, forming a dielectric layer over a first portion of the top metal, forming a solderable top metal (STM) layer over a second portion of the top metal, and planarizing the STM layer using chemical mechanical planarization (CMP) to generate a substantially planar surface that includes substantially planar regions of the STM material and dielectric material. The field oxide extends into the epitaxial layer and above the epitaxial layer. The dielectric layer can include polyimide.

In yet another embodiment, the third method further includes planarizing the polysilicon using chemical mechanical planarization (CMP) to generate a substantially planar surface including substantially planar regions of polysilicon, shield dielectric and mesas.

In yet another embodiment, the third method further includes planarizing the field oxide using chemical mechanical planarization (CMP) to generate a substantially planar surface including substantially planar regions of field oxide and epitaxial layer, and planarizing the polysilicon using chemical mechanical planarization (CMP) to generate a substantially planar surface including substantially planar regions of polysilicon, shield dielectric and mesas.

In yet another embodiment, the third method further includes forming a nickel silicide (NiSi) layer over the plurality of trenches. The top metal can be formed over a portion of the NiSi layer and over a portion of the shield dielectric layer deposited on the field oxide layer.

In another embodiment, a semiconductor device includes an epitaxial layer, a field oxide region disposed in the epitaxial layer, a plurality of trenches that include sidewalls and a bottom disposed in the epitaxial layer, the plurality of trenches are separated by a plurality of mesas, a shield dielectric that lines the trench sidewalls and bottom of the trenches and covers the field oxide region, a polysilicon that substantially fills the plurality of trenches, and a substantially planar surface that includes substantially planar regions of polysilicon, shield dielectric and mesas. The substantially planar surface can be formed using chemical mechanical planarization (CMP). The field oxide extends into the epitaxial layer. The substantially planar surface can be contiguous with polysilicon, shield dielectric and mesas.

In yet another embodiment, the semiconductor device further includes a top metal, a dielectric layer and a solderable top metal (STM) layer disposed over the top metal. The tops of the dielectric layer and the STM layer are substantially coplanar.

In another embodiment, a second semiconductor device includes an epitaxial layer, and a field oxide region disposed in the epitaxial layer. The field oxide extends into the epitaxial layer and forms a substantially planar first surface including substantially planar regions of field oxide and epitaxial layer, a plurality of trenches including sidewalls and a bottom disposed in the epitaxial layer, the plurality of trenches separated by a plurality of mesas, a shield dielectric that lines the trench sidewalls and bottom of the trenches and covers the field oxide region, and a polysilicon that substantially fills the plurality of trenches. The first surface can be formed using chemical mechanical planarization (CMP). The top surface of the field oxide and the top surface of the epitaxial layer can form a contiguous surface.

In yet another embodiment, the second semiconductor device further includes a substantially planar second surface including substantially planar regions of polysilicon, shield dielectric and mesas, the second surface is formed using CMP.

In another embodiment, a third semiconductor device includes an epitaxial layer, a field oxide region disposed in the epitaxial layer, a plurality of trenches including sidewalls and a bottom disposed in the epitaxial layer, a shield dielectric that lines the trench sidewalls and bottom of the trenches and covers the field oxide region, a polysilicon that substantially fills the plurality of trenches, a top metal that covers a portion of the shield dielectric layer, a dielectric layer that covers a first portion of the top metal, a solderable top metal (STM) layer disposed adjacent to the dielectric layer and covering a second portion of the top metal, and a substantially planar first surface that includes substantially planar regions of the STM material and dielectric material. The substantially planar first surface can be formed using chemical mechanical planarization (CMP). The field oxide extends into the epitaxial layer. The plurality of trenches is separated by a plurality of mesas. The dielectric layer can be any dielectric materials such as polyimide, polymer dielectrics, know semiconductor dielectrics, or combinations thereof. For example, the dielectric layer can be selected from the group consisting of polyimide and deposited silicon nitride, polyimide and deposited silicon dioxide, polyimide and deposited silicon oxy-nitride, silicon nitride, silicon oxy-nitride, and silicon dioxide. The STM metal can include Ti/NiV/Ag or Ta/Cu.

In yet another embodiment, a third semiconductor device further includes a substantially planar third surface including substantially planar regions of polysilicon, shield dielectric and mesas, the substantially planar third surface formed using chemical mechanical planarization (CMP).

In yet another embodiment, a third semiconductor device further includes a substantially planar second surface including substantially planar regions of field oxide and epitaxial layer, and a substantially planar third surface including substantially planar regions of polysilicon, shield dielectric and mesas. The substantially planar second surface is formed using chemical mechanical planarization (CMP). The substantially planar third surface is formed using chemical mechanical planarization (CMP).

The embodiments described above and herein are not the only embodiments of this invention. Features found in particular embodiments described herein can be combined with other embodiments described herein. Further areas of applicability of the present disclosure will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating various embodiments, are intended for purposes of illustration only and are not intended to necessarily limit the scope of the disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

A further understanding of the nature and advantages of the invention may be realized by reference to the remaining portions of the specification and the drawings, presented below. The Figures are incorporated into the detailed description portion of the invention.

FIG. 1 illustrates a cross section of an HED rectifier with significant topography variations at the surface.

FIG. 2A is an illustration of a top view of an HED rectifier that is made to have a planar structure between edge termination to trenches and trenches to mesa regions.

FIGS. 2B-2C are expanded views of one of the HED rectifier corners showing active devices separated by streets.

FIGS. 3A-3K are simplified cross section views at various stages of a process for forming a HED rectifier, in accordance with one embodiment of the invention.

FIG. 4 is a flowchart illustrating a method of forming a semiconductor device using CMP to planarized polysilicon deposited in trenches and above an epitaxial layer of a substrate.

FIG. 5 is a flowchart illustrating a method of forming a semiconductor device using CMP to planarize an oxide layer and using CMP to planarized polysilicon deposited in trenches and above an epitaxial layer disposed on a substrate.

FIG. 6 is a flowchart illustrating a method of forming a semiconductor device using CMP to planarize an oxide layer.

FIG. 7 is a flowchart illustrating a method of forming a semiconductor device using CMP to planarize an oxide layer, using CMP to planarized polysilicon deposited in trenches and above an epitaxial layer disposed on a substrate, and using CMP to planarized a STM layer.

FIG. 8 is a flowchart illustrating a method of forming a semiconductor device using CMP to planarized polysilicon deposited in trenches and above an epitaxial layer disposed above a substrate and using CMP to planarized a STM layer.

FIG. 9 is a flowchart illustrating a method of forming a semiconductor device using CMP to planarize an oxide layer and using CMP to planarized a STM layer.

FIG. 10 is a flowchart illustrating a method of forming a semiconductor device using CMP to planarized a STM layer.

FIG. 11 illustrates a cross section view of a semiconductor device made in accordance with the methods described above with reference to FIGS. 3-10.

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details.

Embodiments of the present invention provide HED rectifiers with improved performance including reduced reverse leakage current, reliable solderability properties, and higher manufacturing yields. The improved HED rectifier has a reduce topography variation across the surface between termination and active cells which assists in reducing reverse leakage current and significantly improves solderability depending on packaging methodology. The reverse leakage current is reduced by creating a planar surface between shield dielectric, polysilicon and mesas, prior to Schottky metallization. The reduced topography variation produces a more uniform surface across the device which eliminates plasma etch damage caused by traditional contact etch methods and improves the uniformity of layers within the device. A CMP process can also be used to keep the shield electrode and dielectric intact to reduce the electric field at the top corners of the cell structure. A low stress metallic Schottky contact region is formed with the mesa that is co-planar with the shield electrode and dielectric. A recessed field oxide is produced using a LOCal Oxidation of Silicon (LOCOS) process. A chemical mechanical planarization process can be used to form the termination dielectric which provides a planar surface from street to active area. The shield polysilicon electrode is processed using CMP to produce a planarized surface across the active cell structure (shield polysilicon, shield dielectric and active silicon mesa area). The solderable metal surface can also be processed using CMP to help planarize the solderable surface.

FIG. 1 illustrates a cross section of an HED rectifier with significant topography variations at the surface that are caused by height variations between the shield dielectric layer, polysilicon gates, and field oxide layers. The HED rectifier includes a substrate 100, an epitaxial layer 102, a field oxide region 120, an implant region 125, trenches 135 shield dielectric layer 140, polysilicon 145, a nickel silicide layer (NiSi) 160, a top metal 165, a nitride layer 175, a solderable top metal (STM) layer 185, and regions 190A-190E. Region 190A is a region showing the irregularity in the nickel silicide layer (NiSi) 160, which causes reverse leakage current. The irregularities shows in the region 190A are caused by height variations between the trenches 135 and the mesas between the trenches 135. Regions 190B-190E are regions where the nitride layer 175 is prone to cracking because of the topography of the nitride layer 175 in these regions. The variations in topography on the nitride layer 175 at the surface of the HED rectifier, which are illustrated in regions 190A-190E, originated because of height variations between the field oxide layers 120, shield dielectric layer 140, and polysilicon 145 gates. These height variations between the field oxide layers 120, shield dielectric layer 140, and polysilicon 145 gates are propagated when a layer is deposited on top of these layers until the variations are manifested on the surface of the HED rectifier.

Because of its topography, region 190A can cause significant reverse leakage current in the HED rectifier, which can reduce its performance or render it inoperable. In one embodiment, the field oxide region 120 is planarized using a CMP process to generate a substantially planar surface having substantially planar regions at the top of the trenches with field oxide and epitaxial layer, which significantly reduces reverse leakage current. Further details of this CMP process are discussed with reference to FIGS. 3-10 below.

Also, because of its topography the other regions 190B-190E can develop a primary crack that can propagate to the bottom part of the nitride 175, which can increase the reverse leakage current in the HED rectifier reducing its performance or rendering it inoperable. The chances of this primary crack developing can be significantly reduced by reducing the variation in topography in region 190A. The chances of this primary crack developing can also be significantly reduced by reducing the variation in topography in regions 190B-190E. In one embodiment the variation in topography in regions 190B-190E is reduced by using CMP to planarize the field oxide layers 120, shield dielectric layer 140, and polysilicon 145 gates. Once these layers are planarized, their height variation will be significantly reduced and therefore will not propagate and manifest itself on the surface of the HED rectifier. Further details of this CMP process are discussed with reference to FIGS. 3-10 below. In another embodiment the variation in topography is reduced by using polyimide instead of nitride in layer 175, as is also discussed in further detail with reference to FIGS. 3-10 below. As an alternative to using polyimide, the following compounds can also be used: polyimide and deposited silicon nitride, polyimide and deposited silicon dioxide, polyimide and deposited silicon oxy-nitride, silicon nitride, silicon oxy-nitride, and silicon dioxide.

FIG. 2A is an illustration of a top view of a die 200 having HED rectifiers which are made to have a planar structure between edge termination to trenches and trenches to mesa regions. The HED rectifiers in die 200 have a reduced reverse leakage current caused by non-planarity. Die 200 includes diagonal opposite corners 210A-210D that have the same layout, regions 215A-215E which can include active devices, and street 220. In other embodiments, only some of the diagonal opposite corners 210A-210D have the same layout.

FIGS. 2B and 2C are expanded views of one of the corners 210A-210D showing active devices 215A-215E with street separation 220. The expanded views of the top of the die 200 include a solderable top metal (STM) 230, a dielectric opening 240, an end of the STM 245, a contact opening 250, and an aluminum under dielectric region 255. The STM layer can be a (Ti—NiV—Ag) pad with topography lines of contact and aluminum layers. In some embodiments, the Ag layer is slightly etched back from the NiV layer resulting in two topography lines. FIG. 2C shows one representative location where cross sections along lines A-A′ can be taken as illustrated in FIGS. 3A-3K.

FIGS. 3A-3K are simplified cross section views at various stages of a process for forming a HED rectifier, in accordance with one embodiment of the invention. FIGS. 3A-3K illustrate the process of forming the region of the HED rectifier identified in region A-A′ as illustrated in FIG. 2C. However, the techniques illustrated in FIGS. 3A-3K are applicable for forming HED rectifiers located in other regions of die 200. In FIGS. 3A-3K, various operations are performed on an epitaxial layer 302, which is disposed on a substrate 300, to form an HED rectifier having a planar structure between edge termination to trenches and trenches to mesa regions, which reduces reverse leakage current caused by non-planarity. Many HED rectifiers similar to that shown in FIGS. 3A-3K are typically dispersed throughout the active region of the die 200 in a predetermined frequency.

FIG. 3A, which illustrates a partially fabricated HED rectifier along the cutline A-A′, includes a substrate 300, an epitaxial layer 302, a pad oxide layer 305, a nitride layer 310, exposed photo resist coat 315A, and a field oxide region 320. The substrate 300 can be an N-type wafer which has been previously scribed with a laser to include information such as device type, lot number, and wafer number. The substrate 300 can also be a highly doped N+ substrate. The epitaxial layer 302, which is formed over the substrate 300, can be made of the same conductivity or different conductivity than the substrate 300. MOSFETs are formed when the substrate 300 and epitaxial layer 302 are of the same conductivity type, and IGBTs are formed when the substrate 300 has the opposite conductivity type to that of the epitaxial layer 302. In some embodiments, the epitaxial layer 302 is made of lightly doped n-type material. The semiconductor region is a lightly doped n-type epitaxial layer 302 formed over a highly doped substrate 300. A pad oxide layer 305 ranging from 200A to 400A is grown on the epitaxial layer 302 using an oxidation process. The epitaxial layer 302 is epitaxially grown on a substrate 300. The pad oxide layer 305 is used for adherence and stress relief for subsequently deposited layers. In some embodiments the substrate is cleaned prior to forming the pad oxide layer 305. The nitride layer 310, which ranges from 500 Å to 2000 Å, is deposited over the pad oxide layer 305. In some embodiments, the nitride layer 310 is maintained between 1000 Å to 1500 Å. The nitride layer 310 is used to protect the active area of the device during the field oxidation process. The exposed photo resist coat 315A is used for field photolithography and defines future field oxide and alignment targets. The exposed photo resist 315A is shown as exposed and developed. The field oxide region 320 is formed by first etching the nitride layer 310, and then the oxide layer 305, and may extend into the epitaxial layer 302, which will eventually become part of the field oxide region 320, stripping the masks used to perform the etching, cleaning the device and then growing the field oxide region 320 to be recessed in the silicon substrate with some of the field oxide region being above the top surface of the epitaxial layer 302.

FIG. 3B, which illustrates a further partially fabricated HED rectifier along the cutline A-A′, includes the substrate 300, an epitaxial layer 302, exposed photo resist coat 315B, the field oxide region 320 and an implant region 325. The exposed photo resist coat 315B is used for field photolithography and defining the subsequent implant regions. The exposed photo resist 315B is shown as exposed and developed. In one embodiment a chemical mechanical planarization (CMP) process is performed on the HED rectifier illustrated in FIG. 3A to planarize the field oxide to silicon mesa portions. The implant region 325 is produced by implanting boron into the regions that are not covered by the exposed photoresist 315B. In one embodiment boron is implanted using a dosage ranging from 1e13 to 1e14 ions/cm2 and an energy ranging from 40 to 200 KeV. In some embodiments, the implantation energy is increased in order to produce a P-iso under the field oxide layer 320. After the boron is implanted, the exposed photo resist 315B is removed using oxygen plasma resist strip. After the oxygen plasma strip, the HED rectifier is cleaned using combinations of H₂SO₄/H₂O₂, mega Sonics, NH₄OH, H₂O₂, and DI Water. In some embodiments, the implant regions 325 are omitted. In the embodiments where implant regions 325 are omitted, the following FIGS. 3C-3K would also have the implant regions 325 omitted.

FIG. 3C, which illustrates a further partially fabricated HED rectifier along the cutline A-A′, includes the substrate 300, an epitaxial layer 302, the field oxide region 320, an implant region 325, and a hard mask layer 330. In one embodiment a P-Iso drive is performed. The hard mask layer 330 is also grown over the substrate 300, the epitaxial layer 302, the field oxide region 320 and the implant region 325. The hard mask 330 is used later to define trench etch areas. The thickness of the hard mask 330 depends upon photo resist type and thickness used to define trench critical dimensions (CD) and depth. In one embodiment, the hard mask oxide is thermally grown. In another embodiment the hard mask oxide is deposited (i.e sputter, CVD, PVD, ALD, or combination of deposition and thermal growth). This hard mask 330 is produced with an oxidation process that may cause film thickness variations between field and active regions causing non-uniform trench dimensions in areas of trench termination (i.e. CD change of 5%).

FIG. 3D illustrates one way of forming trenches in a partially fabricated HED rectifier. FIG. 3D, which illustrates this formation, as seen along cutline A-A′ includes the substrate 300, an epitaxial layer 302, the field oxide region 320, an implant region 325, the hard mask layer 330, an exposed photoresist 315C, and trenches 335. The exposed photo resist coat 315C is used for field photolithography and defining the subsequent formed trenches 335. The exposed photo resist 315C is shown as exposed and developed. A plasma etch is used to open the hard mask layer 330 where trenches will be etched later. After the trench 335 openings are formed in the hard mask layer 330, in one embodiment the exposed photo resist 315C is removed using oxygen plasma resist strip prior to etching trenches 335. The trenches 335 are formed by etching. The etching process can involve using gaseous etchants such as, for example, SF₆/He/O₂chemistries. The depth of the trenches can range from 0.5 to 10 μm. In some embodiments, the trenches are etched to a depth of approximately 1.20 um. The etching process is selected so that the etching is selective to silicon rather than the hard mask layer 330 material.

FIG. 3E illustrates an alternative to the methods illustrated in FIGS. 3C-3D for P-iso driving and trench formation. FIG. 3E, which illustrates this formation, as seen along cutline A-A′ includes the substrate 300, the epitaxial layer 302, the field oxide region 320, an implant region 325, an exposed photoresist 315D, and trenches 335. A comparison of FIG. 3E with FIGS. 3C-3D shows that the method illustrated in FIG. 3E does not use a hard mask layer 330 which results in fewer processing steps and a potentially more planar surface between the field regions and active regions of the final HED rectifier device. The P-iso drive is performed in nitrogen at ambient pressure. Since the exposed photoresist 315D pattern will be used as an etch mask and a hard mask layer 330 is not formed, this process reduces or eliminates oxide thickness variations between field oxide region 320 and the oxide hard mask layer 330. The etching process is selected so that the etching is selective to silicon rather than the exposed photoresist 315D material.

FIG. 3F illustrates the formation of a shield dielectric layer and polysilicon in a partially fabricated HED rectifier having trenches already formed. FIG. 3F, which illustrates the formation of the shield dielectric layer and polysilicon, as seen along cutline A-A′ includes the substrate 300, the epitaxial layer 302, the field oxide region 320, an implant region 325, trenches 335 shield dielectric layer 340, and polysilicon 345. Before the shield dielectric layer 340 is deposited, the partially fabricated HED rectifier is cleaned. The cleaning process can include a hydrogen fluoride (HF) etch and second soft etch, which can clean the trenches 335 and remove residual polymer. Once the HED rectifier is cleaned, the shield dielectric layer 340, also know as the gate oxide, is formed. In some embodiments the shield dielectric layer 340 can be thermally grown, deposited using atomic layer deposition, physical vapor deposition, chemical vapor deposition, or combination thereof. In one embodiment, the shield dielectric layer 340 can have a thickness of approximately 400±50 Å. However the thickness of the shield dielectric layer 340 can range from 200 to 5000 Å, depending on the specific application. The shield dielectric layer quality and thickness determines the device capability for electric field and breakdown voltage. The shield dielectric layer 340 is deposited so that it follows the contours of the trench and the substrate. The shield dielectric layer 340 is deposited along the bottom and sidewalls of the trench 335 and along the top of the epitaxial layer 302, the field oxide region 320 and an implant region 325. In some embodiments, the shield dielectric layer 340 can form a contiguous film along the bottom and sidewalls of the trench 335 and along the top of the epitaxial layer 302, the field oxide region 320 and the implant region 325. The shield dielectric layer 340 can be formed by exposing the HED rectifier to oxygen diluted in an inert gas such as argon, helium, or xenon at high temperatures over 1000° C. The shield dielectric layer 340 can form a thick bottom oxide (TBO) in the trenches 335 to improve breakdown voltage capabilities.

After the shield dielectric layer 340 is deposited, the polysilicon 345 material is deposited inside the trench 335 and over the top of the shield dielectric layer 340. The polysilicon material which is deposited into the trenches 335 and over the shield dielectric layer 340 is amorphous undoped polysilicon and has a thickness of approximately 5500 Å±500 Å. The polysilicon material is then doped by implanting boron. In one embodiment, boron is implanted into the undoped polysilicon material using a high carrier concentration.

FIG. 3G illustrates the process of annealing the polysilicon, removing the excess polysilicon and etching recesses in a partially fabricated HED rectifier shown in FIG. 3F. FIG. 3G, which illustrates annealing the polysilicon, removing the excess polysilicon and etching recesses, as seen along cutline A-A′, includes the substrate 300, the epitaxial layer 302, the field oxide region 320, the implant region 325, trenches 335 shield dielectric layer 340, and polysilicon 345. Once the HED rectifier is cleaned, the polysilicon 345 material is annealed by heating the partial HED rectifier. The excess polysilicon 335 material is then removed using CMP. The CMP process removes the excess polysilicon 335 material disposed on top of the shield dielectric layer 340 outside of the trenches 335 with the use of a chemical slurry and abrasive grinding pad specially designed for removing polysilicon film. The CMP tool dispenses a chemical slurry mixture onto the top surface of the wafer. The grinder head, which has an abrasive pad attached to the head, is then lowered to come into contact with upper polysilicon surface and the slurry. The slight chemical etch provided by the slurry coupled with the force of the abrasive pad provided by the head causes the polysilicon to be planarized to the shield dielectric surface. The CMP process can also be used to remove some of the shield dielectric layer 340 disposed outside of the trench 335, leaving behind a thinner shield dielectric layer 340 outside of trenches 335 than inside of trenches 335. After the partial HED rectifier has been processed with CMP, the resulting partial HED rectifier has the shield dielectric layer 340 partially extending above the epitaxial layer 302, and trenches 335 with the polysilicon 345 material filling the trenches 335 up to the shield dielectric layer 340 and flush with the top of the shield dielectric layer 340.

In other embodiments, a CMP process can be used to further remove the remaining shield dielectric on the tops of the mesas. In this embodiment an end point detector can be used to determine when the polysilicon has been removed. After the polysilicon is removed the CMP process can be changed to a different CMP process to remove the shield dielectric layer. Changing to a different CMP process can include changing the slurry composition and pad abrasiveness to one which is designed to etch oxides. Once the CMP setup and process is changed the shield dielectric is removed from the mesa surface using this new CMP process. This new CMP process is stopped when silicon is exposed.

FIG. 3H, which illustrates the partially fabricated HED rectifier after having several metallic layers deposited, as seen along cutline A-A′, includes the substrate 300, the epitaxial layer 302, the field oxide region 320, the implant region 325, trenches 335 shield dielectric layer 340, and polysilicon 345, a nickel silicide layer (NiSi) 360, a top metal 365 and an opening 370. The NiSi layer 360 is formed by depositing nickel over the planarized region having exposed polysilicon 345 in the trenches 335 and exposed silicon which forms the mesas between the trenches 335. Nickel silicide (NiSi) forms when the nickel is exposed to the silicon from substrate 300 and some subsequent heat treatment ranging from 250° C. to 550° C. is applied. The un-reacted nickel is removed from the oxide areas. In some cases, the un-reacted nickel can be left behind. In some embodiments that NiSi layer can be sputter deposited and the thickness can be approximately 600 Å. In other embodiments the thickness of the NiSi layer can range from 100 Å to 1000 Å. In some embodiments the NiSi layer can be etched to clean the surface before additional steps are performed. The NiSi layer 360 can alternatively be other materials that form a Schottky layer such as platinum, cobalt, etc. The top layer 365 is formed by depositing Al/Si/Cu over the NiSi layer 360 and the shield dielectric layer 340 which has been deposited over the field oxide region 320. After the top layer 365 is formed, a portion of the top layer 365 is etched to form opening 370. In this etching process, the top layer 365 is etched down to the field oxide region 320. In some embodiments, the un-reacted nickel can also be etched at this time thus minimizing potential aluminum spiking over active cells and reducing the number of processing steps.

FIG. 3I, which illustrates the partially fabricated HED rectifier after formation of the top layer 365 with opening 370, as seen along cutline A-A′, includes the substrate 300, the epitaxial layer 302, the field oxide region 320, the implant region 325, trenches 335 shield dielectric layer 340, and polysilicon 345, a NiSi layer 360, a top metal 365, a dielectric layer 375 and a mask layer 380. The dielectric layer 375 is formed by depositing over the entire structure illustrated in FIG. 3H a dielectric material. The dielectric material can be polyimide, BCB, nitride, oxy-nitride films that act as a dielectric material, polyimide and deposited silicon nitride, polyimide and deposited silicon dioxide, polyimide and deposited silicon oxy-nitride, silicon nitride, silicon oxy-nitride, or silicon dioxide. After the dielectric material is deposited, a mask layer 380 is applied over the dielectric layer and a portion of the dielectric layer is etched leaving behind dielectric material over most of the field oxide region 320 and over a portion of the top metal but not over the trenches 335. The device can then be alloyed by subjecting the device to temperatures ranging between 350° C.-500° C. in the presence of forming gas or Hydrogen containing gas to allow any interface layer that may exist between the metal and Si or metal to metal to be consumed. This alloying forms an improved contact through interdiffusion between the silicon substrate 300, the NiSi layer 360 and the top layer 365. This alloy step can also is used to anneal out any surface states (i.e. interfaces trap at the oxide to silicon interface).

FIG. 3J illustrates the partially fabricated HED rectifier shown in FIG. 3I after forming the patterned dielectric layer 375. FIG. 3J, which illustrates the partially fabricated HED rectifier after formation of the patterned dielectric layer 375, as seen along cutline A-A′, includes the substrate 300, the epitaxial layer 302, the field oxide region 320, the implant region 325, trenches 335, shield dielectric layer 340, and polysilicon 345, a NiSi layer 360, a top metal 365, a dielectric layer 375 and a solderable top metal (STM) layer 385. Before the STM layer 385 is formed, the HED rectifier shown in FIG. 3I is cleaned to remove thin AlO₃films that may have formed. The STM layer 385 is formed by depositing a solderable material such as Ti/NiV/Ag, Ta/Cu, tin or other solderable metals. The STM layer 385 can be formed using various deposition methods such as electroless deposition. After the STM layer 385 is deposited, a pattern can be formed on top for later bonding. In some embodiments, the STM layer 385 can be further etched or processed using CMP. In some embodiments, the tops of the dielectric layer 375 and the STM layer 385 are substantially coplanar.

FIG. 3K illustrates the partially fabricated HED rectifier shown in FIG. 3J after forming the STM layer 385, as seen along cutline A-A′, and includes the substrate 300, the epitaxial layer 302, the field oxide region 320, the implant region 325, trenches 335 shield dielectric layer 340, polysilicon 345, NiSi layer 360, a top metal 365, a dielectric layer 375, an STM layer 385, and a back metal 390. Before the back layer 390 is formed, the bottom of the substrate 300 undergoes a mechanical back grinding process that grinds off a portion the substrate 300. After the grinding process, the back metal 390 is formed. The back metal 390 can include layers of Ti, NiV and Ag as well as other metals and is not limited to these specific metallic films.

FIG. 4 is a flowchart illustrating a method of forming a semiconductor device using CMP to planarized polysilicon deposited in trenches and above an epitaxial layer deposited on a substrate. The semiconductor device made using CMP to planarized the polysilicon has a planar structure between edge termination to trenches and trenches to mesa regions to reduce reverse leakage current caused by non-planarity. The method starts in operation 405 when a substrate is provided. The substrate can be N-Type wafer with an epitaxial layer deposited on top. Next in operation 440, a hard mask oxide is grown. The hard mask will be used in subsequent operations to form various features including trenches 335. In operation 445 the hard mask is patterned. In operation 450, trenches 335 are formed using an etch process. In one embodiment the trenches 335 have a pitch ranging from 0.8-1.0 um, a critical dimension ranging from 0.4-0.6 um, and a depth ranging from 0.5-5.0 um. However, in other embodiments the trenches can have values for the pitch, critical dimension, and depth which are outside of these ranges. In operation 455, the hard mask is removed. The hard mask can be removed using various techniques or combinations of techniques such as etching, wet BOE, which just removes the remaining hard mask oxide, or CMP which planarizes the field to active regions. In some embodiments, operation 455 is optional and the hard mask can be left on for future removal post polysilicon etch.

In operation 460, the shield dielectric layer 340 is formed so that it follows the contours of the trench and the substrate. The shield dielectric layer 340 can be formed by growing the oxide layer, depositing the oxide layer or combinations of growing and depositing the oxide. The shield dielectric layer 340 is formed along the bottom and sidewalls of the trench 335 and along the top of the epitaxial layer 302, and an implant region 325. The shield dielectric layer 340 can have a thickness ranging from 200 Å to 5000 Å depending on the breakdown voltage of the device. In one embodiment, the shield dielectric layer 340 can have a thickness of approximately 400±50 Å. In some embodiments, the shield dielectric layer 340 can form a contiguous film along the bottom and sidewalls of the trench 335 and along the top of the epitaxial layer 302, and the implant region 325. The shied oxide layer 340 can be formed by exposing the HED rectifier to oxygen diluted in an inert gas such as argon, helium, or xenon at elevated temperatures. In operation 465, the polysilicon 345 material is deposited inside the trench 335 and over the top of the shield dielectric layer 340. In one embodiment the polysilicon material is amorphous undoped polysilicon and has a thickness of approximately 5500 Å±500 Å. The polysilicon can be doped by several methods, such as vapor phase doping of polysilicon or implanting of dopant ions with dopant species such as boron, phosphorous, arsenic (the doping species are not limited to these examples). In another embodiment, the polysilicon could be a single crystal polysilicon. In another embodiment, the polysilicon could be insitu doped polysilicon using dopant gases during a deposition cycle. In operation 470, excess polysilicon 335 material is removed and the polysilicon to silicon mesa regions are planarized. In one embodiment, this planarization is performed using CMP. The CMP process removes the excess polysilicon 335 material disposed on top of the shield dielectric layer 340 outside of the trenches 335. The CMP process can also be used to remove some of the shield dielectric layer 340 disposed outside of the trench 335, leaving behind a thinner shield dielectric layer 340 outside of trenches 335 than inside of trenches 335. After the partial HED rectifier has been processed with CMP, the resulting partial HED rectifier has the shield dielectric layer 340 partially extending above the epitaxial layer 302 and trenches 335 with the polysilicon 345 material filling the trenches 335 up to the shield dielectric layer 340 and flush with the top of the shield dielectric layer 340. Planarizing the polysilicon using CMP generates a substantially planar surface having substantially planar regions of polysilicon and gate oxide. The regions of polysilicon and gate oxide formed by planarizing form a substantially flat contiguous surface.

Next in operation 472, a field dielectric region 320, which can be an oxide region, is formed in the epitaxial layer 302 and is recessed into the epitaxial layer 302 with some of the field dielectric region 320 being above the epitaxial layer 302 plane. In one embodiment, the field dielectric region 320 is deposited. In operation 475, a Schottky metallization layer is deposited. Next in operation 480, a Schottky barrier silicide is formed. In some embodiments, the Schottky metallization layer is omitted and operations 475 and 480 are not used. In operation 485 a top metal 365 containing aluminum is formed. The top metal 365 is formed over a Schottky metallization layer and over a portion of the gate oxide layer. In operation 490 a dielectric layer 375 and STM layer 385 are formed. The dielectric can be polyimide, PECVD oxy-nitride, PECVD nitride, BCB, oxy-nitride films that act as a dielectric material, polyimide and deposited silicon nitride, polyimide and deposited silicon dioxide, polyimide and deposited silicon oxy-nitride, silicon nitride, silicon oxy-nitride, silicon dioxide, or some other dielectric. The dielectric layer 375 is formed according to a pattern and the STM layer 385 is formed over the top metal 365. Finally, in operation 498, the HED rectifier is completed.

FIG. 5 is a flowchart illustrating a method of forming a semiconductor device using CMP to planarize a field oxide layer and using CMP to planarized polysilicon deposited in trenches and above an epitaxial layer. The semiconductor device made using CMP to planarize the field oxide layer and the polysilicon has a planar structure between edge termination to trenches and trenches to mesa regions to reduce reverse leakage current caused by non-planarity. The method starts in operation 505 when a substrate is provided. The substrate can be N-Type wafer with an epitaxial layer deposited on top. Next in operation 510 a field termination region is created using LOCOS oxidation methods. Next in operation 515 a pad oxide layer 305 is formed over the substrate using an oxidation process. The thickness of the pad oxide layer 305 can range from 200 Å to 400 Å. In operation 520, a nitride layer 310 is deposited over the pad oxide layer 305. The thickness of the nitride layer 310 ranges from 1000 Å to 1500 Å. In operation 525, a pattern is formed in the pad oxide layer 305 and nitride layer 310 using photolithography and etching. The photoresist is also removed in this operation. After the pattern is formed, in operation 530, a field oxide region 320 is formed in the epitaxial layer 302 and is recessed into the epitaxial layer 302 with some of the field oxide region 320 being above the epitaxial layer 302 plane. In operation 535, the field oxide region is planarized using a CMP etch process to generate a substantially planar surface having substantially planar regions of field oxide and epitaxial layer.

In operation 540, a hard mask oxide is deposited or grown. The hard mask will be used in subsequent operations to form various features including trenches 335. In operation 545 the hard mask is patterned. In operation 550, trenches 335 are formed using an etch process. In one embodiment the trenches 335 have a pitch ranging from 0.8-1.0 um, a critical dimension ranging from 0.4-0.6 um, and a depth ranging from 0.5-5.0 um. However, in other embodiments the trenches can have values for the pitch, critical dimension, and depth which are outside of these ranges. In operation 555, the hard mask is removed. The hard mask can be removed using various techniques or combinations of techniques such as etching, wet BOE, which just removes the remaining hard mask oxide with minimum attack to field oxide, or CMP which planarizes the field to active regions. In some embodiments, operation 555 is optional and the hard mask can be left on for future removal post polysilicon etch.

In operation 560, the shield dielectric layer 340 is formed so that it follows the contours of the trench and the substrate. The shield dielectric layer 340 can be formed by growing the oxide layer, depositing the oxide layer or combinations of growing and depositing the oxide. The shield dielectric layer 340 is formed along the bottom and sidewalls of the trench 335 and along the top of the epitaxial layer 302, the field oxide region 320 and an implant region 325. The shield dielectric layer 340 can have a thickness of approximately 400±50 Å. In some embodiments, the shield dielectric layer 340 can form a contiguous film along the bottom and sidewalls of the trench 335 and along the top of the epitaxial layer 302, the field oxide region 320 and the implant region 325. The shied oxide layer 340 can be formed by exposing the HED rectifier to oxygen diluted in an inert gas such as argon, helium, or xenon at high temperatures. In operation 565, the polysilicon 345 material is deposited inside the trench 335 and over the top of the shield dielectric layer 340. The polysilicon material is amorphous undoped polysilicon and has a thickness of approximately 5500 Å±500 Å. The polysilicon material can then be doped by implanting boron. In operation 570, excess polysilicon 335 material is removed and the polysilicon to silicon mesa regions are planarized. In one embodiment this planarization is performed using CMP. The CMP process removes the excess polysilicon 335 material disposed on top of the shield dielectric layer 340 outside of the trenches 335. The CMP process can also be used to remove some of the shield dielectric layer 340 disposed outside of the trench 335, leaving behind a thinner shield dielectric layer 340 outside of trenches 335 than inside of trenches 335. After the partial HED rectifier has been processed with CMP, the resulting partial HED rectifier has the shield dielectric layer 340 partially extending above the epitaxial layer 302 and trenches 335 with the polysilicon 345 material filling the trenches 335 up to the shield dielectric layer 340 and flush with the top of the shield dielectric layer 340. Planarizing the polysilicon using CMP generates a substantially planar surface having substantially planar regions of polysilicon, gate oxide and field oxide. The regions of polysilicon, gate oxide and field oxide formed by planarizing form a substantially flat contiguous surface. This process can be performed with or without a photo pattern.

In operation 575, a Schottky metallization layer is deposited. Next in operation 580, a Schottky barrier silicide is formed. In operation 585 a top metal 365 containing aluminum is formed. The top metal 365 is formed over a Schottky metallization layer and over a portion of the gate oxide layer. In operation 590 a dielectric layer 375 and STM layer 385 are formed. The dielectric layer 375 is formed according to a pattern and the STM layer 385 is formed over the top metal 365. In some embodiments the dielectric layer 375 is polyimide. Alternatively, the dielectric layer 375 can be PECVD oxy-nitride, PECVD nitride, BCB, oxy-nitride films that act as a dielectric material, polyimide and deposited silicon nitride, polyimide and deposited silicon dioxide, polyimide and deposited silicon oxy-nitride, silicon nitride, silicon oxy-nitride, silicon dioxide, or some other dielectric. Finally, in operation 598, the HED rectifier is completed.

FIG. 6 is a flowchart illustrating a method of forming a semiconductor device using CMP to planarize an oxide layer. The semiconductor device made using CMP to planarize the oxide layer has a planar structure between edge termination to trenches and trenches to mesa regions to reduce reverse leakage current caused by non-planarity. The method starts in operation 605 when a substrate is provided. The substrate can be an N-Type wafer with an epitaxial layer deposited on top. Next in operation 610 a field termination region is created using LOCOS oxidation methods. Next in operation 615 a pad oxide layer 305 is formed over the substrate using an oxidation process. The thickness of the pad oxide layer 305 can range from 200 Å to 400 Å. In operation 620, a nitride layer 310 is deposited over the pad oxide layer 305. The thickness of the nitride layer 310 ranges from 1000 Å to 1500 Å. In operation 625, a pattern is formed in the pad oxide layer 305 and nitride layer 310 using photolithography and etching. The photoresist is also removed in this operation. After the pattern is formed, in operation 630, a field oxide region 320 is formed in the epitaxial layer 302 and is recessed into the epitaxial layer 302 with some of the field oxide region 320 being above the epitaxial layer 302 plane. In operation 635, the field oxide region is planarized using a CMP etch process to generate a substantially planar surface having substantially planar regions of field oxide and epitaxial layer.

In operation 640, a hard mask oxide is grown. The hard mask will be used in subsequent operations to form various features including trenches 335. In operation 645 the hard mask is patterned. In operation 650, trenches 335 are formed using an etch process. In one embodiment the trenches 335 have a pitch ranging from 0.8-1.0 um, a critical dimension ranging from 0.4-0.6 um, and a depth ranging from 0.5-5.0 um. However, in other embodiments the trenches can have values for the pitch, critical dimension, and depth which are outside of these ranges. In operation 655, the hard mask is removed. The hard mask can be removed using various techniques or combinations of techniques such as etching, wet BOE, which just removes the remaining hard mask oxide with minimum attack to field oxide, or CMP which planarizes the field to active regions. In some embodiments, operation 655 is optional and the hard mask can be left on for future removal post polysilicon etch.

In operation 660, the shield dielectric layer 340 is formed so that it follows the contours of the trench and the substrate. The shield dielectric layer 340 can be formed by growing the oxide layer, depositing the oxide layer or combinations of growing and depositing the oxide. The shield dielectric layer 340 is formed along the bottom and sidewalls of the trench 335 and along the top of the epitaxial layer 302, the field oxide region 320 and an implant region 325. The shield dielectric layer 340 can have a thickness of approximately 400±50 Å. In some embodiments, the shield dielectric layer 340 can form a contiguous film along the bottom and sidewalls of the trench 335 and along the top of the epitaxial layer 302, the field oxide region 320 and the implant region 325. The shied oxide layer 340 can be formed by exposing the HED rectifier to oxygen diluted in an inert gas such as argon, helium, or xenon at high temperatures. In operation 665, the polysilicon 345 material is deposited inside the trench 335 and over the top of the shield dielectric layer 340. The polysilicon material is amorphous undoped polysilicon and has a thickness of approximately 5500 Å±500 Å. The polysilicon material can then be doped by implanting boron. In operation 670, excess polysilicon 335 material is removed. In one embodiment, the excess polysilicon 335 is removed using an Oxide/Nitride/Oxide (ONO) etch process. This process can be performed with or without a photo pattern.

In operation 675, a Schottky metallization layer is deposited. Next in operation 680, a Schottky barrier silicide is formed. In operation 685 a top metal 365 containing aluminum is formed. The top metal 365 is formed over a Schottky metallization layer and over a portion of the gate oxide layer. In operation 690 a dielectric layer 375 and STM layer 385 are formed. The dielectric layer 375 can be polyimide, PECVD oxy-nitride, PECVD nitride, BCB, oxy-nitride films that act as a dielectric material, polyimide and deposited silicon nitride, polyimide and deposited silicon dioxide, polyimide and deposited silicon oxy-nitride, silicon nitride, silicon oxy-nitride, silicon dioxide, or some other dielectric. The dielectric layer 375 is formed according to a pattern and the STM layer 385 is formed over the top metal 365. Finally, in operation 698, the HED rectifier is completed.

FIG. 7 is a flowchart illustrating a method of forming a semiconductor device using CMP to planarize a field oxide layer, using CMP to planarized polysilicon deposited in trenches and above an epitaxial layer, and using CMP to planarized a STM layer. The semiconductor device made using CMP to planarized the field oxide layer, the polysilicon and the STM layer has a planar structure between edge termination to trenches and trenches to mesa regions to reduce reverse leakage current caused by non-planarity. The method starts in operation 705 when a substrate is provided. The substrate can be an N-Type wafer with an epitaxial layer deposited on top. Next in operation 710 a field termination region is created using LOCOS oxidation methods. Next in operation 715 a pad oxide layer 305 is formed over the substrate using an oxidation process. The thickness of the pad oxide layer 305 can range from 200 Å to 400 Å. In operation 720, a nitride layer 310 is deposited over the pad oxide layer 305. The thickness of the nitride layer 310 ranges from 1000 Å to 1500 Å. In operation 725, a pattern is formed in the pad oxide layer 305 and nitride layer 310 using photolithography and etching. The photoresist is also removed in this operation. After the pattern is formed, in operation 730, a field oxide region 320 is formed in the epitaxial layer 302 and is recessed into the epitaxial layer 302 with some of the field oxide region 320 being above the epitaxial layer 302 plane. In operation 735, the field oxide region is planarized using a CMP etch process to generate a substantially planar surface having substantially planar regions of field oxide and epitaxial layer.

In operation 740, a hard mask oxide is grown. The hard mask will be used in subsequent operations to form various features including trenches 335. In operation 745 the hard mask is patterned. In operation 750, trenches 335 are formed using an etch process. In one embodiment the trenches 335 have a pitch ranging from 0.8-1.0 um, a critical dimension ranging from 0.4-0.6 um, and a depth ranging from 0.5-5.0 um. However, in other embodiments the trenches can have values for the pitch, critical dimension, and depth which are outside of these ranges. In operation 755, the hard mask is removed. The hard mask can be removed using various techniques or combinations of techniques such as etching, wet BOE, which just removes the remaining hard mask oxide with minimum attack to field oxide, or CMP which planarizes the field to active regions. In some embodiments, operation 755 is optional and the hard mask can be left on for future removal post polysilicon etch.

In operation 760, the shield dielectric layer 340 is formed so that it follows the contours of the trench and the substrate. The shield dielectric layer 340 can be formed by growing the oxide layer, depositing the oxide layer or combinations of growing and depositing the oxide. The shield dielectric layer 340 is formed along the bottom and sidewalls of the trench 335 and along the top of the epitaxial layer 302, the field oxide region 320 and an implant region 325. The shield dielectric layer 340 can have a thickness of approximately 400±50 Å. In some embodiments, the shield dielectric layer 340 can form a contiguous film along the bottom and sidewalls of the trench 335 and along the top of the epitaxial layer 302, the field oxide region 320 and the implant region 325. The shied oxide layer 340 can be formed by exposing the HED rectifier to oxygen diluted in an inert gas such as argon, helium, or xenon at high temperatures. In operation 765, the polysilicon 345 material is deposited inside the trench 335 and over the top of the shield dielectric layer 340. The polysilicon material is amorphous undoped polysilicon and has a thickness of approximately 5500 Å±500 Å. The polysilicon material can then be doped by implanting boron. In operation 770, excess polysilicon 335 material is removed and the polysilicon to silicon mesa regions are planarized. In one embodiment this planarization is performed using CMP. The CMP process removes the excess polysilicon 335 material disposed on top of the shield dielectric layer 340 outside of the trenches 335. The CMP process can also be used to remove some of the shield dielectric layer 340 disposed outside of the trench 335, leaving behind a thinner shield dielectric layer 340 outside of trenches 335 than inside of trenches 335. After the partial HED rectifier has been processed with CMP, the resulting partial HED rectifier has the shield dielectric layer 340 partially extending above the epitaxial layer 302 and trenches 335 with the polysilicon 345 material filling the trenches 335 up to the shield dielectric layer 340 and flush with the top of the shield dielectric layer 340. Planarizing the polysilicon using CMP generates a substantially planar surface having substantially planar regions of polysilicon, gate oxide and field oxide. The regions of polysilicon, gate oxide and field oxide formed by planarizing form a substantially flat contiguous surface. This process can be performed with or without a photo pattern.

In operation 775, a Schottky metallization layer is deposited. Next in operation 780, a Schottky barrier silicide is formed. In operation 785 a top metal 365 containing aluminum is formed. The top metal 365 is formed over a Schottky metallization layer and over a portion of the gate oxide layer. In operation 790 a dielectric layer 375 and STM layer 385 are formed. The dielectric layer 375 is formed according to a pattern and the STM layer 385 is formed over the top metal 365. In some embodiments the dielectric layer 375 is polyimide. Alternatively, the dielectric layer 375 can be PECVD oxy-nitride, PECVD nitride, BCB, oxy-nitride films that act as a dielectric material, polyimide and deposited silicon nitride, polyimide and deposited silicon dioxide, polyimide and deposited silicon oxy-nitride, silicon nitride, silicon oxy-nitride, silicon dioxide, or some other dielectric. In operation 795, STM layer 385 material is removed using CMP. The CMP process removes the excess STM layer 385 material disposed on top of the top metal 365 and next to the dielectric layer 375. After the partial HED rectifier has been processed with CMP, the resulting partial HED rectifier has dielectric layer 375 and the STM layer 385 substantially co-planar so that both form a flush top surface. Planarizing the STM layer 385 using CMP generates a substantially planar surface having substantially planar regions of dielectric layer 375 material and STM layer 385 material. The regions of dielectric layer 375 material and STM layer 385 material formed by planarizing form a substantially flat contiguous surface. Finally, in operation 798, the HED rectifier is completed.

FIG. 8 is a flowchart illustrating a method of forming a semiconductor device using CMP to planarize polysilicon deposited in trenches and above an epitaxial layer and using CMP to planarized a STM layer. The semiconductor device made using CMP to planarize the polysilicon and the STM layer has a planar structure between edge termination to trenches and trenches to mesa regions to reduce reverse leakage current caused by non-planarity. The method starts in operation 805 when a substrate is provided. The substrate can be an N-Type wafer with an epitaxial layer deposited on top. Next in operation 840, a hard mask oxide is grown. The hard mask will be used in subsequent operations to form various features including trenches 335. In operation 845 the hard mask is patterned. In operation 850, trenches 335 are formed using an etch process. In one embodiment the trenches 335 have a pitch ranging from 0.8-1.0 um, a critical dimension ranging from 0.4-0.6 um, and a depth ranging from 0.5-5.0 um. However, in other embodiments the trenches can have values for the pitch, critical dimension, and depth which are outside of these ranges. In operation 855, the hard mask is removed. The hard mask can be removed using various techniques or combinations of techniques such as etching, wet BOE, which just removes the remaining hard mask oxide, or CMP which planarizes the field to active regions. In some embodiments, operation 855 is optional and the hard mask can be left on for future removal post polysilicon etch.

In operation 860, the shield dielectric layer 340 is formed so that it follows the contours of the trench and the substrate. The shield dielectric layer 340 can be formed by growing the oxide layer, depositing the oxide layer or combinations of growing and depositing the oxide. The shield dielectric layer 340 is formed along the bottom and sidewalls of the trench 335 and along the top of the epitaxial layer 302, and an implant region 325. The shield dielectric layer 340 can have a thickness of approximately 400±50 Å. In some embodiments, the shield dielectric layer 340 can form a contiguous film along the bottom and sidewalls of the trench 335 and along the top of the epitaxial layer 302, and the implant region 325. The shied oxide layer 340 can be formed by exposing the HED rectifier to oxygen diluted in an inert gas such as argon, helium, or xenon at high temperatures. In operation 865, the polysilicon 345 material is deposited inside the trench 335 and over the top of the shield dielectric layer 340. The polysilicon material is amorphous undoped polysilicon and has a thickness of approximately 5500 Å±500 Å. The polysilicon material can then be doped by implanting boron. In operation 870, excess polysilicon 335 material is removed and the polysilicon to silicon mesa regions are planarized. In one embodiment this planarization is performed using CMP. The CMP process removes the excess polysilicon 335 material disposed on top of the shield dielectric layer 340 outside of the trenches 335. The CMP process can also be used to remove some of the shield dielectric layer 340 disposed outside of the trench 335, leaving behind a thinner shield dielectric layer 340 outside of trenches 335 than inside of trenches 335. After the partial HED rectifier has been processed with CMP, the resulting partial HED rectifier has the shield dielectric layer 340 partially extending above the epitaxial layer 302 and trenches 335 with the polysilicon 345 material filling the trenches 335 up to the shield dielectric layer 340 and flush with the top of the shield dielectric layer 340. Planarizing the polysilicon using CMP generates a substantially planar surface having substantially planar regions of polysilicon, and gate oxide. The regions of polysilicon and gate oxide formed by planarizing form a substantially flat contiguous surface. This process can be performed with or without a photo pattern.

Next in operation 872, a field dielectric region 320, which can be an oxide region, is formed in the epitaxial layer 302 and is recessed into the epitaxial layer 302 with some of the field dielectric region 320 being above the epitaxial layer 302 plane. In operation 875, a Schottky metallization layer is deposited. Next in operation 880, a Schottky barrier silicide is formed. In operation 885 a top metal 365 containing aluminum is formed. The top metal 365 is formed over a Schottky metallization layer and over a portion of the gate oxide layer. In operation 890 a dielectric layer 375 and STM layer 385 are formed. In some embodiments the dielectric layer 375 is polyimide. Alternatively, the dielectric layer 375 can be PECVD oxy-nitride, PECVD nitride, BCB, oxy-nitride films that act as a dielectric material, polyimide and deposited silicon nitride, polyimide and deposited silicon dioxide, polyimide and deposited silicon oxy-nitride, silicon nitride, silicon oxy-nitride, silicon dioxide, or some other dielectric. The dielectric layer 375 is formed according to a pattern and the STM layer 385 is formed over the top metal 365. In operation 895, STM layer 385 material is removed using CMP. The CMP process removes the excess STM layer 385 material disposed on top of the top metal 365 and next to the dielectric layer 375. After the partial HED rectifier has been processed with CMP, the resulting partial HED rectifier has dielectric layer 375 and the STM layer 385 substantially co-planar so that both form a flush top surface. Planarizing the STM layer 385 using CMP generates a substantially planar surface having substantially planar regions of dielectric layer 375 material and STM layer 385 material. The regions of dielectric layer 375 material and STM layer 385 material formed by planarizing form a substantially flat contiguous surface. Finally, in operation 898, the HED rectifier is completed.

FIG. 9 is a flowchart illustrating a method of forming a semiconductor device using CMP to planarize an oxide layer and using CMP to planarized a STM layer. The semiconductor device made using CMP to planarize the oxide layer and the STM layer has a planar structure between edge termination to trenches and trenches to mesa regions to reduce reverse leakage current caused by non-planarity. The method starts in operation 905 when a substrate is provided. The substrate can be an N-Type wafer with an epitaxial layer deposited on top. Next in operation 910 a field termination region is created using LOCOS oxidation methods. Next in operation 915 a pad oxide layer 305 is formed over the substrate using an oxidation process. The thickness of the pad oxide layer 305 can range from 200 Å to 400 Å. In operation 920, a nitride layer 310 is deposited over the pad oxide layer 305. The thickness of the nitride layer 310 ranges from 1000 Å to 1500 Å. In operation 925, a pattern is formed in the pad oxide layer 305 and nitride layer 310 using photolithography and etching. The photoresist is also removed in this operation. After the pattern is formed, in operation 930, a field oxide region 320 is formed in the epitaxial layer 302 and is recessed into the epitaxial layer 302 with some of the field oxide region 320 being above the epitaxial layer 302 plane. In operation 935, the field oxide region is planarized using a CMP etch process to generate a substantially planar surface having substantially planar regions of field oxide and epitaxial layer.

In operation 940, a hard mask oxide is grown. The hard mask will be used in subsequent operations to form various features including trenches 335. In operation 945 the hard mask is patterned. In operation 950, trenches 335 are formed using an etch process. In one embodiment the trenches 335 have a pitch ranging from 0.8-1.0 um, a critical dimension ranging from 0.4-0.6 um, and a depth ranging from 0.5-5.0 um. However, in other embodiments the trenches can have values for the pitch, critical dimension, and depth which are outside of these ranges. In operation 955, the hard mask is removed. The hard mask can be removed using various techniques or combinations of techniques such as etching, wet BOE, which just removes the remaining hard mask oxide with minimum attack to field oxide, or CMP which planarizes the field to active regions. In some embodiments, operation 955 is optional and the hard mask can be left on for future removal post polysilicon etch.

In operation 960, the shield dielectric layer 340 is formed so that it follows the contours of the trench and the substrate. The shield dielectric layer 340 can be formed by growing the oxide layer, depositing the oxide layer or combinations of growing and depositing the oxide. The shield dielectric layer 340 is formed along the bottom and sidewalls of the trench 335 and along the top of the epitaxial layer 302, the field oxide region 320 and an implant region 325. The shield dielectric layer 340 can have a thickness of approximately 400±50 Å. In some embodiments, the shield dielectric layer 340 can form a contiguous film along the bottom and sidewalls of the trench 335 and along the top of the epitaxial layer 302, the field oxide region 320 and the implant region 325. The shied oxide layer 340 can be formed by exposing the HED rectifier to oxygen diluted in an inert gas such as argon, helium, or xenon at high temperatures. In operation 965, the polysilicon 345 material is deposited inside the trench 335 and over the top of the shield dielectric layer 340. The polysilicon material is amorphous undoped polysilicon and has a thickness of approximately 5500 Å±500 Å. The polysilicon material can then be doped by implanting boron. In operation 970, excess polysilicon 335 material is removed. In one embodiment, the excess polysilicon 335 is removed using an ONO etch process. This process can be performed with or without a photo pattern.

In operation 975, a Schottky metallization layer is deposited. Next in operation 980, a Schottky barrier silicide is formed. In operation 985 a top metal 365 containing aluminum is formed. The top metal 365 is formed over a Schottky metallization layer and over a portion of the gate oxide layer. In operation 990 a dielectric layer 375 and STM layer 385 are formed. The dielectric layer 375 is formed according to a pattern and the STM layer 385 is formed over the top metal 365. In operation 995, STM layer 385 material is removed using CMP. The CMP process removes the excess STM layer 385 material disposed on top of the top metal 365 and next to the dielectric layer 375. After the partial HED rectifier has been processed with CMP, the resulting partial HED rectifier has dielectric layer 375 and the STM layer 385 substantially co-planar so that both form a flush top surface. Planarizing the STM layer 385 using CMP generates a substantially planar surface having substantially planar regions of dielectric layer 375 material and STM layer 385 material. The regions of dielectric layer 375 material and STM layer 385 material formed by planarizing form a substantially flat contiguous surface. In some embodiments the dielectric layer 375 is polyimide. Alternatively, the dielectric layer 375 can be PECVD oxy-nitride, PECVD nitride, BCB, oxy-nitride films that act as a dielectric material, polyimide and deposited silicon nitride, polyimide and deposited silicon dioxide, polyimide and deposited silicon oxy-nitride, silicon nitride, silicon oxy-nitride, silicon dioxide, or some other dielectric. Finally, in operation 998, the HED rectifier is completed.

FIG. 10 is a flowchart illustrating a method of forming a semiconductor device using CMP to planarized a STM layer. The semiconductor device made using CMP to planarize the STM layer has a planar structure between edge termination to trenches and trenches to mesa regions to reduce reverse leakage current caused by non-planarity. The method starts in operation 1005 when a substrate is provided. The substrate can be an N-Type wafer with an epitaxial layer deposited on top. Next in operation 1040, a hard mask oxide is grown. The hard mask will be used in subsequent operations to form various features including trenches 335. In operation 1045 the hard mask is patterned. In operation 1050, trenches 335 are formed using an etch process. In one embodiment the trenches 335 have a pitch ranging from 0.8-1.0 um, a critical dimension ranging from 0.4-0.6 um, and a depth ranging from 0.5-5.0 um. However, in other embodiments the trenches can have values for the pitch, critical dimension, and depth which are outside of these ranges. In operation 1055, the hard mask is removed. The hard mask can be removed using various techniques or combinations of techniques such as etching, wet BOE, which just removes the remaining hard mask oxide, or CMP which planarizes the field to active regions. In some embodiments, operation 1055 is optional and the hard mask can be left on for future removal post polysilicon etch.

In operation 1060, the shield dielectric layer 340 is formed so that it follows the contours of the trench and the substrate. The shield dielectric layer 340 can be formed by growing the oxide layer, depositing the oxide layer or combinations of growing and depositing the oxide. The shield dielectric layer 340 is formed along the bottom and sidewalls of the trench 335 and along the top of the epitaxial layer 302, and an implant region 325. The shield dielectric layer 340 can have a thickness of approximately 400±50 Å. In some embodiments, the shield dielectric layer 340 can form a contiguous film along the bottom and sidewalls of the trench 335 and along the top of the epitaxial layer 302, and the implant region 325. The shied oxide layer 340 can be formed by exposing the HED rectifier to oxygen diluted in an inert gas such as argon, helium, or xenon at high temperatures. In operation 1065, the polysilicon 345 material is deposited inside the trench 335 and over the top of the shield dielectric layer 340. The polysilicon material is amorphous undoped polysilicon and has a thickness of approximately 5500 Å±500 Å. The polysilicon material can then be doped by implanting boron. In operation 1070, excess polysilicon 335 material is removed. In one embodiment, the excess polysilicon 335 is removed using an ONO etch process. This process can be performed with or without a photo pattern.

Next in operation 1072, a field dielectric region 320, which can be an oxide region, is formed in the epitaxial layer 302 and is recessed into the epitaxial layer 302 with some of the field dielectric region 320 being above the epitaxial layer 302 plane. In operation 1075, a Schottky metallization layer is deposited. Next in operation 1080, a Schottky barrier silicide is formed. In operation 1085 a top metal 365 containing aluminum is formed. The top metal 365 is formed over a Schottky metallization layer and over a portion of the gate oxide layer. In operation 1090 a dielectric layer 375 and STM layer 385 are formed. In some embodiments the dielectric layer 375 is polyimide. Alternatively, the dielectric layer 375 can be PECVD oxy-nitride, PECVD nitride, BCB, oxy-nitride films that act as a dielectric material, polyimide and deposited silicon nitride, polyimide and deposited silicon dioxide, polyimide and deposited silicon oxy-nitride, silicon nitride, silicon oxy-nitride, silicon dioxide, or some other dielectric. The dielectric layer 375 is formed according to a pattern and the STM layer 385 is formed over the top metal 365. In operation 1095, STM layer 385 material is removed using CMP. The CMP process removes the excess STM layer 385 material disposed on top of the top metal 365 and next to the dielectric layer 375. After the partial HED rectifier has been processed with CMP, the resulting partial HED rectifier has dielectric layer 375 and the STM layer 385 substantially co-planar so that both form a flush top surface. Planarizing the STM layer 385 using CMP generates a substantially planar surface having substantially planar regions of dielectric layer 375 material and STM layer 385 material. The regions of dielectric layer 375 material and STM layer 385 material formed by planarizing form a substantially flat contiguous surface. Finally, in operation 1098, the HED rectifier is completed.

FIG. 11 illustrates a cross section view of a semiconductor device made along cutline A-A′ illustrated in FIG. 2C, in accordance with the methods described above with reference to FIGS. 3-10. The semiconductor device illustrated in FIG. 11 is an HED rectifier made using CMP to planarized the field oxide layer, the polysilicon and/or the STM layer. The semiconductor device has a planar structure between edge termination to trenches and trenches to mesa regions to reduce reverse leakage current caused by non-planarity. The semiconductor device includes a substrate 1100, an epitaxial layer 1102, a field oxide region 1120, an implant region 1125, trenches 1135, a shield dielectric layer 1140, polysilicon 1145, a NiSi layer 1160, a top metal 1165, a dielectric layer 1175, an STM layer 1185, and a back metal 1190. The substrate 1100 can be an N-type wafer which has been previously scribed with a laser to include information such as device type, lot number, and wafer number. The substrate 1100 can also be a highly doped N+ substrate. The epitaxial layer 1102, which is formed over the substrate 1100, can be made of the same conductivity or different conductivity than the substrate 1100. MOSFETs are formed when the substrate 1100 and epitaxial layer 1102 are of the same conductivity type, and IGBTs are formed when the substrate 1100 has the opposite conductivity type to that of the epitaxial layer 1102. In some embodiments, the epitaxial layer 1102 is made of lightly doped n-type material. The field oxide region 1120 extends into the epitaxial layer 1102 and has a top surface that is coplanar with a top surface of the epitaxial layer 1102. In some embodiments this coplanar surface is produced using CMP.

The implant region 1125 is produced by implanting boron into the epitaxial layer 1102. In some embodiments, the implantation energy is increased in order to produce a P-iso under the field oxide layer 1120. The trenches 1135 are formed by etching and have a final thickness that ranges from about 2250 Å to about 2450 Å and the final depth that ranges from about 1275 nm to about 1555 nm. The width and depth of the trenches can vary outside of these ranges. In one embodiment the depth of the trenches is approximately 1415 nm. The shield dielectric layer 1140 can have a thickness of approximately 400±50 Å and follows the contours of the trench and the substrate. The shield dielectric layer 1140 is grown so that it lines the bottom and sidewalls of the trench 1135 and along the top of the epitaxial layer 1102, the field oxide region 1120 and an implant region 1125. In some embodiments, the shield dielectric layer 1140 can form a contiguous film along the bottom and sidewalls of the trench 1135 and along the top of the epitaxial layer 1102, the field oxide region 1120 and the implant region 1125. The polysilicon material 1145 which is deposited into the trenches 1135 and over the shield dielectric layer 1140 is amorphous undoped polysilicon and has a thickness of approximately 5500 Å±500 Å. The polysilicon material 1145 is then doped by implanting boron. The polysilicon material 1145 substantially fills the trenches 1135 and produces a structure where the polysilicon material 1145 has a top surface that is coplanar with top surfaces of the gate oxide and/or the field oxide 1120. In some embodiments this coplanar surface is produced using CMP.

The NiSi layer 1160 is formed by first depositing nickel over the planarized region having exposed polysilicon 1145 in the trenches 1135 and exposed silicon which form the mesas between the trenches 1135, and then subjecting the nickel to external heat generated by sources such as rapid thermal anneal (RTA), hot chuck, and furnace sources (other heat sources can be used and the heat sources are not limited to these). NiSi forms when the nickel is exposed to the silicon from substrate 1100 and is subjected to external heat generated by sources such as rapid thermal anneal (RTA), hot chuck, and furnace sources (other heat sources can be used and the heat sources are not limited to these). In some embodiments un-reacted residual nickel is present. In some embodiments that Nickel layer can be sputter deposited and the thickness can be approximately 600 Å. The top layer 1165 is made of Al/Si/Cu, which is formed over the NiSi layer 1160 and the shield dielectric layer 1140, which has been deposited over the field oxide region 1120. The top layer 1165 includes an opening which is filled with dielectric layer 1175. In one embodiment, the dielectric layer 1175 is polyimide. Alternatively, the dielectric layer 1175 can be PECVD oxy-nitride, PECVD nitride, BCB, oxy-nitride films that act as a dielectric material, polyimide and deposited silicon nitride, polyimide and deposited silicon dioxide, polyimide and deposited silicon oxy-nitride, silicon nitride, silicon oxy-nitride, silicon dioxide, or some other dielectric. The dielectric layer 1175 is deposited over a portion of the top layer 1165 and fills the opening. The STM layer 1185 is made of a solderable material such as Ti/NiV/Ag, Ta/Cu, tin or other solderable metals. The STM layer 1185 can be formed using various deposition methods such as electroless deposition. The dielectric layer 1175 and the STM layer 1185 form a substantially planar surface which can be produced using CMP. The back metal 1190 is formed on the back side of the substrate 1100. The back metal 1190 can include layers of Ti, NiV and Ag or other solderable metals, which are formed on the back of the substrate 1100 after the back of the substrate 1100 has undergone a mechanical back grinding process that grinds off a portion the substrate 1100.

Although specific embodiments of the invention have been described, various modifications, alterations, alternative constructions, and equivalents are also encompassed within the scope of the invention. The described invention is not restricted to operation within certain specific embodiments, but is free to operate within other embodiments configurations as it should be apparent to those skilled in the art that the scope of the present invention is not limited to the described series of transactions and steps.

The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that additions, subtractions, deletions, and other modifications and changes may be made thereunto without departing from the broader spirit and scope of the invention as set forth in the claims.

Claims

1. A semiconductor device comprising: an epitaxial layer;a field oxide disposed in the epitaxial layer, the field oxide extending into the epitaxial layer;a first trench having a sidewall and disposed in the epitaxial layer;a second trench having a sidewall and disposed in the epitaxial layer;a mesa disposed between the first trench and the second trench, the mesa having a top surface substantially coplanar with a top surface of the field oxide;a shield dielectric having a first portion lining the sidewall of the first trench and having a second portion covering at least a portion of the top surface of the field oxide;a polysilicon disposed in the first trench; anda substantially planar surface including the top surface of the polysilicon, a bottom surface of the second portion of the shield dielectric, and the top surface of the mesa.
2. The semiconductor device of claim 1 wherein the substantially planar surface is formed using chemical mechanical planarization (CMP).
3. The semiconductor device of claim 1, wherein the substantially planar surface is contiguous with the top surface of the polysilicon, the second portion of the shield dielectric, and the top surface of the mesa.
4. The semiconductor device of claim 1, further comprising: a top metal; anda dielectric layer and a solderable top metal layer disposed over the top metal,the dielectric layer having a top surface substantially coplanar with a top surface of the solderable top metal layer.
5. The semiconductor device of claim 4, wherein the dielectric layer includes polyimide.
6. The semiconductor device of claim 1, further comprising: a silicide layer disposed on at least a portion of the epitaxial layer, the substantially planar surface being in contact with a substantially planar bottom surface of the silicide layer;a top metal disposed above the silicide layer; anda solderable top metal layer disposed above the top metal, the solderable top metal layer being electrically coupled to the polysilicon via the top metal and the silicide layer.
7. The semiconductor device of claim 1, further comprising: a silicide layer disposed on at least a portion of the epitaxial layer, the substantially planar surface being in contact with a substantially planar bottom surface of the silicide layer.
8. A semiconductor device comprising: an epitaxial layer;a field oxide disposed in the epitaxial layer;a trench having a sidewall and disposed in the epitaxial layer;a mesa disposed between the trench and the field oxide;a dielectric having a first portion lining the sidewall of the trench and having a second portion covering at least a portion of a top surface of the field oxide;a polysilicon disposed in the trench; anda substantially planar surface including a top surface of the polysilicon, a top surface of the dielectric, a top surface of the mesa, and a top surface of the field oxide.
9. The semiconductor device of claim 8, further comprising: a top metal having a portion disposed on the second portion of the dielectric; anda dielectric layer and a solderable top metal layer disposed over at least a portion of the top metal, the dielectric layer having a top surface substantially coplanar with a top surface of the solderable top metal layer.
10. The semiconductor device of claim 8, wherein the substantially planar surface is formed using chemical mechanical planarization (CMP).
11. The semiconductor device of claim 8, further comprising: a silicide layer disposed on at least a portion of the epitaxial layer, the substantially planar surface being in contact with a substantially planar bottom surface of the silicide layer.
12. The semiconductor device of claim 8, further comprising: a silicide layer disposed on at least a portion of the epitaxial layer, the silicide layer and the epitaxial layer form at least a portion of a Schottky rectifier.
13. The semiconductor device of claim 8, further comprising: a silicide layer disposed on at least a portion of the epitaxial layer and at least a portion of the polysilicon, the substantially planar surface being in contact with a substantially planar bottom surface of the silicide layer;a top metal disposed above the silicide layer; anda solderable top metal layer disposed above the top metal, the solderable top metal layer being electrically coupled to the polysilicon via the top metal and the silicide layer.
14. A semiconductor device comprising: an epitaxial layer;a field oxide disposed in the epitaxial layer;a trench having a sidewall and disposed in the epitaxial layer;a mesa disposed between the trench and the field oxide;a first dielectric lining the sidewall of the trench;a second dielectric disposed on at least a portion of the field oxide;a polysilicon disposed in the trench; anda substantially planar surface including a top surface of the polysilicon, a top surface of the first dielectric, a bottom surface of the second dielectric, and a top surface of the mesa.
15. The semiconductor device of claim 14, further comprising: a top metal having a portion disposed on the second dielectric; anda dielectric layer and a solderable top metal layer disposed over at least a portion of the top metal, the dielectric layer having a top surface substantially coplanar with a top surface of the solderable top metal layer.
16. The semiconductor device of claim 14, wherein the substantially planar surface is formed using chemical mechanical planarization (CMP).
17. The semiconductor device of claim 14, wherein the substantially planar surface is contiguous with the top surface of the polysilicon, the second dielectric, and the top surface of the mesa.
18. The semiconductor device of claim 14, further comprising: a silicide layer disposed on at least a portion of the epitaxial layer, the substantially planar surface being in contact with a substantially planar bottom surface of the silicide layer.
19. The semiconductor device of claim 14, further comprising: a silicide layer disposed on at least a portion of the epitaxial layer, the silicide layer and the epitaxial layer form at least a portion of a Schottky rectifier.
20. The semiconductor device of claim 14, further comprising: a silicide layer disposed on at least a portion of the epitaxial layer and at least a portion of the polysilicon, the substantially planar surface being in contact with a substantially planar bottom surface of the silicide layer;a top metal disposed above the silicide layer; anda solderable top metal layer disposed above the top metal, the solderable top metal layer being electrically coupled to the polysilicon via the top metal and the silicide layer.

US Referenced Citations (374)

Number	Name	Date	Kind
3404295	Warner et al.	Oct 1968	A
3412297	Amlinger	Nov 1968	A
3497777	Teszner et al.	Feb 1970	A
3564356	Wilson	Feb 1971	A
3660697	Berglund et al.	May 1972	A
3855009	Lloyd et al.	Dec 1974	A
4003072	Matsushita et al.	Jan 1977	A
4011105	Paivinen et al.	Mar 1977	A
4062747	Chang et al.	Dec 1977	A
4300150	Colak	Nov 1981	A
4324038	Chang et al.	Apr 1982	A
4326332	Kenney et al.	Apr 1982	A
4337474	Yukimoto	Jun 1982	A
4345265	Blanchard	Aug 1982	A
4445202	Goetze et al.	Apr 1984	A
4541001	Schutten et al.	Sep 1985	A
4568958	Baliga	Feb 1986	A
4579621	Hine	Apr 1986	A
4621414	Iranmanesh	Nov 1986	A
4636281	Buiguez et al.	Jan 1987	A
4638344	Cardwell, Jr.	Jan 1987	A
4639761	Singer et al.	Jan 1987	A
4641174	Baliga	Feb 1987	A
4666556	Fulton et al.	May 1987	A
4698653	Cardwell, Jr.	Oct 1987	A
4716126	Cogan	Dec 1987	A
4745079	Pfiester	May 1988	A
4746630	Hui et al.	May 1988	A
4754310	Coe	Jun 1988	A
4767722	Blanchard	Aug 1988	A
4774556	Fujii et al.	Sep 1988	A
4801986	Chang et al.	Jan 1989	A
4821095	Temple	Apr 1989	A
4823176	Baliga et al.	Apr 1989	A
4824793	Richardson et al.	Apr 1989	A
4833516	Hwang et al.	May 1989	A
4853345	Himelick	Aug 1989	A
4868624	Grung et al.	Sep 1989	A
4893160	Blanchard	Jan 1990	A
4914058	Blanchard	Apr 1990	A
4941026	Temple	Jul 1990	A
4961100	Baliga et al.	Oct 1990	A
4967245	Cogan et al.	Oct 1990	A
4969028	Baliga	Nov 1990	A
4974059	Kinzer	Nov 1990	A
4975782	Bauer	Dec 1990	A
4979004	Esquivel et al.	Dec 1990	A
4990463	Mori	Feb 1991	A
4992390	Chang	Feb 1991	A
5027180	Nishizawa et al.	Jun 1991	A
5032888	Seki	Jul 1991	A
5034785	Blanchard	Jul 1991	A
5065273	Rajeevakumar	Nov 1991	A
5071782	Mori	Dec 1991	A
5072266	Bulucea et al.	Dec 1991	A
5079608	Wodarczyk et al.	Jan 1992	A
5105243	Nakagawa et al.	Apr 1992	A
5111253	Korman et al.	May 1992	A
5134448	Johnsen et al.	Jul 1992	A
5142640	Iwamatsu	Aug 1992	A
5155059	Hieda	Oct 1992	A
5156989	Williams et al.	Oct 1992	A
5164325	Cogan et al.	Nov 1992	A
5164802	Jones et al.	Nov 1992	A
5168331	Yilmaz et al.	Dec 1992	A
5188973	Omura et al.	Feb 1993	A
5208657	Chatterjee et al.	May 1993	A
5216275	Chen	Jun 1993	A
5219777	Kang	Jun 1993	A
5219793	Cooper et al.	Jun 1993	A
5233215	Baliga	Aug 1993	A
5241195	Tu et al.	Aug 1993	A
5242845	Baba et al.	Sep 1993	A
5250450	Lee et al.	Oct 1993	A
5262336	Pike, Jr. et al.	Nov 1993	A
5268311	Euen et al.	Dec 1993	A
5275961	Smayling et al.	Jan 1994	A
5275965	Manning	Jan 1994	A
5281548	Prall	Jan 1994	A
5283201	Tsang et al.	Feb 1994	A
5294824	Okada	Mar 1994	A
5298781	Cogan et al.	Mar 1994	A
5300447	Anderson	Apr 1994	A
5300452	Chang et al.	Apr 1994	A
5326711	Malhi	Jul 1994	A
5346834	Hisamoto et al.	Sep 1994	A
5350937	Yamazaki et al.	Sep 1994	A
5363327	Henkles et al.	Nov 1994	A
5365102	Mehrotra et al.	Nov 1994	A
5366914	Takahashi et al.	Nov 1994	A
5389815	Takahashi	Feb 1995	A
5405794	Kim	Apr 1995	A
5418376	Muraoka et al.	May 1995	A
5424231	Yang	Jun 1995	A
5429977	Lu et al.	Jul 1995	A
5430311	Murakami et al.	Jul 1995	A
5430324	Bencuya	Jul 1995	A
5434435	Baliga	Jul 1995	A
5436189	Beasom	Jul 1995	A
5438007	Vinal et al.	Aug 1995	A
5438215	Tihanyi	Aug 1995	A
5442214	Yang	Aug 1995	A
5473176	Kakumoto	Dec 1995	A
5473180	Ludikhuize	Dec 1995	A
5474943	Hshieh et al.	Dec 1995	A
5488010	Wong	Jan 1996	A
5519245	Tokura et al.	May 1996	A
5532179	Chang et al.	Jul 1996	A
5541425	Nishihara	Jul 1996	A
5554552	Chi	Sep 1996	A
5554862	Omura et al.	Sep 1996	A
5567634	Hebert et al.	Oct 1996	A
5567635	Acovic et al.	Oct 1996	A
5572048	Sugawara	Nov 1996	A
5576245	Cogan et al.	Nov 1996	A
5578851	Hshieh et al.	Nov 1996	A
5581100	Ajit	Dec 1996	A
5583065	Miwa	Dec 1996	A
5592005	Floyd et al.	Jan 1997	A
5593909	Han et al.	Jan 1997	A
5595927	Chen et al.	Jan 1997	A
5597765	Yilmaz et al.	Jan 1997	A
5605852	Bencuya	Feb 1997	A
5616945	Williams	Apr 1997	A
5623152	Majumdar et al.	Apr 1997	A
5629543	Hshieh et al.	May 1997	A
5637898	Baliga	Jun 1997	A
5639676	Hshieh et al.	Jun 1997	A
5640034	Malhi	Jun 1997	A
5648670	Blanchard	Jul 1997	A
5656843	Goodyear et al.	Aug 1997	A
5665619	Kwan et al.	Sep 1997	A
5668394	Lur et al.	Sep 1997	A
5670803	Beilstein, Jr. et al.	Sep 1997	A
5679966	Baliga et al.	Oct 1997	A
5684320	Kawashima	Nov 1997	A
5691553	Mori et al.	Nov 1997	A
5693569	Ueno	Dec 1997	A
5705409	Witek	Jan 1998	A
5710072	Krautschneider et al.	Jan 1998	A
5714781	Yamamoto et al.	Feb 1998	A
5719409	Singh et al.	Feb 1998	A
5723891	Malhi	Mar 1998	A
5731626	Eaglesham et al.	Mar 1998	A
5744372	Bulucea	Apr 1998	A
5767004	Balasubramanian et al.	Jun 1998	A
5770878	Beasom	Jun 1998	A
5773851	Nakamura et al.	Jun 1998	A
5776813	Huang et al.	Jul 1998	A
5780343	Bashir	Jul 1998	A
5801417	Tsang et al.	Sep 1998	A
5814858	Williams	Sep 1998	A
5821583	Hshieh et al.	Oct 1998	A
5856692	Williams et al.	Jan 1999	A
5877528	So	Mar 1999	A
5879971	Witek	Mar 1999	A
5879994	Kwan et al.	Mar 1999	A
5894157	Han et al.	Apr 1999	A
5895951	So et al.	Apr 1999	A
5895952	Darwish et al.	Apr 1999	A
5897343	Mathew et al.	Apr 1999	A
5897360	Kawaguchi	Apr 1999	A
5900663	Johnson et al.	May 1999	A
5906680	Meyerson	May 1999	A
5907776	Hshieh et al.	May 1999	A
5917216	Floyd et al.	Jun 1999	A
5929481	Hshieh et al.	Jul 1999	A
5943581	Lu et al.	Aug 1999	A
5949104	D'Anna et al.	Sep 1999	A
5949124	Hadizad et al.	Sep 1999	A
5959324	Kohyama	Sep 1999	A
5960271	Wollesen et al.	Sep 1999	A
5972741	Kubo et al.	Oct 1999	A
5973360	Tihanyi	Oct 1999	A
5973367	Williams	Oct 1999	A
5976936	Miyajima et al.	Nov 1999	A
5981344	Hshieh et al.	Nov 1999	A
5981996	Fujishima	Nov 1999	A
5998833	Baliga	Dec 1999	A
6005271	Hshieh	Dec 1999	A
6008097	Yoon et al.	Dec 1999	A
6011298	Blanchard	Jan 2000	A
6015727	Wanlass	Jan 2000	A
6020250	Kenney et al.	Feb 2000	A
6034415	Johnson et al.	Mar 2000	A
6037202	Witek	Mar 2000	A
6037628	Huang	Mar 2000	A
6037632	Omura et al.	Mar 2000	A
6040600	Uenishi et al.	Mar 2000	A
6048772	D'Anna	Apr 2000	A
6049108	Williams et al.	Apr 2000	A
6051488	Lee et al.	Apr 2000	A
6057558	Yamamoto et al.	May 2000	A
6063678	D'Anna	May 2000	A
6064088	D'Anna	May 2000	A
6066878	Neilson	May 2000	A
6069043	Floyd et al.	May 2000	A
6077733	Chen et al.	Jun 2000	A
6078090	Williams et al.	Jun 2000	A
6081009	Neilson	Jun 2000	A
6084264	Darwish	Jul 2000	A
6084268	de Fresart et al.	Jul 2000	A
6087232	Kim et al.	Jul 2000	A
6096608	Williams	Aug 2000	A
6097063	Fujihira	Aug 2000	A
6103578	Uenishi et al.	Aug 2000	A
6103619	Lai	Aug 2000	A
6104054	Corsi et al.	Aug 2000	A
6110799	Huang	Aug 2000	A
6114727	Ogura et al.	Sep 2000	A
6137152	Wu	Oct 2000	A
6144054	Agahi et al.	Nov 2000	A
6150697	Teshigahara et al.	Nov 2000	A
6153920	Gossmann et al.	Nov 2000	A
6156606	Michaelis	Dec 2000	A
6156611	Lan et al.	Dec 2000	A
6163052	Liu et al.	Dec 2000	A
6165870	Shim et al.	Dec 2000	A
6168983	Rumennik et al.	Jan 2001	B1
6168996	Numazawa et al.	Jan 2001	B1
6171935	Nance et al.	Jan 2001	B1
6174769	Lou	Jan 2001	B1
6174773	Fujishima	Jan 2001	B1
6174785	Parekh et al.	Jan 2001	B1
6184545	Werner et al.	Feb 2001	B1
6184555	Tihanyi et al.	Feb 2001	B1
6188104	Choi et al.	Feb 2001	B1
6188105	Kocon et al.	Feb 2001	B1
6190978	D'Anna	Feb 2001	B1
6191447	Baliga	Feb 2001	B1
6194741	Kinzer et al.	Feb 2001	B1
6198127	Kocon	Mar 2001	B1
6201279	Pfirsch	Mar 2001	B1
6204097	Shen et al.	Mar 2001	B1
6207994	Rumennik et al.	Mar 2001	B1
6222229	Hebert et al.	Apr 2001	B1
6222233	D'Anna	Apr 2001	B1
6225649	Minato	May 2001	B1
6228727	Lim et al.	May 2001	B1
6236099	Boden, Jr.	May 2001	B1
6239463	Williams et al.	May 2001	B1
6239464	Tsuchitani et al.	May 2001	B1
6265269	Chen et al.	Jul 2001	B1
6271082	Hou et al.	Aug 2001	B1
6271100	Ballantine et al.	Aug 2001	B1
6271552	D'Anna	Aug 2001	B1
6271562	Deboy et al.	Aug 2001	B1
6274904	Tihanyi	Aug 2001	B1
6274905	Mo	Aug 2001	B1
6277706	Ishikawa	Aug 2001	B1
6281547	So et al.	Aug 2001	B1
6285060	Korec et al.	Sep 2001	B1
6291298	Williams et al.	Sep 2001	B1
6291856	Miyasaka et al.	Sep 2001	B1
6294818	Fujihira	Sep 2001	B1
6297534	Kawaguchi et al.	Oct 2001	B1
6303969	Tan	Oct 2001	B1
6307246	Nitta et al.	Oct 2001	B1
6309920	Laska et al.	Oct 2001	B1
6313482	Baliga	Nov 2001	B1
6316806	Mo	Nov 2001	B1
6326656	Tihanyi	Dec 2001	B1
6337499	Werner	Jan 2002	B1
6346464	Takeda et al.	Feb 2002	B1
6346469	Greer	Feb 2002	B1
6351018	Sapp	Feb 2002	B1
6353252	Yasuhara et al.	Mar 2002	B1
6359308	Hijzen et al.	Mar 2002	B1
6362112	Hamerski	Mar 2002	B1
6362505	Tihanyi	Mar 2002	B1
6365462	Baliga	Apr 2002	B2
6365930	Schillaci et al.	Apr 2002	B1
6368920	Beasom	Apr 2002	B1
6368921	Hijzen et al.	Apr 2002	B1
6376314	Jerred	Apr 2002	B1
6376315	Hshieh et al.	Apr 2002	B1
6376878	Kocon	Apr 2002	B1
6376890	Tihanyi	Apr 2002	B1
6384456	Tihanyi	May 2002	B1
6388286	Baliga	May 2002	B1
6388287	Deboy et al.	May 2002	B2
6400003	Huang	Jun 2002	B1
6429481	Mo et al.	Aug 2002	B1
6433385	Kocon et al.	Aug 2002	B1
6436779	Hurkx et al.	Aug 2002	B2
6437399	Huang	Aug 2002	B1
6441454	Hijzen et al.	Aug 2002	B2
6444574	Chu	Sep 2002	B1
6452230	Boden, Jr.	Sep 2002	B1
6461918	Calafut	Oct 2002	B1
6465304	Blanchard et al.	Oct 2002	B1
6465843	Hirler et al.	Oct 2002	B1
6465869	Ahlers et al.	Oct 2002	B2
6472678	Hshieh et al.	Oct 2002	B1
6472708	Hshieh et al.	Oct 2002	B1
6475884	Hshieh et al.	Nov 2002	B2
6476443	Kinzer	Nov 2002	B1
6479352	Blanchard	Nov 2002	B2
6489652	Jeon et al.	Dec 2002	B1
6498061	Divakaruni et al.	Dec 2002	B2
6501129	Osawa	Dec 2002	B2
6501146	Harada	Dec 2002	B1
6534825	Calafut	Mar 2003	B2
6566804	Trujillo et al.	May 2003	B1
6580123	Thapar	Jun 2003	B2
6593620	Hshieh et al.	Jul 2003	B1
6608350	Kinzer et al.	Aug 2003	B2
6621121	Baliga	Sep 2003	B2
6657254	Hshieh et al.	Dec 2003	B2
6667515	Inoue	Dec 2003	B2
6677641	Kocon	Jan 2004	B2
6683346	Zeng	Jan 2004	B2
6710403	Sapp	Mar 2004	B2
6720616	Hirler et al.	Apr 2004	B2
6734066	Lin et al.	May 2004	B2
6750508	Omura et al.	Jun 2004	B2
6762127	Boiteux et al.	Jul 2004	B2
6780714	Gajda et al.	Aug 2004	B2
6806533	Henninger et al.	Oct 2004	B2
6833584	Henninger et al.	Dec 2004	B2
6838722	Bhalla et al.	Jan 2005	B2
6841825	Kurosaki et al.	Jan 2005	B2
6870220	Kocon et al.	Mar 2005	B2
6916745	Herrick et al.	Jul 2005	B2
6936890	Hueting et al.	Aug 2005	B2
6979874	Harada	Dec 2005	B2
7005347	Bhalla et al.	Feb 2006	B1
7180152	Herman	Feb 2007	B2
7345342	Challa et al.	Mar 2008	B2
7416948	Kraft et al.	Aug 2008	B2
7482205	Herman	Jan 2009	B2
7638841	Challa	Dec 2009	B2
7652326	Kocon	Jan 2010	B2
20010023961	Hshieh et al.	Sep 2001	A1
20010026989	Thapar	Oct 2001	A1
20010028083	Onishi et al.	Oct 2001	A1
20010032998	Iwamoto et al.	Oct 2001	A1
20010041400	Ren et al.	Nov 2001	A1
20010049167	Madson	Dec 2001	A1
20010050394	Onishi et al.	Dec 2001	A1
20020008284	Zeng	Jan 2002	A1
20020009832	Blanchard	Jan 2002	A1
20020014658	Blanchard	Feb 2002	A1
20020066924	Blanchard	Jun 2002	A1
20020070418	Kinzer et al.	Jun 2002	A1
20020100933	Marchant	Aug 2002	A1
20020155685	Sakakibara	Oct 2002	A1
20030006452	Challa	Jan 2003	A1
20030060013	Marchant	Mar 2003	A1
20030073287	Kocon	Apr 2003	A1
20030132450	Minato et al.	Jul 2003	A1
20030178676	Henninger et al.	Sep 2003	A1
20030178678	Wei et al.	Sep 2003	A1
20030193067	Kim	Oct 2003	A1
20030197220	Disney	Oct 2003	A1
20030209757	Henninger et al.	Nov 2003	A1
20040031987	Henninger et al.	Feb 2004	A1
20040089910	Hirler et al.	May 2004	A1
20040121572	Darwish et al.	Jun 2004	A1
20040232407	Calafut	Nov 2004	A1
20050009277	Chuang et al.	Jan 2005	A1
20050017293	Zundel et al.	Jan 2005	A1
20080135889	Session	Jun 2008	A1
20080135931	Challa et al.	Jun 2008	A1
20080138953	Challa et al.	Jun 2008	A1
20080150020	Challa et al.	Jun 2008	A1
20080169505	Hsieh	Jul 2008	A1
20080185730	Lung	Aug 2008	A1
20080197407	Challa et al.	Aug 2008	A1
20080199997	Grebs et al.	Aug 2008	A1
20090008706	Yedinak et al.	Jan 2009	A1
20090008709	Yedinak et al.	Jan 2009	A1
20090111227	Kocon et al.	Apr 2009	A1
20100084706	Kocon	Apr 2010	A1

Foreign Referenced Citations (52)

Number	Date	Country
1036666	Oct 1989	CN
4300806 CI	Dec 1993	DE
19736981	Aug 1998	DE
0975024	Jan 2000	EP
1026749	Aug 2000	EP
1054451	Nov 2000	EP
20031168455	Jan 2002	EP
0747967	Feb 2002	EP
1205980	May 2002	EP
20031369927	Dec 2003	EP
56-058267	May 1981	JP
62-069562	May 1981	JP
63-186475	Mar 1987	JP
63-288047	Aug 1988	JP
63-224260	Sep 1988	JP
64-059868	Mar 1989	JP
01-192174	Aug 1989	JP
03024765	Feb 1991	JP
08186258	Jul 1996	JP
08-264772	Oct 1996	JP
64-022051	Nov 1998	JP
2000-012842	Jan 2000	JP
2000-040822	Feb 2000	JP
2000-040872	Feb 2000	JP
2000-156978	Feb 2000	JP
2000-277726	Oct 2000	JP
2000-277728	Oct 2000	JP
2001-015448	Jan 2001	JP
2001-015752	Jan 2001	JP
2001-102577	Apr 2001	JP
2001-111041	Apr 2001	JP
2001-135819	May 2001	JP
2001-144292	May 2001	JP
2001-244461	Sep 2001	JP
2001-313391	Sep 2001	JP
2002-083976	Mar 2002	JP
224372	Nov 2004	TW
WO0033386	Jun 2000	WO
WO00042665	Jul 2000	WO
WO0068997	Nov 2000	WO
WO0068998	Nov 2000	WO
WO0075965	Dec 2000	WO
WO0106550	Jan 2001	WO
WO0106557	Jan 2001	WO
WO0145155	Jun 2001	WO
WO0159847	Aug 2001	WO
WO0171815	Sep 2001	WO
WO0195385	Dec 2001	WO
WO0195398	Dec 2001	WO
WO0201644	Jan 2002	WO
WO0247171	Jun 2002	WO
WO03023861	Mar 2003	WO

Non-Patent Literature Citations (46)

Entry
“CoolMOS.TM. the second generation,” Infineon Technologies product information (2000), 2 pages total.
“IR develops CoolMOS.TM.—equivalent technology, positions it at the top of a 3-tiered line of new products for SMPS,” International Rectifiers company information available at http://www.irf.com (1999), 3 pages total.
Bai et al., “Novel automated optimization of power MOSFET for 12V input, high-frequency DC-DC converter,” International Symposium on Power Semiconductors and ICs, Technical Digest, (2003), pp. 366-369.
Baliga “New Concepts in Power Rectifiers,” Physics of Semiconductor Devices, Proceedings of the Third Int'l Workshop, Madras (India), Committee on Science and Technology in Developing Countries(1985). pp. 471-481.
Baliga “Options for CVD of Dielectrics Include Low-k Materials,” Technical Literature from Semiconductor International Jun. 1998., 4 pages total.
Baliga et al., “Improving the reverse recovery of power MOSFET integral diodes by electron irradiation,” (Dec. 1983) Solid State Electronics, vol. 26, No. 12, pp. 1133-1141.
Brown et al. Novel Trench Gate Structure Developments Set the Benchmark for Next Generation Power MOSFET Switching Performance. Power Electronics—May 2003 Proceedings (PCIM), Nurenburg, vol. 47, pp. 275-278.
Bulucea “Trench DMOS Transistor Technology for High Current (100 A Range) Switching” Solid-State Electronics vol. 34 No. pp. 493-507 (1991).
Chang et al. “Numerical and experimental Analysis of 500-V Power DMOSFET with an Atomic-Lattice Layout,” IEEE Transactions on Electron Devices 36:2623 (1989).
Chang et al. “Self-Aligned UMOSFET's with a Specific On-Resistance of 1m.OMEGA. cm.sup.2,” IEEE Transactions on Electron Devices 34:2329-2333 (1987).
Cheng et al. , “Fast reverset recovery body diodie in high-voltage VDMOSFET using cell-dsistributed schottky contacts,” (May 2003) IEEE Transactions on Electron Devices, vol. 50. No. 5, pp. 1422-1425.
Curtis et al. “APCVD TEOS: 03 Advanced Trench Isolation Applications,” Semiconductor Fabtech 9th Edition (1999) 8 pages total.
Darwish et al. A New Power W-Gated Trench MOSFET (WMOSFET) with High Switching Performance. ISPSD Proceedings—Apr. 2003, Cambridge, 4 pages total.
Djekic, O. et al., “High frequency synchronous buck converter for low voltage applications,” (1998) Proc. IEEE Power Electronics Specialist Conf. (PESC), pp. 1248-1254.
Fujihara “Theory of Semiconductor Superjunction Devices” Jpn. J. Appl. Phys. vol. 36 pp. 6254-6252 (1997).
Gan et al. “Poly Flanked VDMOS (PFVDMOS): A Superior Technology for Superjunction Devices,” IEEE Power Electronics Specialists Conference, Jun. 17-22, 2001, Vancouver, Canada, 4 pages total.
Glenn et al. “A Novel Vertical Deep Trench Resurf DMOS (VTR-DMOS)” IEEE ISPD, May 22-25, 2000, Toulouse France, pp. 197-200.
Kao et al. “Two Dimensional Thermal Oxidation of Silicon-I. Experiments, ”, IEEE Transactions on Electron Devices, vol. ED-34, No. 5, May 1987, pp. 1008-1017.
Kao et al. “Two Dimensional Thermal Oxidation of Silicon-II. Modeling Stress Effects in Wet Oxides,”, IEEE Transactions on Electron Devices, vol. ED-35, No. 1, Jan. 1988, pp. 25-37.
Kassakian, J.G. et al., “High-frequency high-density converters for distributed power supply systems,” (Apr. 1988) Proceedings of the IEEE, vol. 76, No. 4, pp. 362-376.
Korman, C.S. et al., “High performance power DMOSFET with integrated schottky diode,” (1989) Proc. IEEE Power Electronics Specialist Conf. (PESC), pp. 176-179.
Lorenz et al. “Cool MOS—An important milestone towards a new Power MOSFET generation” power Conversion pp. 151-160 (1988).
Maksimovic, A.M. et al., “Modeling and simulation of power electronic converters,” (Jun. 2001) Proceedings of the IEEE, vol. 89, No. 6, pp. 898-912.
Mehrotra, M. et al., “Very low forward drop JBS rectifiers fabricated using submicron technology,” (Nov. 1993) IEEE Transactions on Electron Devices, vol. 40, No. 11, pp. 2131-2132.
Miller, “Power Management & Supply—Market, Applications Technologies—an Overview,” Infineon Technologies, downloaded from the internet <<http://www.ewh.ieee.org/r8/germany/ias-pels/m—regensburg/overview—miller.pdf>>, May 5, 2003, 53 pages total.
Moghadam “Delivering Value Around New Industry Paradigms,” Technical Literature from Applied Materials, pp. 1-11, vol. 1, Issue 2, Nov. 1999.
Park et al., “Lateral Trench Gate Super-Junction SOI-LDMOSFETs with Low On-Resistance,” Institute for Microelectronics, University of Technology Vienna, Austria, (2002). pp. 283-285.
Sakai et al., “Experimental investigation of dependence of electrical characteristics of device parameters in trench MOS barrier, schottky diodes,” (1998) International Symposium on Power Semiconductors and ICs, Technical Digest, pp. 293-296.
Shenai et al., “Current transport mechanisms in atomically abrupt metal-semiconductor interfaces,” (Apr. 1988) IEEE Transactions on Electron Devices, vol. 35, No. 4, pp. 468-482.
Shenai et al., “Monolithically integrated power MOSFET and schottky diode with improved reverse recovery characteristics,” (Apr. 1990) IEEE Transactions on Electron Devices, vol. 37, No. 4, pp. 1167-1169.
Shenoy et al. “Analysis of the Effect of Charge Imbalance on the Static and Dynamic Characteristic of the Super Junction MOSFET,” IEEE International Symposium on Power Semiconductor Devices 1999, pp. 99-102 (1999).
Singer “Empty Spaces in Silicon (ESS): An Alternative to SOI,” Semiconductor International p. 42, Dec. 1999.
Tabisz et al., “A MOSFET resonant synchronous rectifier for high-frequency dc/dc converters,” (1990) Proc. IEEE Power Electronics Specialist Conf. (PESC), pp. 769-779.
Technical Literature from Quester Technology, Model APT-4300 300 mm Atmospheric TEOS/Ozone CVD System, ( unknown date), 3 pages total.
Technical Literature from Quester Technology, Model APT-6000 Atmospheric TEOS-Ozone CVD System, (unknown date), 2 pages total.
Technical Literature from Silicon Valley Thermal Systems, APNext, High Throughput APCVD Cluster Tool for 200 mm/300 mm Wafer Processing, unknown date.
Tu et al. “On the reverse blocking characteristics of schottky power diodes,” (Dec. 1992) IEEE Transactions on Electron Devices, vol. 39, No. 12, pp. 2813-2814 2 pages total. cited by other.
Ueda et al. “An Ultra-Low On-Resistance Power MOSFET Fabricated by Using a Fully Self-Aligned Process,” IEEE Transactions on Electron Devices 34:926-930 (1987).
Wilamowski et al. “Schottky Diodes with High Breakdown Voltages,” Solid-State Electronics 26:491-493 (1983).
Wolf “Silicon Processing for the VLSI Era” vol. 2 Process Integration Lattice Press (1990), 3 pages total.
Wolf et al., “Silicon Processing for the VLSI Era” vol. 1—Process Technology, Second Edition, (1990), pp. 658.
Yamashita et al., Conduction Power loss in MOSFET synchronous rectifier with parallel-connected schottky barrier diode, (Jul. 1998) IEEE Transactions on Power electronics, vol. 13, No. 4, pp. 667-673.
Yang, et al.; “Tunable Oxide-Bypassed Trench Gate MOSFET: Breaking the Ideal Superjunction MOSFET Performance Line at Equal col. Width;” IEEE Electron Device Letters; Nov. 2003; pp. 704-706; vol. 24; No. 11.
Office action for U.S. Appl. No. 12/039,011 (Apr. 23, 2012).
Notice of Allowance for U.S. Appl. No. 12/636,011 (Mar. 22, 2012).
Office action for U.S. Appl. No. 12/819,109 (Feb. 24, 2012).

Related Publications (1)

	Number	Date	Country
	20110309469 A1	Dec 2011	US

Trench MOS barrier schottky rectifier with a planar surface using CMP techniques

Information

Patent Number

Date Filed

Date Issued

Inventors

Original Assignees

Examiners

CPC

US Classifications

Field of Search

US

International Classifications