This invention relates to the field of semiconductor devices. More particularly, this invention relates to trench isolation in semiconductor devices.
As the dimensions of integrated circuits continue to scale to smaller an smaller dimensions, the electrical isolation of one transistor from the next becomes increasingly difficult. The most commonly used method for electrical isolation is shallow trench isolation (STI) in which shallow trenches are formed between transistors and filled with a dielectric. In instances where the voltage is higher, the trenches must either be made wider or deeper to support the higher voltage. Increasing the active pitch (trench opening width plus active geometry width) by making the trenches wider is the more manufacturable solution, but it also causes the area of the integrated circuit to increase thus reducing the number of chips that may be formed on a wafer with a resultant increase in cost per chip. Making the trenches deeper while keeping the active pitch constant is difficult because trench etch tends to increase the width of the trench opening for deeper trenches. This results in a decrease in the width of the active width resulting in reduced transistor drive current.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to a more detailed description that is presented later.
In one embodiment, an isolation trench in a substrate of a semiconductor device has a shallower portion and a deeper portion and a transition region between the deeper portion and the shallower portion. A slope of a sidewall of the transition region sidewall is less vertical than a slope of a sidewall of the shallower portion and is less vertical than a slope of a sidewall of the deeper portion. The isolation trench contains a dielectric fill material.
In another embodiment, the isolation trench is formed by forming a first portion of the isolation trench in a substrate of the semiconductor device; forming polysilicon sidewalls on walls of the first portion; etching the substrate below the first portion to form a second portion of the isolation trench; and filling the isolation trench with a dielectric fill material.
The present invention is described with reference to the attached figures, wherein like reference numerals are used throughout the figures to designate similar or equivalent elements. The figures are not drawn to scale and they are provided merely to illustrate the invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention.
A method of forming an isolation trench with increased depth without increasing active pitch according to an embodiment is described in
To prevent erosion of the top of the trench 1112 which would increase the size of the trench opening, a layer of polysilicon 1220 is deposited over the partially etched trench as shown in
The trench 1112 is then etched to full depth which may be 200 to 1000 nm deep as shown in
The trench 1112 is shown in
After the polysilicon sidewalls 1324 are removed, the trench 1112 is filled with dielectric 1638 and the dielectric is planarized as shown in
Additional processing then may be performed to build transistors and other electrical devices and also to build the interconnection layers to complete the integrated circuit.
In some applications it may be desirable to form deep trenches on portions of the chip where high voltage circuits are constructed and to form shallow trenches where low voltage circuits are constructed. One embodiment in which both deep and shallow isolation trenches are simultaneously formed is illustrated in
In
A first portion 2114 of deep isolation trench 2112 is etched and active photoresist pattern 2008 is removed as shown in
In
In
Shallow isolation trench 2529 and the second portion 2528 of deep high voltage trench 2112 are etched together as shown in
The dielectric 2638 is then planarized and the silicon nitride layer 2006 and pad oxide layer 2004 removed as shown in
Additional processing to form devices and interconnection may then be performed to complete the integrated circuit.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above described embodiments. Rather, the scope of the invention should be defined in accordance with the following claims and their equivalents.
This application is a divisional of U.S. Nonprovisional application Ser. No. 13/284,241, filed Oct. 28, 2011, which claims the benefit of priority of U.S. Provisional Application No. 61/407,756, filed Oct. 28, 2010, both of which are herein incorporated by reference in their entireties. The following co-pending patent application is related and hereby incorporated by reference: U.S. patent application Ser. No. 13/284,181 (Texas Instruments docket number TI-66906), filed on Oct. 28, 2011. With its mention in this section, this patent application is not admitted to be prior art with respect to the present invention
Number | Date | Country | |
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61407756 | Oct 2010 | US |
Number | Date | Country | |
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Parent | 13284241 | Oct 2011 | US |
Child | 14190229 | US |