Claims
- 1. A method of dynamically biasing a transistor, the method comprising:
applying a signal transitioning from a logic low level to a logic high level to a first transistor base via a capacitor, to thereby bias the first transistor on; in response to the first transistor being biased on, conducting current via the first transistor through a first resistor to generate a first voltage, applying the first voltage to an emitter of a second transistor, wherein the first voltage tends to bias the second transistor off, and lowering a voltage AC coupled to a base of the second transistor, further tending to bias the second transistor off; applying a signal transitioning from a logic high level to a logic low level to the first transistor base via the capacitor, to thereby bias the first transistor off; and in response to the first transistor being biased off, inhibiting the conduction of current via the first transistor through the first resistor to thereby generate a second voltage tending to turn the second transistor on, the second voltage lower than the first voltage, and raising the voltage AC coupled to the base of the second transistor, further tending to bias the second transistor on.
- 2. The method as defined in claim 1, wherein AC coupling the voltage to the base of the second transistor keeps the second transistor operating in a linear region.
- 3. The method as defined in claim 1, further comprising applying the signal transitioning from a logic low level to a logic high level to a third transistor base via a second capacitor, to thereby bias the third transistor on, wherein having one or more of the first transistor and the third transistor biased on causes the second transistor to be biased off.
- 4. The method as defined in claim 1, further comprising applying the signal transitioning from a logic high level to a logic low level to a third transistor base via a second capacitor, to thereby bias the third transistor off, wherein having both of the first transistor and the third transistor biased off causes the second transistor to be biased on.
- 5. The method as defined in claim 1, further comprising sinking current from an output switch circuit via the second transistor at least partly in response to the second transistor being biased on.
- 6. The method as defined in claim 1, further comprising AC coupling a clock signal to the first base, to thereby cyclically bias the first transistor on and off.
- 7. A trigger circuit used to enable and disable a current sink output, the trigger circuit comprising:
a first input terminal; a first capacitor having a first capacitor terminal and a second capacitor terminal, the first capacitor terminal connected to the first input terminal; a first transistor having a first base, a first collector, and a first emitter, the first base connected to the second capacitor terminal, wherein the first capacitor is configured to AC couple the first base to the first input terminal; a first resistor having a first resistor terminal and a second resistor terminal, the first resistor terminal configured to be connected to a first voltage source, and the second resistor terminal connected to the first base; a second resistor having a third resistor terminal and a fourth resistor terminal, the third resistor terminal configured to be connected to a second voltage source, and the second resistor terminal connected to the first collector; a third resistor having a fifth resistor terminal and a sixth resistor terminal, the fifth resistor terminal connected to the first emitter, and the sixth resistor terminal configured to be coupled to a ground reference; a fourth resistor having a seventh resistor terminal and an eighth resistor terminal, the seventh resistor terminal configured to be coupled to the second voltage source; a second capacitor having a third capacitor terminal and a fourth capacitor terminal, the third capacitor terminal configured to be coupled to the fourth resistor terminal; and a second transistor having a second base, a second collector, and a second emitter, the second base connected to the eighth resistor terminal and to the fourth capacitor terminal, wherein the second capacitor is configured to AC couple the second base to the first collector, and the second emitter is coupled to the fifth resistor terminal, wherein the second transistor is configured to selectively provide a current path via the second collector, through the second transistor and thorough the third resistor.
- 8. The trigger circuit as defined in claim 7, further comprising:
a second input terminal; a third capacitor having a fifth capacitor terminal and a sixth capacitor terminal, the fifth capacitor terminal connected to the second input terminal; a third transistor having a third base, a third collector, and a third emitter, the third base connected to the sixth capacitor terminal, wherein the third capacitor is configured to AC couple the third base to the second input terminal, the third collector connected to the first collector, the third emitter is coupled to the first emitter, wherein the trigger circuit is configured to bias the second transistor on in response to the first input terminal and the second input terminal being coupled to a signal at a logic low state.
- 9. The trigger circuit as defined in claim 7, further comprising:
a fifth resistor having a ninth resistor terminal and a tenth resistor terminal, the ninth resistor terminal connected to the seventh resistor terminal; a sixth resistor having an eleventh resistor terminal and a twelfth resistor terminal, the tenth resistor terminal connected to the ground reference; and a third transistor having a third base, a third collector, and a third emitter, the third base connected to the tenth resistor terminal, the first collector connected to the eighth resistor terminal, and the third emitter coupled to the twelfth resistor terminal.
- 10. The trigger circuit as defined in claim 7, wherein the second transistor is configured to be operated in a non-saturated mode.
- 11. A method of dynamically biasing a transistor, the method comprising:
AC coupling a first input to a first transistor base of a first transistor, so that an input signal applied to the first input that transitions from a logic low level to a logic high level biases the first transistor on, and wherein an input signal applied to the first input that transitions from a logic high level to a logic low level biases the first transistor off; conducting a first current via a first emitter of the first transistor when the first transistor is on, wherein the first current is conducted through a first resistor connected to a second emitter of a second transistor, thereby placing the second emitter at a first voltage, the first voltage tending to turn the second transistor off; and applying a biasing-on voltage via a capacitor to a second base of the second transistor upon the first transistor being initially biased off in response to the input signal transitioning from a logic high level to a logic low level, and inhibiting the first current from being conducted via the first emitter through the first resistor, thereby placing the second emitter at a second voltage lower than the first voltage, further tending to bias the second transistor on.
PRIORITY CLAIMS
[0001] The benefit under 35 U.S.C. §119(e) of U.S. Provisional Application No. 60/208,899, filed Jun. 2, 2000, and entitled “MIXED MODE TRANSCEIVER” and of U.S. Provisional Application No. 60/267,366, filed Feb. 7, 2001, and entitled “TRANSCEIVER,” is hereby claimed.
Provisional Applications (2)
|
Number |
Date |
Country |
|
60208899 |
Jun 2000 |
US |
|
60267366 |
Feb 2001 |
US |