Patent Application
20240313080
This application claims the priority benefit of Taiwan application serial no. 112109159, filed on Mar. 13, 2023. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
The disclosure relates to a two-dimensional semiconductor device technique, and in particular to a two-dimensional semiconductor device and an electrode used therein.
Two-dimensional material is a crystalline material composed of a single layer or a few layers of atoms. Its energy gap may be adjusted with changes in chemical composition and atomic layer number. Hence, it can be used to improve the performance of electronic devices, such as light-emitting devices. Furthermore, two-dimensional materials have also been applied to semiconductor devices recently, and the channel thickness of field effect transistors is expected to be further reduced to the atomic scale.
Reducing the impedance between the metal/semiconductor interface to improve the efficiency of the device has always been an effective method to improve the efficiency of the device. For a two-dimensional material semiconductor device using transition metal dichalcogenide (TMD), the interface between the semiconductor and the metal will generate additional gap states (metal-induced gap state, MIGS) on the energy gap at the interface due to the metallization of the semiconductor. These induced vacant gap states will trap carriers flowing through the interface, resulting in the Fermi level pinning (FLP) effect, causing the formation of Schottky contacts on the metal-semiconductor interface, which will cause inevitable and undesirable contact impedance.
The disclosure provides an electrode for a two-dimensional semiconductor device, which may not only improve the properties of the device, but also adjust its Fermi level to be the same as or close to that of the semiconductor via altering its alloy composition or alloy ratio. Therefore, more kinds of semiconductor materials can have the properties of stable interface and ohmic contact.
The disclosure provides a two-dimensional semiconductor device, which can improve the electrical properties of the device, such as low subthreshold swing (SS), high carrier mobility, and improved junction contact resistance.
An electrode for a two-dimensional semiconductor device of the disclosure includes a contact electrode and a metal electrode formed thereon. The contact electrode is made of a semi-metal alloy including several semi-metal elements or at least one semi-metal element and its alloy. And the Fermi surface of the semi-metal alloy is adjusted by altering its alloy ratio, hence as the contact electrode is in contact with the two-dimensional semiconductor, only a tiny amount of gap states (such as gap states less than leV or even zero) is generated on the energy gap at the interface to reduce the Schottky energy barrier. At the same time, a space gap slightly smaller than a Van der Waals distance is created on top of the two-dimensional semiconductor to ensure the stability of the structure while preventing or minimizing the coupling of outer orbital electrons between the metal electrode and the two-dimensional semiconductor.
In an embodiment of the disclosure, the semi-metal element includes antimony (Sb), bismuth (Bi), or tin (Sn).
In an embodiment of the disclosure, the semi-metal alloy is an antimony-bismuth alloy or a bismuth-aluminum alloy.
In an embodiment of the disclosure, the antimony content in the antimony-bismuth alloy is between 10 a % and 84 a %.
In an embodiment of the disclosure, the Fermi surface of the semi-metal alloy may be matched with that of the Fermi surface of the n-type or p-type two-dimensional semiconductor to achieve the lowest Schottky energy barrier.
In an embodiment of the disclosure, the metal electrode includes platinum (Pt), gold (Au), aluminum (Al), titanium (Ti), or chromium (Cr).
A two-dimensional semiconductor device of the disclosure includes a substrate, a two-dimensional semiconductor layer, and multiple electrodes. A two-dimensional semiconductor layer is formed on the substrate, and the electrodes are formed on the two-dimensional semiconductor layer. The electrodes include a contact electrode and a metal electrode, and the contact electrode is set not only between the metal electrode and the two-dimensional semiconductor layer to avoid direct contact of the two-dimensional material and the metal electrode, but also creates a space gap slightly smaller than a Van der Waals distance between the metal electrode and the two-dimensional semiconductor layer to further ensure the stability of the structure and prevent/minimize the coupling of outer orbital electrons between the metal electrode and the two-dimensional semiconductor layer.
In an embodiment of the disclosure, the material of the two-dimensional semiconductor layer includes, but is not limited to, tungsten disulfide (WS2), molybdenum disulfide (MoS2), tungsten diselenide (WSe2), molybdenum ditelluride (MoTe2), tungsten ditelluride (WTe2), or molybdenum diselenide (MoSe2).
Based on the above, in the electrode for the two-dimensional semiconductor device of the disclosure, the semi-metal alloy is used as the contact electrode in contact with the two-dimensional semiconductor layer, which can not only reduce the generation of additional gap states (metal-induced gap state; MIGS) at the semiconductor-metal interface, but also change the Fermi surface of the semi-metal alloy appropriately by adjusting the ratio of the alloy, thereby reducing or eliminating the Schottky energy barrier caused by the Fermi level pinning (FLP) effect at the metal-semiconductor interface. Compared with the contact electrode using a single element electrode (single metal or single semi-metal), the use of the semi-metal alloy of the disclosure may not only adjust the Fermi level of the contact electrode, so that the Fermi level thereof can better match the Fermi level of the semiconductor, but also effectively improve the properties of the device, such as a transistor, because of the matching of energy levels.
To make the aforementioned more comprehensible, several embodiments accompanied by drawings are described in detail as follows.
An electrode for a two-dimensional semiconductor device of the disclosure at least includes a contact electrode and a metal electrode formed thereon, wherein the material of the contact electrode is a semi-metal alloy, and the semi-metal alloy includes several semi-metal elements or at least one semi-metal element and an alloy material thereof. In an embodiment, the semi-metal element includes antimony (Sb), bismuth (Bi), tin (Sn), and other elements, and the semi-metal alloy refers to a mixture of various semi-metal elements (for example, antimony-bismuth alloy) or an alloy formed of a semi-metal element and an alloy material thereof (for example, bismuth aluminum alloy). In an embodiment, the metal electrode includes platinum (Pt), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), or other known common electrodes. Since the semi-metal has no (or extremely low) electronic density of state in the Fermi level bandgap, after contact with the two-dimensional semiconductor, only a tiny amount of gap states (such as gap states less than leV or even 0) are produced, so as to reduce the Schottky energy barrier. Therefore, the generation of MIGS can be avoided/reduced, and the phenomenon of FLP can be eliminated/reduced to achieve the purpose of improving the electrical properties of the semiconductor device. However, the energy level properties of a single semi-metal are fixed and cannot be applied to various semiconductor devices (especially when more two-dimensional semiconductor devices will be developed in the future). Therefore, it is necessary to use an alloy to regulate the Fermi level of the semi-metal contact electrode, so as to adjust the energy level mismatch between the metal and the semiconductor and eliminate/improve the FLP at the interface. At the same time, the semi-metal alloy may form a gap that is slightly smaller than the Van der Waals distance above the two-dimensional semiconductor, so as to ensure the stability of the structure while preventing/minimizing the coupling of outer orbital electrons at the interface between the two-dimensional semiconductor and the metal electrode.
The accompanying drawings in the following embodiments are for a more complete description of the embodiments of the disclosure. However, the disclosure may still be implemented in many different forms not limited to the described embodiments. In addition, the relative thicknesses, distances, and positions of various regions or layers may be reduced or enlarged for clarity.
Referring to
The two-dimensional semiconductor layer 102 is usually only a few layers thick and exists in the form of a strong bonding within the same layer, and there is only a weak Van der Waals force between the layers, which may be mechanically or chemically exfoliated into individual and atomically thin layers. In some embodiments, the two-dimensional semiconductor layer 102 may include one or more layers, and the thickness thereof may be between about 0.5 nm and 100 nm. The material of the two-dimensional semiconductor layer 102 includes, but is not limited to, tungsten disulfide (WS2), molybdenum disulfide (MoS2), tungsten diselenide (WSe2), molybdenum ditelluride (MoTe2), tungsten ditelluride (WTe2), or molybdenum diselenide (MoSe2). The two-dimensional semiconductor layer 102 may be used as an active layer of an ultra-thin channel transistor, and tungsten disulfide (WS2) has the properties of a semiconductor and a direct optical bandgap that may be adjusted in the range of 0.8 eV to 2.0 eV, so WS2 is a preferred material for the two-dimensional semiconductor layer 102.
Please continue to refer to
Several experimental examples are listed below to verify the implementation effect of the disclosure, but the disclosure is not limited to the following content.
Low-pressure chemical vapor deposition (LPCVD) was used, and a sapphire substrate was used as the substrate for growing WS2.
First, the sulfur powder was placed upstream in a LPCVD furnace tube, and a quartz boat loaded with tungsten oxide powder and sapphire substrate was placed downstream. Then. 200 sccm of argon gas and 20 sccm of hydrogen gas were introduced, and a constant pressure was maintained. Finally, the temperature was raised to 850° C., and WS2 started to grow.
A 3% polycarbonate (PC) chloroform solution was used to spin-coat the sapphire substrate grown with WS2 as a carrier for transferring WS2.
After peeling off the PC film adhered to WS2 with water, WS2 was moved into isopropanol (IPA) and then transferred onto a Si/SiO2 substrate.
After the transfer, PC/WS2/SiO2/Si was put into a chloroform solution for 24 hours to dissolve the outermost PC film, leaving WS2 with a thickness of about 0.8 nm on the SiO2/Si substrate. Then, after washing with acetone and IPA, the substrate was placed in a vacuum furnace tube for baking to remove residual moisture, volatile solvents, and polymer materials.
The disclosure is an example of using an antimony-bismuth alloy as a semi-metal alloy.
The preparation manner was to mix specific ratios of antimony and bismuth metal particles, then put the mixture into a small quartz tube, and seal the tube under a vacuum. The sealed quartz tube was placed in a furnace tube, heated to 800° C. at a slow speed, and then maintained for 6 hours to alloy. Then, the temperature was slowly lowered by 1 to 24 hours for the antimony-bismuth alloy to harvest better crystallinity.
A digital light processing (DLP) lithography tool was used to generate the designed patterns on the WS2 active layer. Then, the antimony bismuth alloy and gold (Au) were sequentially deposited onto the SiO2/Si substrate by thermal evaporation, wherein the antimony-bismuth alloy was preheated for several minutes under 10-7 torr before the deposition to guarantee the uniformity of the deposited alloy film. The thickness of the antimony-bismuth alloy used as the contact electrode was about 20 nm, and the thickness of gold used as the metal electrode was about 60 nm.
After the deposition, a photoresist remover (Remover PG) was used to remove/liftoff the residual photoresist and its on-top antimony-bismuth alloy and gold to obtain the two-dimensional semiconductor device (that is, the WS2-FET device) as shown in
In order to detect the alloy ratio, an Energy-dispersive X-ray spectroscopy (EDS) was used for analysis.
The sample preparation method was to deposit a thickness of about 120 nm of the antimony-bismuth alloy prepared in Step 1.3 above on the sapphire substrate by thermal evaporation. The measurement results of the ratio of specific elements were obtained, so the percentage of the antimony-bismuth alloy was calculated.
The device properties of the back-gate field effect transistor of Experimental Example 1 were tested to obtain the on/off ratio, subthreshold swing (SS), and carrier mobility of the WS2-FET device.
The back-gate field effect transistor was prepared by the above manner, and the obtained antimony-bismuth alloy had an antimony content of 15 a % (atomic percentage) and a bismuth content of 85 a %.
Then, the electrical properties of the WS2-FET device of Experimental Example 1 were measured, and the results are shown in
The WS2-FET devices were fabricated by the same preparation manner as Experimental Example 1, but in Step 1.4, a single metal Cr (Comparative Example 1), a single semi-metal Sb (Comparative Example 2), and a single semi-metal metal Bi (Comparative Example 3), which are conventional adhesive layers used for gold metal electrode, were used as the materials of the contact electrode.
Then, the electrical properties of the WS2-FET device of Comparative Examples 1 to 3 were measured, and the results are also shown in
It may be seen from
With the same preparation method as Experimental Example 1, another batch of WS2-FET devices were fabricated, but the antimony-bismuth alloys were respectively Bi0.90Sb0.10 (Experimental Example 2). Bi0.68Sb0.32 (Experimental Example 3), and Bi0.16Sb0.84 (Experimental Example 4).
Then, the electrical properties of the WS2-FET devices of Experimental Examples 2 to 4 were measured, and the results are shown in
It may be seen from
In summary, the disclosure uses the semi-metal alloys as the electrode for the two-dimensional semiconductor device, which can not only reduce the generation of MIGS, but also linearly change the Fermi level of the semi-metal alloy by adjusting the alloy ratio, so as to form ohmic contact compatible with different two-dimensional semiconductor materials. Therefore, the two-dimensional semiconductor device improved through the contact electrode can not only effectively improve the phenomenon of FLP, but also greatly help the development and application of the two-dimensional semiconductor device.
Although the disclosure has been disclosed above with the embodiments, the embodiments are not intended to limit the disclosure. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the disclosure. The scope of protection of the disclosure should be defined by the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 112109159 | Mar 2023 | TW | national |
