Patent Application
20100062693
The present invention relates, most generally, to semiconductor manufacturing. More particularly, the present invention is related to an apparatus and polishing method for removing metal and other films.
In the rapidly advancing semiconductor manufacturing industry, conventional methods for polishing to remove metal or other conductive films from over the surface of a semiconductor substrate, are well known. Chemical mechanical polishing, CMP, is a favored polishing operation although various other polishing operations are available in the semiconductor manufacturing industry. CMP is conventionally used in damascene processing operations which include forming a metal or other conductive layer over a dielectric or other surface and filling openings such as contacts, vias and trenches formed in the surface. CMP removes the metal or other conductive materials from over the surface, leaving the metal or other conductive material filling the openings to form conductive interconnect structures such as contacts, vias and conductive leads, the tops of these interconnect structures being coplanar with the dielectric surface.
Advanced technologies such as 3D-IC using wafer stacking and through-Si-via (TSV) technologies require narrow, deeper vias or other openings with high aspect ratios. As a consequence, conductive films with greater thicknesses are now used in order to ensure that these narrow, deeper vias or other openings with high aspect ratios, are completely filled with the conductive material. One shortcoming associated with conventional chemical mechanical polishing operations is a relatively slow removal rate that is typically less than about 0.4 or 0.5 microns per minute. Therefore, as advancing technologies require the metal or other conductive film thicknesses to become greater to fill narrower, deeper openings with higher aspect ratios, the time associated with removing a metal or other conductive film from over the surface of the semiconductor substrate increases and limits production throughput. Another shortcoming associated with conventional CMP is the very high cost of the polishing slurry used, this shortcoming being magnified when CMP is used for lengthy operations required for removing increasingly thicker films.
It would therefore be advantageous to provide an apparatus and cost-efficient process that more quickly removes a bulk metal or other conductive film from over a surface of a semiconductor wafer and produces a high-quality polished surface such as may be produced by chemical mechanical polishing.
To address these and other needs, and in view of its purposes, one aspect of the present invention provides a wafer processing apparatus. The apparatus comprises a first processing chamber comprising at least one of (a) a wet chemical etching apparatus and (b) a mechanical polishing apparatus that removes material from a wafer seated on a chuck therein by relative motion between the chuck and a cutting member. The wafer processing apparatus also includes a second processing chamber comprising a chemical mechanical polishing, CMP, apparatus and a wafer transfer apparatus that transfers the semiconductor substrate from the first processing chamber to the second processing chamber within the wafer processing apparatus.
According to another aspect, the present invention provides a method for processing a semiconductor wafer within a single apparatus, the method comprising: forming a semiconductor wafer with a bulk metal layer formed over a surface thereof; removing an upper portion of the bulk metal layer from the semiconductor wafer using wet chemical etching or mechanical cutting in a first processing chamber of the apparatus; and thereafter, polishing in a second processing chamber of the apparatus, thereby removing a remaining portion of the bulk metal layer and exposing the surface. The polishing comprises chemical mechanical polishing, CMP.
The present invention is best understood from the following detailed description when read in conjunction with the accompanying drawing. It is emphasized that, according to common practice, the various features of the drawing are not necessarily to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. Like numerals denote like features throughout the specification and drawing.
Damascene processing is commonly used in the semiconductor manufacturing industry and includes forming a dielectric layer then forming openings or voids in a surface of the dielectric layer. The openings or voids, hereinafter referred to as openings, extend down from an upper surface of the dielectric layer. The openings which may be contact openings, vias, trenches or other grooves, are then filled with a conductive material, typically a metal such as aluminum or copper. Various deposition methods may be used to form a film of the conductive material over the top surface of the dielectric and also filling the openings. A polishing operation is then used to planarize by removing the bulk conductive film from over the surface, leaving the conductive material to fill the openings. The conductive material in the openings form conductive structures such as contacts, vias, or interconnect leads. Chemical mechanical polishing, CMP, is conventionally known and used for this purpose.
As technologies advance, the vias and other openings formed in the dielectric layers become increasingly deeper and narrower and have increasingly higher aspect ratios. In order to completely fill such a deep via or other opening with high aspect ratio, various deposition techniques such as ECP (electrochemical plating) may be used to form a conductive material such as metal over the dielectric surface and within the opening, but these deposition processes require the formation of an increasingly thicker bulk film over the dielectric surface in order ensure that the vias or other openings are completely filled. Typical CMP polishing operations remove bulk metal films such as copper at a relatively slow rate such as about 0.4 μm/min. With the thickness of the bulk metal films increasing to accommodate the deeper openings with higher aspect ratios, the use of CMP to completely remove an entire bulk metal layer and to finally polish the film to produce the interconnect structure using damascene technology, is a time consuming process that limits throughput.
The present invention provides a multi-step processing operation that removes a bulk metal or other conductive or semiconductive film from over a surface and is carried out in a single, multi-chamber processing apparatus. The multi-step processing operation features a first, bulk film removal operation followed by CMP which polishes and planarizes the surface to form damascene structures such as contacts, openings and interconnect leads from conductive material formed in the openings formed within the dielectric layer.
According to the exemplary wafer processing apparatus shown in
Wet chemical etching apparatus 16 may be any of various suitable and conventionally known wet chemical etching apparatuses, such as a stagnant or cascading bath or an apparatus that includes a chuck upon which a wafer is seated and including one or more nozzles directing wet chemical etching solutions to a surface of the wafer seated on the chuck. According to various exemplary embodiments, the chuck may provide rotation to the wafer and various conventional methods such as laser interferometry may be used to detect an amount of film thickness being removed and to provide feedback to a controller to terminate the operation when a desired thickness has been removed. In one exemplary embodiment, chemical etching apparatus 16 may be used to remove a copper film from over a substrate and the wet chemical solution may be DI:H3PO4:H2O2 in a 20:1:1 ratio but other suitable wet chemical etching solutions may be used for etching copper and various suitable wet chemical etching solutions may be used for removing other conductive films such as aluminum, or other semiconductive films, in other exemplary embodiments.
Mechanical polishing station 18 may be any of various mechanical polishing stations that remove a film from the surface of a substrate using conventional abrading or cutting methods. Mechanical polishing station 18 may use any of various conventional techniques for terminating the removal operation when a desired film thickness has been removed. In one exemplary embodiment, mechanical polishing station 18 may include a diamond grit for planar cutting and according to another exemplary embodiment, various teeth or blades may be used to remove a film from a surface of a substrate by mechanical force by providing motion between the cutting member and the chuck upon which a wafer is seated.
Each of wet chemical etching apparatus 16 and mechanical polishing station 18 may have their particular components adapted to remove a conductive metal film such as aluminum, copper, or alloys thereof or various semiconductor materials such as polysilicon, from over a subjacent surface such as a dielectric or other material. For example, the cutting tool or surface and rotational speed in mechanical polishing station 18 may be chosen in conjunction with the material to be removed and the chemical solution, temperatures and other parameters in wet chemical etching apparatus 16 may be chosen in conjunction with the material to be removed.
Although openings 34 are illustrated as terminating within film 32, it should be understood that in other exemplary embodiments openings 34 may extend through film 32 and extend into an underlying layer and in still other exemplary embodiments openings 34 may be formed directly within a substrate material.
The structure in
The removal operation in the first processing chamber advantageously includes a faster removal rate than that which will be obtained in the subsequent chemical mechanical processing operation that may be carried out in CMP apparatus 10 of
A chemical mechanical polishing operation is carried out on the structure illustrated in
The preceding merely illustrates the principles of the invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and conditional language recited herein are principally intended expressly to be only for pedagogical purposes and to aid the reader in understanding the principles of the invention and the concepts contributed by the inventors to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents and equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.
This description of the exemplary embodiments is intended to be read in connection with the figures of the accompanying drawing, which are to be considered part of the entire written description. In the description, relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,” “top” and “bottom” as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation. Terms concerning attachments, coupling and the like, such as “connected” and “interconnected,” refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise.
Although the invention has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly, to include other variants and embodiments of the invention, which may be made by those skilled in the art without departing from the scope and range of equivalents of the invention.
