Two transistor flash memory cell

Abstract

A two transistor cell NOR architecture flash memory is provided wherein the floating gate transistor is couple between the selection transistor and an associated bit line. The flash memory is deposited within a triple well and operates according to a Fowler-Nordheim tunnel mechanism. Programming of memory cells involves tunneling of carriers through gate oxide from a channel region to a floating gate rather than tunneling from a drain or source region to the floating gate.

Description

BACKGROUND OF THE INVENTION

Flash memory cells have enjoyed recent commercial success due to their relatively low cost, the ease in erasing information stored in a flash memory array and their applications to bank check cards, credit cards, and the like. A flash memory cell which is recognized by the semiconductor industry as a standard has not yet emerged. Many types of flash memories exist which embody many different architectures. The programming, reading and erasing of cells can be generally described under one of the following architectures-NOR, AND, or NAND. Further, the programming mechanism of the flash memory cell typically involves Fowler-Nordheim tunneling through an energy barrier or electron injection over an energy barrier.

The array erase mechanism for Fowler-Nordheim cells can involve floating gate to channel, floating gate to drain or floating gate to source as the charge clearing path from the floating gate. The floating gate to drain or source path can prove deleterious to cell operation by destroying the tunnel oxide area located between the floating gate overlap and the drain/source region. On the other hand the tunnel oxide can also be destroyed through the programming mechanisms (e.g., programming a logic one or logic zero on the floating gate) of conventional Fowler-Nordheim flash cells. These programming mechanisms can include charge carrier paths between the floating gate and drain or alternatively between the floating gate and source. However, conventional cells do not include a programming operation involving a path between the channel and floating gate. Such an operation would be desirable from a standpoint of limiting tunnel oxide degradation due to the field re-distribution effect across the entire tunnel oxide region. Until now, a flash memory cell which allows uniform channel programming has not existed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a partial schematic/partial cross-sectional view of the flash memory cell according to the invention.

FIG. 2 illustrates a schematic drawing of a NOR architecture flash memory cell array according to the invention. Reference numerals have been carried forward from FIG. 1 .

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates a partial schematic/partial cross-sectional view of the flash memory cell according to the invention. This cell may be constructed according to fabrication methods combining triple well formation with dual gate technology. As shown, flash memory cell 26 is fabricated in a triple-well comprising a first well region (labeled here as p-weUl), a second well region (labeled here as n-well) and a third well or substrate region (labeled here as psub). The conductivity type (e.g., n-type or p-type) will change according to the field effect transistor being fabricated for the cell. The foregoing conductivity types correspond to n-channel devices. Opposite conductivity types to those named would be used with p-channel devices. Drain region 27 is shared within cell 26 by the selection transistor, which is formed in part by gate 34 , and the floating gate transistor, which is formed in part by floating gate 30 . Source region 31 serves as the source region for the selecton gate transistor while source region 33 serves as the source region for the floating gate transistor. FIG. 2 illustrates a schematic drawing of a NOR architecture flash memory cell array according to the invention. Selection transistor 22 shares a drain region with and is connected to floating gate transistor 24 . Transistors 22 and 24 together comprise memory cell 26 . Gate 34 of selection transistor 22 is connected to selection gate line SG 0 while control gate 28 of floating gate transistor 24 is connected to word line WL 0 . Cell operation for flash memory cell 26 is as follows:

Programming:

To program a cell, such as cell 26 , the associated bit line is toggled low (typically −3 volts) while the associated word line is toggled strongly high. Unselected cells sharing the same word line as the selected cell are subject to a phenomenon known as gate disturb, where the unselected cell could be unintentionally programmed. However, with the full voltage swing of opposite polarity between the selected bit line and unselected bit line make this situation less likely.A typical strong high voltage for the selected wordline for this application is around 12 to 13 volts. Selection gates (SG) for the memory array are held at a low level, typically −3 volts. Unselected bit lines remain at a high level, e.g around 3 to 4 volts. The bias of the p-well region, V p-well for transistor 22 is held at a low voltage (e.g. −3 volts) while the source voltage V s for the selection transistor 22 is left floating. Unselected cells which are associated with the bit line of a selected cell, such as BL 0 of cell 26 are subject to a phenomenon known as drain disturb wherein one of these unselected cells is programmed. However, the strong program voltage (i.e. 12 volts) generally required for programming makes this situation less likely. In connection with programming, a depletion mode transistor is turned off (programmed off or made to store a logic low level voltage) by carriers which (with reference to FIG. 1 ) tunnel in the direction of arrows 35 through a Fowler-Nordheim mechanism to floating gate 30 . Note that tunneling through gate oxide 33 occurs from the channel region to the floating gate, rather than from a drain or source region to the floating gate. This particular tunnel mechanism helps prevent the destruction of the tunnel oxide as discussed in the foregoing section concerning prior art devices. The foregoing voltage characterizations apply to n-channel transistors. Opposite voltage levels (e.g. low instead of high, etc.) apply to p-channel transistors.

Erasing:

With reference to FIGS. 1 and 2 , to erase a cell, such as cell 26 , the associated bit line is left high (e.g. 3 volts) as is VS, the source bias voltage of selection transistor 22 . Gate 34 of selection transistor 22 is toggled high (e.g. 3 volts over the circuit supply voltage) along with the bias of the p-well, Vp,W, .(e.g. 3 volts). Control gates 28 of unselected cells are toggled low (the circuit supply voltage). Control gate 28 of the selected cell 26 is toggled to a strong low, level, e.g around −12 to −14 volts. V p-Well is maintained at a high level (e.g. 3 volts). A phenomenon known as erase disturb wherein unselected cells are erased could occur. However, due the relatively strong negative voltage (e.g. −12 volts) used to erase a cell, this is less likely.

Reading:

With reference to FIGS. 1 and 2 , in order to read the contents of a selected memory cell 22 , selection gate 34 of transistor 22 within cell 28 is toggled high (e.g., the circuit supply voltage) along with the associated bit line BL 0 (e.g. 1.5 volts) of selected cell 26 . Unselected bit lines are biased low (e.g., circuit ground) Likewise voltage V p-well , the p-well voltage is biased low (at circuit ground.) V s . is also maintained low (i.e., circuit ground). Selection gate 34 of unselected bit lines are pulled low. Control gates 28 are pulled low (e.g., circuit ground) during a read operation. Bi line disturb could occur along cells associated with BL 0 . Additionally gate disturb could occur along cells associated with cells having the same selection gate line as the selected cell. The use of the circuit supply voltage in the former case involving gate disturb and the low voltages used involving the latter case make these situations unlikely.

The chart below summarizes the foregoing described cell scenarios: Note that selection lines are operable to carry voltages capable of turning transistor 22 on or off, thus selecting a cell.

						Selection
	Transistor	Bit line BL 0		V p (well)	Control Gate	Transistor Gate
	State	(volts)	V s (volts)	(volts)	(volts) (28)	(volts) (34)
PROGRAM
Selected Cell	Transistor 22-	−3	floating	−3	+12 to +13	−3
	off
Non Selected	Transistor 22-	+3 to +4	Floating	−3	+12 to +13	−3
Cell	off
(Possible-
unlikely gate
disturb)
Non Selected	Transistor 22-	−3	Floating	−3	0 to −3	−3
Cell	off
(Possible-
unlikely bitline
disturb)
ERASE
Selected Cell	Transistor 22-	+3	+3	+3	−12 to −14	Supply voltage
	on					+3
Non Selected	Transistor 22-	+3	+3	+3	0 to +3	Supply voltage
Cell	on					+3
(Possible-
unlikely gate
disturb)
READ
Selected Cell	Transistor 22-	+1.5	0	0	0	Circuit supply
	on
Non Selected	Transistor 24-	0	0	0	0	Circuit supply
Cell	off
(Possible-
unlikely gate
disturb)
Non Selected	Transistor 22-	+1.5	0	0	0	0
Cell	off
(Possible-
unlikely
bitline disturb)

Benefits of the Well:

A primary advantage of the invention is provided by the triple well structure. In view of the 70% cell coupling, which is typical in this art, the forgoing described programming biasing scheme involving 12 to 13 volts on the control gate and −3 volts on the p-well (V p =−3 volts) results in approximately 11 volts across a 100 Å tunnel oxide 33 as shown in FIG. 1. A structure with 12 volts on the control gate but without the negatively biased substrate (e.g., a substrate voltage of 0 volts at region 33 ) ( e.g., a non-triple well structure) would only develop 8.4 volts across tunnel oxide 33 of FIG. 1 . It has been shown, and is well known, that electron tunneling is an extremely sensitive function of the capacitor cathode electric field and that electron tunneling requires a cathode electric field, Ek=V tx /T tx , of at least 10 7 V/cm (where T tx is the tunnel dielectric thickness and V tx is the voltage dropped across this dielectric thickness, e.g. tunnel oxide 33 ). 11 volts across 100 Å tunnel oxide 33 of FIG. 1 provides an E k =1.1*1 7 V/cm. By contrast, an 8.4 voltage across the tunnel oxide for a non-triple well structure in the example above, provides an E=0.84*107 V/cm. Consequently, this E k is in sufficient to cause tunneling, thusly, herein lies an advantage of the triple well structure.

Another primary benefit of the triple well structure is that it allows scaling of the memory cell. Decreases in the size of the cell can include an attendant decrease in bias voltages, independent of the supply voltage. Structures without a triple well are penalized in that scaling is limited by the supply voltage since some minimum supply voltage will be required for proper functioning of periperal circuitry, e.g. sense amps, etc. The foregoing triple well benefits are in additon to the beneficial effects of the tunnel mechanism which prevents destruction of the tunnel oxide as previously mentioned.

Although the invention has been described in detail herein with reference to preferred embodiments and certain described alternatives, it is to be understood that this description is by way of example only, and it is not to be construed in a limiting sense. It is to be further understood that numerous changes in the details of the embodiments of the invention and additional embodiments of the invention, will be apparent to, and may be made by, persons of ordinary skill in the art having reference to this description. It is contemplated that all such changes and additional embodiments are within the spirt and true scope of the invention as claimed below.

Claims

1. A flash memory comprising:an array, having a NOR architecture, of selection gate lines, wordlines, bit lines and a plurality of memory cells, each said memory cell comprising a floating gate transistor connected to a selection transistor, said floating gate transistor being operable to couple said selection gate transistor to an associated cell bit line according to a method whereby carriers tunnel through gate oxide of the floating gate transistor from a channel region to the floating gate , each said memory cell being formed within a triple well including a first well of a first conductivity type within a second well of a second conductivity type within a third well of said first conductivity type.

2. A flash memory as recited in claim 1 wherein each floating gate transistor includes a tunnel oxide disposed between a floating gate and channel region of said floating gate transistor and wherein an electric field of at least 1.1*17 V/cm is developed across said tunnel oxide of a selected cell in connection with cell programming.

3. A flash memory cell as recited in claim 1 wherein selected cells of said memory are programmed using positive voltages with respect to a circuit ground on their control gates.

4. A flash memory comprising:an array, having a NOR architecture, of selection gate lines, wordlines, bit lines and a plurality of n-channel memory cells, each said memory cell comprising a floating gate transistor connected to a selection transistor, said floating gate transistor being operable to couple said selection gate transistor to an associated cell bit line according to a method whereby carriers tunnel through gate oxide of the floating gate transistor from a channel region to the floating gate , each said memory cell being formed within a triple well including a first well of a first conductivity type within a second well of a second conductivity type within a third well of said first conductivity type.