Claims
- 1. A field effect transistor (FET) comprising:
a substance, a source, a gate and a drain; multiple channels in said substrate between said drain and said source to improve the linearity of drain current vs drain voltage characteristics when a gate voltage exceeding the threshold voltage is applied at the gate, said multiple channels having alternate layers of undoped layers of first kind of semiconductor and doped layers of second kind of semiconductor, and said doped layers having doping concentrations which decrease with depth from said gate, wherein the channels are selected from the group consisting of uniformly doped, delta doped, spike doped, InAs sub-well, TlP (TlAs) sub-well, InN sub-well and InAs, TlP, TlAs, InN self assembled quantum dots for III-V compound semiconductors, and wherein the channels is selected from the group consisting of uniformly doped, delta doped, spike doped, Ge sub-well, Sn sub-well and self assembled quantum dots selected from the group consisting of Ge and Sn for IV-IV compound semiconductors.
- 2. The FET as described in claim 1, wherein any combination of the channel/barrier pairs lattice matched to InP substrate are selected from the group III-V compound semiconductor consisting of: (GaInAs, GaInAsP, AlGaInAs, GaAsSb, InP) /(AlInAs, AlInAsSb, AlGaPSb, AlGaAsSb, AlAsSb, AlGaInAsSb), (TlGaInP, TlInP, TlGaInAs)/(AlInAs, AlAsSb, AlInAsSb, AlGaAsSb) and (GaInAs, AlGaInAs, GaInAsP/InP).
- 3. The FET as described in claim 1, where in any combination of the channel/barrier pairs lattice matched to GaAs or Ge substrate are selected from the group III-V compound semiconductor consisting of: GaAs/(AlGaAs, GaInP, AlAs, AlInP). TlGaP/(AlGaAs, GaInP, AlAs, AlInP).
- 4. The FET as described in claim 1, wherein any combination of the channel/barrier pair lattice mismatched to InP substrate is selected from the group of III-V compound semiconductor consisting of: (GaInAs, GaInAsP, AlGaInAs, GaAsSb, InAsP) /(AlInAs, AlInAsSb, AlGaPSb, AlGaAsSb, AlAsSb, AlGaInAsSb), (TlGaInP, TlInP, TlGaInAs)/(AlInAs, AlAsSb, AlInAsSb, AlGaAsSb) and (GaInAs, AlGaInAs, GaInAsP/InP).
- 5. The FET as described in claim 1, wherein the channel/barrier pairs lattice mismatched to GaAs or Ge substrate are selected from the group III-V compound semiconductor consisting of: GaInAsN/(AlGaAs, GaInP, AlInP, AlAs), GaAs/AlGaPSb, (GaInAs, GaInAsP, AlGaInAs, GaAsSb, InAsP) /(AlGaAs, GaInP, AlInP, AlAs, AlInAs, AlInAsSb, AlGaPSb, AlGaAsSb, AlAsSb, AlGaInAsSb), (TlGaP, TlGaInP, TlInP, TlGaInAs)/(AlGaAs, GaInP, AlInP, AlAs, AlInAs, AlAsSb, AlInAsSb, AlGaAsSb) and (GaInAs, AlGaInAs, GaInAsP/InP).
- 6. The FET as described in claim 1, wherein any combination of the channel/barrier pairs are selected from the group III-V compound semiconductor consisting of: (GaSb, GaAsSb, GaInSb)/(AlGaAsSb, AlSb, AlSbAs, AlInAsSb), (InAs, InAsSb)/AlGaAsSb, AlSb, AlAsSb, AlGaSb, AlInAsSb), GaInAsSb/AlGaAsSb, AlSb, AlAsSb, AlGaSb, AlInAsSb), TlInAs/AlGaAsSb, AlSb, AlAsSb, AlGaSb, AlInAsSb), InSb/AlInSb.
- 7. The FET as described in claim 1, wherein any combination of the channel/barrier pairs deposited on substrate selected from the III-V semiconductor group consisting of Sapphire, GaN, SiC and AlN is selected from compound semiconductor family consisting of: GaN/AlGaN, GaInN/AlGaN, GaN/AlN, GaInN/AlN.
- 8. The FET as described in claim 1, wherein said buffer is selected from the group consisting of lattice matched, graded, metamorphic, and superlattice layers consisting of: lattice matched InP, AlGaInAs, AlInAs, AlSbAs, AlGaAsSb, AlInAsSb on InP substrate; AlInP, AlGaAs, AlAs, GaInP on GaAs substrate; metamorphic and graded AlInAs, AlGaInAs, AlSb, AlGaSb, AlSbAs, AlGaAsSb, AlInAsSb on InP substrate; and AlInAs, AlGaInAs, AlSbAs, AlGaAsSb, AlInAsSb, AlSb, AlGaSb on GaAs substrate; and AlN, GaN on Si substrate.
- 9. The field effect transistor (FET) as described in claim 1, further comprising a Schottky layer and a cap over said multiple channels and support said source, said drain, and said gate.
- 10. The FET as described in claim 9, wherein said cap layer is selected from the group consisting of: undoped GaInAs layer, undoped GaAs, doped GaInAs layer, doped GaAs layer, InAs layer for III-V semiconductor; and
doped Si, SiGe, Ge, and undoped Si, GaP for IV-IV compound semiconductors.
- 11. The FET as described in claim 9, further comprising layers of oxidation barrier between the Schottky barrier and the cap layer, selected from the group consisting of: undoped AlGaAs layer, undoped GaAs layer, undoped AlGaSb layer, undoped AlInAs layer, undoped layers of AlInAs and GaAs,
- 12. The FET as described in claim 1, wherein said the channel/barrier semiconductor pairs are selected from the group of II-VI/III-V, IV-IV/III-V, IV-IV/II-VI semiconductors consisting of Si/GaP, Si/ZnS, GaAs/ZnSe, and InSb/CdTe.
- 13. A field effect transistor (FET) comprising:
a substrate, a source, a gate and a drain; multiple channels in said substrate between said drain and said source to improve the linearity of drain current vs drain voltage characteristics when a gate voltage exceeding the threshold voltage is applied to the gate, said multiple channels having alternate layers of doped layer of first kind of semiconductor and undoped layers of second kind of semiconductor, said multiple channels are created in second kind semiconductor by doping the first kind semiconductor (charge supply layer), said doped layers having doping concentrations which decrease with depth from said gate; a Schottky layer over said multiple channels; and two undoped layers to cap the multiple channels and to support said source, said drain and said gate.
- 14. The FET as described in claim 13, wherein said FET is a HEMT, said multiple conducting channels being formed by 2-dimensional electron gas (2-DEG).
- 15. The FET as described in claim 13, wherein said multiple conducting channels being formed by two dimensional hole gas. (2-DHG)
- 16. The FET as described in claim 13, wherein said layers of first kind (charge supply layers, barriers, spacers) are selected from the group consisting of binary, ternary and quaternary compound semiconductor layers lattice matched to the substrate.
- 17. The FET as described in claim 13, wherein said layers of first kind (charge supply layers, barriers, spacers) are selected from the group consisting of binary, ternary and quaternary compound semiconductor layers lattice mismatched to the substrate.
- 18. The FET as described in claim 13, wherein said layers of second kind (2 DEG channels) are selected from the group consisting of binary, ternary and quaternary compound semiconductor layers lattice-mismatched to the substrate.
- 19. The FET as described in claim 13, wherein said second kind 2-DEG channels are selected from the group consisting of binary, ternary and quaternary compound semiconductor layers pseudomorphic to the substrate.
- 20. The FET described in claim 13, wherein said second kind 2-DEG channels are selected from the group consisting of binary and quaternary compound semiconductor layers lattice mismatched to the substrate.
- 21. The FET as described in claim 13, wherein the thicknesses of the barrier (charge supply, spacer) and the channel range from 2 nm to 10 nm.
- 22. The FET as described in claim 13, wherein said channels comprise of compounds of TlP, TlAs, TlSb, having: at least one of the said channel of TlInP, at least one of the said channel of TlGaInAs, and at least one of the said channel of TlGaInP
- 23. The FET as described in claim 13, wherein any combination of the first kind/second kind pairs lattice matched to InP substrate are selected from the group III-V compound semiconductor family consisting of: (GaInAs, GaInAsP, AlGaInAs, GaAsSb, InP) /(AlInAs, AlInAsSb, AlGaPSb, AlGaAsSb, AlAsSb, AlGaInAsSb), (TlGaInP, TlInP, TlGaInAs)/(AlInAs, AlAsSb, AlInAsSb, AlGaAsSb) and (GaInAs, AlGaInAs, GaInAsP/InP).
- 24. The FET as described in claim 13, wherein any combination of the first kind/second kind pairs lattice matched to the group consisting of GaAs and Ge substrate is selected from the group III-V compound semiconductor family consisting of: GaAs/(AlGaAs, GaInP, AlAs, AlInP), TlGaP/(AlGaAs, GaInP, AlAs, AlInP).
- 25. A FET as described in claim 13, wherein any combination of the first kind/second kind pairs lattice mismatched to InP substrate are selected from the group III-V compound semiconductor family consisting of: (GaInAs, GaInAsP, AlGaInAs, GaAsSb, InAsP) /(AlInAs, AlInAsSb, AlGaPSb, AlGaAsSb, AlAsSb, AlGaInAsSb), (TlGaInP, TlInP, TlGaInAs)/(AlInAs, AlAsSb, AlInAsSb, AlGaAsSb) and (GaInAs, AlGaInAs, GaInAsP/InP).
- 26. The FET as described in claim 13, wherein the first kind/second kind mismatched to substrate selected from the group consisting of GaAs and Ge are selected from the group III-V compound semiconductor family consisting of: GaInAsN/(AlGaAs, GaInP, AlInP, AlAs), GaAs/AlGaPSb, (GaInAs, GaInAsP, AlGaInAs, GaAsSb, InAsP) /( AlGaAs, GaInP, AlInP, AlAs, AlInAs, AlInAsSb, AlGaPSb, AlGaAsSb, AlAsSb, AlGaInAsSb), (TlGaP, TlGaInP, TlInP, TlGaInAs)/( AlGaAs, GaInP, AlInP, AlAs, AlInAs, AlAsSb, AlInAsSb, AlGaAsSb) and (GaInAs, AlGaInAs, GaInAsP/InP).
- 27. A FET as described in claim 13, wherein any combination of the first kind/second kind pairs are selected from the group III-V compound semiconductor family consisting of: (GaSb, GaAsSb, GaInSb)/(AlGaAsSb, AlSb, AlSbAs, AlInAsSb), (InAs, InAsSb)/AlGaAsSb, AlSb, AlAsSb, AlGaSb, AlInAsSb), GaInAsSb/AlGaAsSb, AlSb, AlAsSb, AlGaSb, AlInAsSb), TlInAs/(AlGaAsSb, AlSb, AlAsSb, AlGaSb, AlInAsSb), InSb/AlInSb.
- 28. The FET as described in claim 13, wherein any combination of the first kind/second kind pairs deposited on the group consisting of Sapphire, GaN, SiC and AlN substrate is selected from the group III-V compound semiconductor family consisting of: GaN/AlGaN, GaInN/AlGaN, GaN/AlN and GaInN/AlN.
- 29. The FET as described in claim 13, wherein each said channels layer is selected from the group consisting of uniformly composition, pseudomorphic composition, InAs sub-well, TlP sub-well and self assembled quantum dots.
- 30. The FET as described in claim 13, wherein the said numbers of channels are variable, said number of channels is more than two.
- 31. The FET as described in claim 13, wherein the doping and the number of channels are variable, wherein
the said concentration of 2-DEG/2-DHG in the channels is distributed to give higher gain at pinch-off, and said concentration of 2-DEG/2-DHG in the channels is distributed to give higher gain at gate voltage of 0V, and said sheet concentration in the channels is distributed to give uniform Ft with gate voltage variation, said sheet concentration in the channels is distributed to give uniform Fmax with gate voltage variation.
- 32. The FET as described in claim 13, wherein the doping in each charge supply layer is selected to have a specific design to give overall 2DEG/2DHG distribution of 1/x3 for the multi-channel device, where x is the depth from the gate.
- 33. The FET as described in claim 13, wherein the doping in wide band gap layer is selected from the group consisting of spike, delta, and planar-doping,
wherein the said location of the spike placed in wide band gap layer, and the number of spikes are variable, and wherein the said doping spikes is placed asymmetrically in the layer, and the spikes is placed symmetrically in the layer.
- 34. The FET as described in claim 13, further comprising an undoped buffer layer between said substrate and said multiple channels.
- 35. The FET as described in claim 34, further comprising the a buffer selected from the group consisting of a step graded, linear graded and superlattice buffer layer
- 36. The FET as described in claim 34, wherein said buffer is selected from the group consisting of InP, AlGaInAs, AlInAs, AlSbAs, AlGaAsSb, AlInAsSb on InP substrate,
- 37. The FET as described in claim 34, wherein the said buffer is selected from the group consisting of AlInP, AlGaAs, AlAs, GaInP on GaAs substrate.
- 38. The FET as described in claim 34, wherein said buffer is selected from the group consisting of metamorphic and graded AlInAs, AlGalnAs, AlSb, AlGaSb, AlSbAs, AlGaAsSb, AlInAsSb on InP substrate.
- 39. The FET as described in claim 34, wherein said buffer is selected from the group consisting of metamorphic and graded AlInAs, AlGaInAs, AlSbAs, AlGaAsSb, AlInAsSb, AlSb, AlGaSb on GaAs substrate.
- 40. The field effect transistor (FET) as described in claim 13, further comprising a Schottky layer and a cap over said multiple channels to support said source, said drain, and said gate.
- 41. The FET as described in claim 40, wherein said cap layer is selected from the group consisting of: undoped GaInAs layer, doped GaInAs layer, doped GaAs layer, InAs layer.
- 42. The FET as described in claim 40, further comprising layers of oxidation barrier between the Schottky barrier and the cap layer, selected from the group consisting of: undoped AlGaAs layer, undoped GaAs layer, undoped AlGaSb layer, undoped AlInAs layer, undoped layers of AlInAs and GaAs,
- 43. The FET as described in claim 40, wherein said doped cap layer is recessed for deposition of gate metal and to provide uniform threshold voltage by direct deposition of gate metal
- 44. The FET as described in claim 13, wherein said the first kind semiconductor and the second type semiconductor are selected from the group II-VI semiconductors family consisting of ZnSe, ZnS, CdTe, and CdS.
- 45. The FET as described in claim 13, wherein said the first kind semiconductor and the second type semiconductor are selected from the group of II-VI/III-V, IV-IV/III-V, IV-IV/II-VI semiconductors family consisting of Si/GaP, Si/ZnS, GaAs/ZnSe, and InSb/CdTe.
- 46. The FET as described in claim 13, wherein alternate layers of first kind of semiconductor and a second kind of semiconductor forming heterojunction are selected from the group of IV-IV semiconductor family consisting of Si, Ge, Sn and C and
said multiple channels are created in first kind semiconductor by doping the second kind semiconductor (charge supply layer).
- 47. The FET as described in claim 46, wherein said any combination of lattice first/second kind pairs are selected from the group of IV-IV semiconductor family consisting of SiGe/Si, GeC/Si, SiGeC/Si, GeC/Si, GeSn/Si, Si/SiGe, Si/SiC, SiGe/SiC, Si/SiGeC, SiGe/SiGeC.
- 48. The FET as described in claim 46, wherein the channels are selected from the group consisting of Ge sub-well, Sn sub-well and self assembled quantum dots; and the charge supply layer is selected from the group consisting of delta doped, spike doped, and planar doped.
- 49. A FET as described in claim 46, further comprising a cap over said FET multiple channels and support said source, said drain, and said gate.
- 50. A FET as described in claim 46, wherein the cap provides Schottky barrier selected from the group consisting of Si and GaP.
- 51. The FET as described in claim 1, wherein said FET is an Insulated Gate Field Effect Transistor (IGFET).
- 52. The IGFET as described in claim 51, wherein alternate layers of first kind of semiconductor and a second kind of semiconductor forming heterojunction are selected from the group of semiconductors,
said multiple channels of 2-dimension gas are created in second kind semiconductor by doping the first kind semiconductor (charge supply layer), said multiple channels of 2-DEG or 2-DHG are created in second kind semiconductor by selective implantation into both first and second kind semiconductor, and said multiple channels are created in second kind semiconductor by doping with N- or P-type conductivity and using undoped second kind semiconductor,
- 53. The IGFET as described in claim 51, wherein said any combination of first/second kind pairs are selected from the family of group of III-V, IV-IV, II-VI, III-V/II-VI, and III-V/IV-IV semiconductor.
- 54. The IGFET as described in claim 51, further comprising a cap over said multiple channels and support said source, said drain, and said gate.
- 55. The IGFET as described in claim 51, wherein the cap is the insulator, in which the said insulator is processed by means selected from the group consisting of thermal growth and deposition.
- 56. The IGFET as described in claim 51, wherein the insulator for said FET is thermally grown to form oxides/nitrides selected from the group consisting of Si, InP, GaAs, AlAs, AlGaAs, AlAsSb.
- 57. The IGFET as described in claim 51, wherein the insulator is deposited and said insulator is selected from the group consisting of SiO2, Si3N4, Al2O3, and AlN.
- 58. The IGFET as described in claim 51, wherein a complementary FET is be formed by selective implantation using any combination of first/second kind undoped pairs, selected from the family of group consisting of III-V, IV-IV, II-VI, III-V/II-VI, and III-V/IV-IV semiconductor.
- 59. The FET as described in claims 1, wherein said substrate is selected from the group consisting of Si, GaAs, InP, GaN, AlN, SiC and Sapphire
- 60. The FET as described in claim 1, wherein the devices are grown via the group consisting of MBE/CBE/MEE/GSMBE/VPE/OMVPE/UHVCVD.
BACKGROUND OF THE INVENTION
[0001] This is a continuation-in-part application of U.S. patent application Ser. No. 09/618,884, filed Jul. 18, 2000, and amended in Jan. 11, 2002. This invention relates to field effect transistors, in particular to a multiple channel, ultra-linear field effect transistors.
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
09618884 |
Jul 2000 |
US |
Child |
10176787 |
Jun 2002 |
US |