This application claims the benefit of Korean Patent Application No. 10-2004-0108155, filed on Dec. 17, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and an ultra thin film silicon on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) having a recessed source/drain structure, and a method of fabricating the same.
2. Description of the Related Art
Recently, with the increase of demand for a low power consumption, a high integration, an ultra high speed device characteristics of semiconductor devices, and the like, it is also required that a size of a MOS transistor employed in various semiconductor devices be reduced. In specific, it is required that a channel length of a MOS transistor, a depth of a source/drain junction, and a thickness of a gate insulating layer be reduced. However, as widely known, when the channel length is excessively reduced, there occurs a short channel effect. Further, even in the device having a same size, a high performance of the device characteristics must be implemented through an increase of a drive current and a reduction of a leakage current.
However, with the device size being reduced down to deep-submicron of approximately 100 nm or below, typical short channel effects become more serious problems. For example, when phenomenons such as punch-through, drain induced barrier lowering (DIBL), and gate induced drain leakage current (GIDL), and the like, a roll-off characteristic of a threshold voltage occurs, and an on/off ratio of a drain current is reduced.
In order to alleviate the short channel effect as above, it is necessary to reduce a depth of a source/drain junction. However, there is a limitation to form the ultra shallow junction by using a high energy ion implantation method or a high temperature diffusion process, which is now widely employed. Various methods have been proposed in order to solve the problems. One of the methods involves a low energy ion implantation and a spike rapid thermal processing, in which an ion implantation energy is decreased to a minimum and then, a thermal processing is performed in short time. Another one of the methods is to prevent a channel leakage current flowing below a channel region being little influential in the control of a gate region in a bulk silicon device. The method can be easily implemented using an SOI substrate. The use of the SOI substrate also provides a merit of easily forming the ultra shallow junction in addition to the effect of preventing a channel leakage current.
However, the methods both have unavoidable problems. That is, when a junction is very shallow, or a thin film is very thin in thickness, a resistance of a source/drain region is increased that much. As a result, it occurs a serious reduction of a drive current, one of the important elements in scaling of devices. Furthermore, even in an elevated source/drain SOI MOSFET having an elevated source/drain region formed in order to reduce a high resistance in a source/drain region when an ultra thin film SOI substrate is used, there still occurs a problem of a high resistance in a source/drain extension region for a lightly doped drain (LDD) structure. The problem becomes more serious with an integration of a device being increased.
The present invention provides an ultra thin film silicon on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) having a recessed source/drain structure being capable of suppressing a resistance increase of a source/drain region, thereby preventing a reduction of a drive current due to a resistance increase of the source/drain region.
The present invention also provides a method of fabricating an ultra thin film SOI MOSFET having a recessed source/drain structure.
According to an aspect of the present invention, there is provided an ultra thin film SOI MOSFET including a semiconductor substrate; a buried insulating layer disposed on the semiconductor substrate, and formed recessed except for a center portion thereof; an ultra thin film single crystalline silicon layer pattern disposed on the recessed buried insulating layer; a gate stack disposed on the ultra thin film single crystalline silicon layer pattern, and including a gate insulating layer pattern and a gate conductive layer pattern, which are sequentially stacked; a gate spacer layer disposed on sidewalls of the gate stack; and a recessed source/drain region disposed on the recessed buried insulating layer, and formed to overlap a bottom surface portion of the ultra thin film single crystalline silicon layer pattern, which does not overlap the center portion of the recessed buried insulating layer.
The semiconductor substrate, the recessed buried insulating layer, and the ultra thin film single crystalline silicon layer pattern may constitute an SOI substrate. The recessed buried insulating layer may be an oxide layer. End portions of the ultra thin film single crystalline silicon layer pattern may be formed in a direction normal to sidewalls of the gate spacer layer. The recessed source/drain region may be a polycrystalline silicon layer doped with high concentration impurities.
The present invention may further include a hard mask layer pattern disposed on the gate conductive layer pattern. In this case, the hard mask layer pattern may have a structure in which a silicon oxide layer pattern and a silicon nitride layer pattern are sequentially stacked. Further, the present invention may further include a metal silicide layer disposed on an exposed surface of the recessed source/drain region.
According to another aspect of the present invention, there is provided a method of fabricating an ultra thin film SOI MOS transistor including preparing an SOI substrate formed by sequentially stacking a semiconductor substrate, a buried insulating layer, and a single crystalline silicon layer; removing the single crystalline silicon layer by a predetermined thickness, thereby forming an ultra thin film single crystalline silicon layer; forming a gate stack on the ultra thin film single crystalline silicon layer; forming a gate spacer layer on sidewalls of the gate stack; removing an exposed portion of the ultra thin film single crystalline silicon layer, being not covered by the gate stack and the gate spacer layer, thereby forming an ultra thin film single crystalline silicon layer pattern disposed below the gate stack and the gate spacer layer; partially removing the buried insulating layer, thereby forming a recessed buried insulating layer, which is recessed at a rest portion except for a center portion below the ultra thin film single crystalline silicon layer pattern; and forming a source/drain region on the recessed buried insulating layer.
The buried insulating layer may be an oxide layer. The operation of forming the ultra thin film single crystalline silicon layer may include performing an oxidation process on the single crystalline silicon layer; and removing an oxide layer formed in an upper portion of the single crystalline silicon layer by the oxidation process. In this case, the oxidation process and the oxide layer removing process may be performed using a dry oxidation process and a wet etch process respectively. The prevent invention may further include channel-doping for the ultra thin film single crystalline silicon layer to control a threshold voltage and reduce a short channel effect.
The gate stack may be formed to have a structure of a gate insulating layer pattern and a gate conductive layer pattern, which are sequentially stacked. In this case, the gate stack may further include a hard mask layer pattern formed on the gate conductive layer pattern. The gate insulating layer pattern may be formed of a silicon thermal oxide layer or a high-k insulating layer, the gate conductive layer pattern may be formed of a polycrystalline silicon layer or a metal layer, and the hard mask layer pattern may be formed of a silicon oxide layer and a silicon nitride layer.
The operation of forming the gate spacer layer may include forming an insulating layer for a gate spacer layer on the overall surface of the resultant structure having the gate stack; and performing an anisotropic etch process on the insulating layer, thereby exposing an upper surface of the gate stack and a portion of the surface of the thin film single crystalline silicon layer.
In this case, the insulating layer for the gate spacer layer may be formed using a silicon nitride layer. The thin film single crystalline silicon layer pattern may be formed performing an anisotropic etch process on the thin film single crystalline silicon layer exposed by the gate stack and the gate spacer layer. The recessed buried insulating layer may be formed by performing a wet etch process on the buried insulating layer. In this case, the wet etch process may be performed using a diluted HF solution or a BOE solution as an etch solution.
The operation of forming the source/drain region may include forming a conductive layer on an overall surface of the resultant structure having the recessed buried insulating layer; forming an etch mask layer pattern on the conductive layer to expose an upper surface of the gate stack and the conductive layer around the gate stack; performing an etch process using the etch mask layer pattern as an etch mask, thereby removing the exposed portion of the conductive layer; and removing the etch mask layer pattern.
In this case, the conductive layer may be formed of a polycrystalline silicon layer doped with high concentration impurities. The operation of forming the polycrystalline silicon layer may be performed using a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, or an atomic layer deposition (ALD) method. The conductive layer may be formed of an amorphous silicon layer or a single crystalline silicon layer formed by an epitaxy growth method. The etch mask layer pattern may be formed of a floating oxide layer. In this case, the operation of removing the etch mask layer pattern may be performed using a wet etch process on the floating oxide layer. The operation of removing the exposed portion of the conductive layer by the etch process using the etch mask layer pattern as an etch mask may be performed by an anisotropic etch process. The present invention may further include forming a metal silicide layer on the source/drain region.
The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout the specification.
Referring to
A gate stack is formed on the ultra thin film single crystalline silicon layer pattern 103b by sequentially stacking a gate insulating layer pattern 111, a gate conductive layer pattern 121, and a hard mask layer pattern 130a. The hard mask layer pattern 130a is composed of two layers including a lower silicon oxide layer pattern 131a and an upper silicon nitride layer pattern 132a. Alternatively, the hard mask layer pattern 130a may have a structure of a single layer or three layers or more. The gate stack is vertically disposed relative to the center portion of the recessed buried oxide layer 102a. Gate spacer layers 141 are disposed on the sidewalls of the gate stack respectively.
Source/drain regions 151 are disposed on the recessed portions of the recessed buried oxide layer 102a respectively. The recessed structure of the source/drain region 151 is composed of a polycrystalline silicon layer doped with high concentration impurities. The source/drain region 151 having the recessed structure contacts the bottom surface of the ultra thin film single crystalline silicon layer pattern 103b, particularly the bottom surface portion horizontally protruded from the center portion of the recessed buried oxide layer 102a. A metal silicide layer 170 is disposed on the recessed source/drain regions 151.
The ultra thin film SOI MOSFET having the recessed source/drain regions structured as above can suppress a short channel effect and reduce the resistance of the source/drain regions. That is, an inversion layer generated when a bias above a threshold voltage is applied to the gate conductive layer pattern 121 or a channel is formed inside the ultra thin film single crystalline silicon layer pattern 103b below the gate insulating layer 111. The inversion layer or the channel cannot be formed deeper because of the presence of the center portion of the recessed buried oxide layer 102a even though the recessed source/drain regions 151 is great in thickness. Thus, the short channel effect can be suppressed. Therefore, since the thickness of the recessed source/drain regions 151 does not affect the depth of the inversion layer or the channel, the thickness of the recessed source/drain regions 151 doped with high concentration impurities can be formed sufficiently great, thereby reducing the resistance of the recessed source/drain regions 151.
Hereinafter, a method of fabricating the SOI MOSFET structured as above will be described in detail with reference to
As shown in
As shown in
As shown in
Then, an etch process is performed using the photoresist layer pattern or the electron beam resist layer pattern as an etch mask, thereby sequentially removing the exposed portions of the hard mask layer 130, the gate conductive layer 120, and the gate insulating layer 110. Then, the photoresist layer pattern or the electron beam resist layer pattern is removed, thereby forming the gate stack. The etch process uses an anisotropic dry etch process such as reactive ion etching (RIE). At this time, the thin film single crystalline silicon layer 103a may be lost by the etch depending on the kind of an etch gas to be used. For the reason, an etch gas having a high etch selectivity with respect to the gate insulating layer 110 may be used during the etch of the gate conductive layer 120 in order to avoid the problem. When the gate stack is formed by the method as above, the surface of the thin film single crystalline silicon layer 103a except for the surface portion covered by the gate stack is partially exposed.
As shown in
As shown in
As shown in
Then, as shown in
First, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
As described above, according to the ultra thin film SOI MOSFET having the recessed source/drain structure of the present invention, since the inversion layer or the channel is formed inside the ultra thin film single crystalline silicon layer pattern under the gate insulating layer, and the center portion of the recessed buried oxide layer exists thereunder, the inversion layer or the channel cannot be formed deeper. Therefore, even though the source/drain extension region is formed greater in depth, the generation of a short channel effect can be suppressed. As such, since the depth of the inversion layer or the channel is not affected by the thickness of the recessed source/drain region, the thickness of the recessed source/drain region doped with high concentration impurities must be sufficiently increased, thereby reducing a resistance in the recessed source/drain region.
Furthermore, according to the method of fabricating the ultra thin film SOI MOSFET of the present invention, the ultra thin film SOI MOSFET can be easily fabricated to provide the advantages while using existing processes of fabricating bulk semiconductor devices.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.
Number | Date | Country | Kind |
---|---|---|---|
10-2004-0108155 | Dec 2004 | KR | national |