Patent Application
20070249128
This invention relates to integrated circuit fabrication methods, and more particularly to methods of fabricating dielectric layers for integrated circuits.
Integrated circuits are widely used for consumer, commercial and other applications. As is well known to those having skill in the art, dielectric (insulating) layers have many applications in integrated circuits. For example, in a Shallow Trench Isolation (STI) process and structure, STI trenches are formed in a surface of an integrated circuit substrate and filled with dielectric. Microelectronic devices, such as integrated circuit Field Effect Transistors (FETs) are formed between adjacent spaced apart STI trenches. Moreover, dielectric layers may be used on a face of an integrated circuit substrate, to electrically insulate multiple levels of conductors, such as metal, on an integrated circuit substrate from one another and/or from the substrate. The first dielectric layer between the semiconductor substrate face and a first metal layer may be referred to as a Pre-Metal Dielectric (PMD) layer, whereas the dielectric layer(s) between metal layers may be referred to as Inter-Layer Dielectric (ILD) layer(s).
It is also known that the carrier mobility in the channel region of a field effect transistor can be changed by applying stress to the channel region. In particular, tensile stress may be applied to field effect transistors, such as an n-channel field effect transistor (NFET), to increase the performance thereof. Tensile stress may be applied to a channel region of a field effect transistor by filling adjacent STI trenches with a material that produces tensile stress in the trenches, thereby imparting tensile stress to the charnel. Tensile stress also may be provided by using a PMD material that provides tensile stress.
It is known to provide a dielectric material under tensile stress by performing Subatmospheric Chemical Vapor Deposition (SACVD) of ozone-tetraethoxysilane (O3-TEOS). The SACVD O3-TEOS may be used to fill STI trenches and/or as a PMD layer. SACVD of TEOS is described, for example, in a publication to Shareef et al. entitled Subatmospheric chemical vapor deposition ozone/TEOS process for SiO2 Trench filling, J. Vac. Sci. Technol. B 13(4), July/August 1995, pp. 1888-1892. SACVD of O3-TEOS may be accomplished using a High Aspect Ratio Process (HARP) to provide good gap filling of STI trenches and/or PMD layers at high aspect ratios, such as a 7:1 aspect ratio, for highly integrated devices of about 45 nm or less, as described in an article on the Applied Materials® website, entitled Applied Producer HARP, appliedmaterials.com/products/harp.html?menuID=1—3—6.
Notwithstanding these developments, it may be desirable to further increase the amount of tensile stress that may be produced by SACVD O3-TEOS.
Dielectric layers are formed on a substrate, according to some embodiments of the present invention, by performing Subatmospheric Chemical Vapor Deposition (SACVD) of ozone-tetraethoxysilane (O3-TEOS) to form a layer of O3-TEOS on the substrate, and treating the layer of O3-TEOS with ultraviolet (UV) radiation. The UV radiation treatment can increase the tensile stress in the O3-TEOS layer by reducing the amount of water in the layer. Moreover, the UV treatment may also reduce the amount of silanol in the O3-TEOS layer, which can also increase reliability of the device.
In some embodiments, treating the layer of O3-TEOS with UV radiation is performed between about 400° C. and about 800° C. In other embodiments, UV treatment time between about 200 seconds and about 10 minutes is used. In yet other embodiments, the UV treatment is performed sufficiently to reduce a weight percent of water in the O3-TEOS to below about 2%. In still other embodiments, the UV treatment is also performed sufficiently to reduce a weight percent of silanol in O3-TEOS to below about 6%. Moreover, in some embodiments, the layer of O3-TEOS is chemical-mechanical polished, and treating the layer of O3-TEOS with UV radiation may be performed before and/or after the chemical-mechanical polishing.
Integrated circuits may be fabricated according to some embodiments of the present invention, by forming in a face of an integrated circuit substrate, spaced apart Shallow Trench Isolation (STI) trenches. SACVD of O3-TEOS is then performed to form a layer of O3-TEOS in the STI trenches. The O3-TEOS layer in the STI trenches is treated with UV radiation. In other embodiments, SACVD of O3-TEOS is again performed on the face of the integrated circuit substrate to form a layer of O3-TEOS on the face of the integrated circuit substrate. The layer of O3-TEOS on the face of the integrated circuit is treated with UV radiation. Parameters of the UV treatments may be as described above.
In some embodiments, spaced apart source and drain regions and a channel region therebetween, are formed in the integrated circuit substrate between the spaced apart STI trenches, and the UV treatment of the layer of O3-TEOS in the STI is performed sufficiently to increase stress in the channel region that is imparted by the layer of O3-TEOS in STI trenches. Moreover, in other embodiments, the layer of )3-TEOS on the face of the integrated circuit substrate is UV treated sufficiently to increase stress in the channel region that is imparted by the layer of O3-TEOS on the face of the substrate. In some embodiments, the UV treating of the O3-TEOS in the STI trenches and on the face of the integrated circuit substrate is performed sufficiently to increase stress in the channel region that is imparted by the layer of O3-TEOS in the STI trenches and by the layer of O3-TEOS on the face of the substrate by at least about 30 megapascal (MPa). Parameters of the UV treatments may be as described above.
In other embodiments of the present invention, tensile stress in a channel region of an integrated circuit field effect transistor that is imparted by a first SACVD O3-TEOS layer in a trench isolation region adjacent the field effect transistor and by a second SACVD O3-TEOS layer on the field effect transistor is increased by treating the first and/or second layers of O3-TEOS with UV radiation. In some embodiments, both the first and second layers of O3-TEOS are treated with UV radiation. Parameters of the UV treatments may be as described above.
The invention will be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, the disclosed embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity unless express so defined herein. Moreover, each embodiment described and illustrated herein includes its complementary conductivity type embodiment as well. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being “on”, “connected to” and/or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” and/or “directly coupled to” another element or layer, there are no intervening elements or layers present. As used herein, the term “and/or” may include any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be used to distinguish one element, component, region, layer and/or section from another region, layer and/or section. For example, a first element, component, region, layer and/or section discussed below could be termed a second element, component, region, layer and/or section without departing from the teachings of the present invention.
Spatially relative terms, such as “beneath”, “below”, “lower”, “above”, “upper” and the like, may be used herein for ease of description to describe an element and/or a features relationship to another element(s) and/or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” and/or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular terms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Example embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, may be expected. Thus, the disclosed example embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein unless expressly so defined herein, but are to include deviations in shapes that result, for example, from manufacturing. Thus. the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention, unless expressly so defined herein.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Still referring to
It will be understood by those having skill in the art that the STI regions 108, the source/drain regions 110/112, the source/drain extensions 110a/112a and the gate structure 120 may be fabricated in any arbitrary order or sequence relative to one another, which may vary according to different process recipes. Moreover, all of the regions described above need not be included. For example, a trench liner 104, source/drain extensions 110a/112a, various layers of the gate structure 120 and/or gate spacers 128 may be omitted according to various FET designs.
As also illustrated in
In some embodiments, UV treating the layer of O3-TEOS 206 in the STI region 108 may be performed at between about 400° C. and about 800° C. In other embodiments, treatment with the UV radiation 300 may be performed for between about 200 seconds and about 10 minutes. As will be described in more detail below, it has been found, according to some embodiments of the present invention, that treating the layer of O3-TEOS 206 in the STI regions 108 with UV radiation 300 may be performed sufficiently to reduce a weight percent of water in the O3-TEOS to below about 2%. In other embodiments, the UV treatment may also be performed sufficiently to reduce a weight percent of silanol in the O3-TEOS to below about 6%.
In some embodiments of the present invention, the UV treatment 300 may take place in a Tokyo Electron UV tool, using a UV wavelength of about 172 nm and a power of about 50 mW/cm2. Other specifications for the UV tool are shown in the following Table:
However, it will be understood by those having skill in the art that other UV tools with other specifications also may be used according to embodiments of the present invention
It will be understood by those having skill in the art that the UV treatment 300 of
In some embodiments of the invention, in forming the O3-TEOS 206 in the STI region 108, a blanket layer of O3-TEOS is deposited by SACVD, and then the layer of SACVD O3-TEOS is Chemical-Mechanical Polished (CMP). In these embodiments, the layer of O3-TEOS may be treated with UV radiation before and/or after the CMP. For example,
As was the case with the STI layer 206, the PMD layer 430 may also be formed by CMP a layer of O3-TEOS on the face of the integrated substrate. In these embodiments, treating the layer of O3-TEOS on the face of the integrated circuit substrate with UV radiation may be performed before and/or after the CMP. For example, as shown in
It will be understood by those having skill in the art that although
Accordingly,
Without wishing to be bound by any theory of operation, it appears that UV treatment(s) according to some embodiments of the present invention can reduce moisture present in an SACVD O3-TEOS film, and can reduce or prevent additional moisture from being incorporated into SACVD O3-TEOS film, which can increase the tensile strength and/or increase the reliability of the film. In particular, an SACVD O3-TEOS film may include (Si—O)x-Hy therein. The combination of UV radiation and heat can provide outgassing of H2O and Si—OH. This can cause further shrinkage in the SACVD O3-TEOS film, which can increase tensile stress.
It is known to use High Density Plasma (HDP) CVD technology to deposit O3-TEOS. HDPCVD may be a very slow and expensive process, but may be practically free of moisture. SACVD can be faster and cheaper, but can have a significant amount of moisture incorporated in the film, due to incomplete reaction of the chemical precursors. Some embodiments of the present invention can reduce the moisture in the film to an insignificant level. Moreover, the UV treatment can cause the remaining moisture in the film to react to form stable products, so the film will no longer incorporate significant moisture.
In the drawings and specification, there have been disclosed embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
