Patent Application
20150008488
The present invention generally relates to semiconductor devices, and more particularly to field effect transistor devices including replacement metal gate structures, and a method for making the same.
Complementary Metal-oxide-semiconductor (CMOS) technology is commonly used for fabricating field effect transistors (FETs) as part of advanced integrated circuits (IC), such as CPUs, memory, storage devices, and the like. At the core of planar FETs, a channel region is formed in an n-doped or p-doped semiconductor substrate on which a gate structure is formed. The overall fabrication process is well known in the art, and includes forming a gate structure over a channel region connecting a source region and a drain region within the substrate on opposite ends of the gate, typically with some vertical overlap between the gate and the source-drain region.
Scaling down of transistor dimensions requires a high-k metal gate to reduce gate leakage and improve device performance. A polycristalline silicon material, commonly referred as polysilicon or poly, is normally used in the gate manufacturing process. Polysilicon exhibits high thermal resistivity, which makes a polysilicon gate resistant to high temperature processes such as high temperature annealing. The replacement of a polysilicon gate with a metal gate electrode is frequently used in CMOS fabrication to address problems related to high temperature processing on metal materials. This process is known as replacement metal gate (RMG) or gate last process. A RMG process includes the formation of a dummy polysilicon gate structure, commonly referred to as a dummy poly gate or simply a dummy gate, in the semiconductor substrate. The device manufacturing may continue until deposition of an interlayer dielectric (ILD) layer. After the ILD layer deposition, the dummy gate may be removed and replaced with a high-k metal gate.
Known RMG technology usually involves additional processes, such as chemical mechanical polishing (CMP) of the ILD layer that may result in non-uniform gate height, in turn affecting device performance. For instance, poor control of combined poly open and replacement metal (aluminum or other) CMP during the RMG process results in shorter gate height.
A method for RMG process that allows precise control of gate height within the semiconductor device and in turn, of the corresponding RMG contact with source-drain regions is desirable.
According to an embodiment of the present invention, a method of manufacturing a semiconductor structure includes: forming a chemical mechanical polish (CMP) stop layer above a dummy gate and above a top surface of a semiconductor substrate. A first ILD layer is formed and then removed until the CMP stop layer located above the gate structure is reached.
The method further includes: forming a raised source drain region in a semiconductor substrate adjacent to a dummy gate and forming a chemical mechanical polish (CMP) stop layer over the gate structure and above a top surface of the semiconductor substrate. A first ILD layer is formed above the CMP stop layer. The first ILD layer is removed to a portion of the CMP stop layer located above the gate structure and the portion of the CMP stop layer located above the gate structure is removed to expose the dummy gate. The method further includes: replacing the dummy gate with a metal gate and polishing the metal gate until a top portion of the CMP stop layer located above the raised source-drain region is reached. In a related aspect of the invention, a second ILD layer is formed above the structure and contacts are formed within the second ILD layer, the contacts extending from a top surface of the second ILD layer to the raised source-drain region.
According to another embodiment of the present invention, a semiconductor device includes: a metal gate structure located on a top surface of a semiconductor substrate between a raised source-drain region, a CMP stop layer located on top of the raised source-drain region and above the top surface of the semiconductor substrate and a portion of an interlayer dielectric (ILD) layer positioned on a top of the CMP stop layer and between a substrate contact and a gate contact. The device further includes: two or more gate structures where a height of one metal gate structure is substantially similar to the height of another metal gate structure.
The features and advantages of the present disclosure will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. The various features of the drawings are not to scale as the illustrations are for clarity in facilitating one skilled in the art in understanding the disclosure in conjunction with the detailed description. In the drawings:
The drawings are not necessarily to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like numbering represents like elements.
Exemplary embodiments now will be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. This invention may, however, be modified in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this invention to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessary obscuring the presented embodiments.
One method of manufacturing a semiconductor structure is described in detail below by referring to the accompanying drawings in
Referring to
The semiconductor structure 100 may further include a plurality of n-channel field effect transistor (n-FET) devices and p-channel field effect transistor (p-FET) devices. The n-FET and p-FET devices may have a gate dielectric 106 which may be formed over the semiconductor substrate 102 by any deposition method known in the art, for example, by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), high-density CVD (HDCVD), physical vapor deposition (PVD), plating, sputtering, evaporation, and chemical solution deposition of a dielectric material. Gate dielectric 106 may be formed through oxidizing a top surface of substrate 102 as well. In one embodiment, the gate dielectric 106 may include a high-k dielectric material having a dielectric constant greater than, for example, 3.9, which is the dielectric constant of silicon oxide.
The devices formed as discussed below, such as the structure 100, may be an n-FET or p-FET device by doping the substrate as is known in the art. The devices discussed below are generically referred to as FET devices.
The semiconductor structure 100 may further include a dummy gate 108. The dummy gate 108 may be formed using conventional techniques known in the art. For example, the dummy gate 108 may be formed by depositing a blanket layer of polysilicon. In some embodiments, multiple gates may be formed above a single channel region when fabricating multiple transistor structures having shared source-drains regions (not shown).
The semiconductor structure 100 may further include a hard mask layer 112 located above the dummy gate 108. The hard mask layer 112 may be formed by any deposition method known in the art including, for example, by CVD, PECVD, HDCVD, PVD, plating, sputtering, evaporation, and chemical solution deposition. The hard mask layer 112 may be made of any known semiconductor material including, but not limited to: silicon nitride, silicon oxy-nitride and silicon carbide.
The dummy gate 108 may further include one or more dielectric spacers, for example spacers 110. The spacers 110 may be formed by depositing or growing a conformal dielectric layer, followed by an anisotropic etch that removes the dielectric from the horizontal surfaces of the semiconductor structure 100, while leaving it on the sidewalls of the dummy gate 108. In a RMG process flow the spacers 110 may remain on the sidewalls of a dummy gate 108. In one embodiment, the spacers 110 may include any suitable dielectric material such as silicon nitride. In one embodiment, the spacers 110 may have a horizontal width, or thickness, ranging from about 3 nm to about 30 nm. The spacers 110 may include a single layer; however, the spacers 110 may include multiple layers of dielectric material. The spacers 110 may be positioned along the sidewalls of the dummy gate 108 and separate a subsequently formed metal gate from an epitaxial embedded source-drain region, as shown in
In one embodiment of the present disclosure, source-drain recesses 104 may be formed adjacent to a channel region 103 in the semiconductor substrate 102. The source-drain recesses may be formed by etching the semiconductor substrate 102 using a dry etching technique. Initial source-drain recesses in the semiconductor substrate 102 may have a U shape (not shown), which may then be processed into the present sigma shape shown in
Referring now to
For example, the epitaxial doped material used to form RSD region 204 in a p-FET device may include a silicon-germanium (SiGe) material, where the atomic concentration of germanium (Ge) may range from about 10-80%. In an embodiment of the present disclosure, the concentration of germanium (Ge) may be about 25-50%. The epitaxial doped material forming the RSD region 204 may provide a compressive stress to the channel region 103. More specifically, the epitaxial doped material forming the RSD region 204 may induce a compressive stress in the channel region 103 of the p-FET device which may enhance carrier mobility and increase drive current. Thus, the RSD region 204 may include enhanced carrier mobility provided by the epitaxial doped material. P-type dopants such as boron may be incorporated into the epitaxial doped material by in-situ doping. The percentage of boron may range from 1E19cm−3 to 2E21cm−3, preferably 1E20cm−3 to 1E21cm−3.
For example, the epitaxial doped material used to form RSD region 204 in an n-FET device may include a carbon-doped silicon (Si:C) material, where the atomic concentration of carbon (C) may range from about 0.4-3.0%. The epitaxial doped material forming the RSD region 204 may provide a tensile stress to the channel region 103. More specifically, the epitaxial doped material forming the RSD region 204 may induce a tensile stress in the channel region 103 of the n-FET device which may enhance carrier mobility and increase drive current. Thus, the RSD region 204 may include enhanced carrier mobility provided by the epitaxial doped material. N-type dopants such as phosphorus or arsenic may be incorporated into the epitaxial doped material by in-situ doping. The percentage of phosphorus or arsenic may range from 1E19cm−3 to 2E21cm−3, preferably 1E20cm−3 to 1E21cm−3.
In another embodiment of the present disclosure, a source-drain region may be formed in the semiconductor substrate 102 by any suitable technique known in the art. For example, the source-drain region may alternatively be formed directly in the semiconductor substrate 102 without creating a recess in the semiconductor substrate 102. The process may include ion implantation, photolithography, diffusion or any other suitable process that may allow inclusion of doping species in the semiconductor substrate 102. The doping species may vary according to p-FET or n-FET devices. One or more annealing processes may be conducted to activate the doped regions (not shown). After the activation process, raised source-drain regions may be formed above the doped source-drain regions using known techniques, such as, for example, epitaxial growth. The raised source-drain regions may be formed with a doped material as described above.
Referring now to
The CMP stop layer 302 may have a thickness of approximately 5-25 nm. A CMP stop layer of thickness less than 5 nm may not be able to effectively stop the polishing process causing punch through. Furthermore, a CMP stop layer 302 of thickness greater than 25 nm may affect etch selectivity depending on the selected carbon-based material forming the CMP stop layer 302. For example, a carbon nitride (SiCN) CMP stop layer including a thickness greater than 25 nm may include limited etch selectivity to gate spacers while a CMP stop layer made of conformal carbon (C) including a thickness greater than 25 nm may be easily removed but may cause problems during integration with the replacement metal gates (RMG). Additionally, a thickness greater than 25 nm may cause problems when etching the CMP stop layer through contact diffusion regions.
Referring now to
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For example, the metal gate 704 in a p-FET device may include a p-type metal including titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN) or other suitable materials.
For example, the metal gate 704 in an n-FET device may include an n-type metal including titanium aluminide (TiAl), titanium aluminum nitride (TiAlN) or other suitable materials.
Referring now to
The aforementioned steps may provide a method for controlling combined poly open and replacement metal chemical mechanical polish (CMP) during the replacement metal gate (RMG) process. Uncontrolled poly open and replacement metal CMP may result in shorter metal gate height. In severe over polish cases the height of the replacement metal gate may be the same as the raised source-drain region (RSD) epi overfill which may result in problems such as attack of RSD regions, severe silicon gouging, silicide placement near the channel region and increase leakage. The deposition of a CMP stop layer made of a chemical resistant carbon-based material directly on top of the dummy gates and RSD regions of the semiconductor substrate may prevent the CMP process to continue hence avoiding over polish of the metal gates and allowing uniform metal gate height in the semiconductor device.
Referring now to
Finally, contacts, for example substrate contacts 902 may be formed in the second ILD layer 906. The formation of contacts may further include the salicidation of the RSD regions 204. The contacts (902, 904) may be patterned by means of a photolithography process. Following the photolithography process, areas of the second ILD layer 906 may be etched to create contact holes and then a metal layer (not shown) may be deposited within the contact holes and over the entire semiconductor substrate by means of any deposition method known in the art including, for example, by CVD, PECVD, HDCVD, PVD, plating, sputtering, evaporation, and chemical solution deposition. In one embodiment of the present disclosure, the metal layer may include a nickel-platinum alloy (NiPt) where the atomic concentration of nickel (Ni) may range from about 70-95%. In another embodiment of the present disclosure, the metal layer may include nickel palladium (NiPd), nickel rhenium (NiRe), titanium (Ti), titanium tantalum (TiTa), titanium niobium (TiNb), or cobalt (Co). Alternatively, other metals commonly employed in salicide processing such as tantalum (Ta), tungsten (W), cobalt (Co), nickel (Ni), platinum (Pt), palladium (Pd), or alloys thereof may be employed.
After the metal layer is formed, the structure 900 may be subjected to a thermal annealing process, using conventional processes such as, but not limited to, rapid thermal annealing (RTA). During the thermal annealing process, the metal layer reacts with the silicon present in the RSD regions 204 to form a metal silicide. After the annealing process, an etching process may be carried out to remove substantially all un-reacted metal or metal alloy of the remaining portion of the metal layer. The etching process may include a wet etching method.
Next, gate contacts 904 may be patterned and formed. The process of patterning and formation of gate contacts may include a succession of techniques that may include photolithography and photomasking, wet or dry etching and metal deposition.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
