Patent Application
20180019250
The present invention relates to a nonvolatile memory cell and, more particularly, to a single-poly one-time programmable (OTP) memory cell that is capable of improving UV erase performance.
Demands of diversified markets and applications drive embedded logic non-volatile memory (logic NVM) for distinct functions. One of the well-known logic NVM is single-poly NVM or single-poly OTP memory technology, which is fully compatible with CMOS processes and is widely used in various chip designs for data storage.
Typically, a single-poly OTP memory cell includes two serially connected transistors. The first transistor acts as select transistor. A gate of the second transistor serves as a floating gate. The single-poly OTP memory cell is typically capped by dielectric materials, which are transparent to ultraviolet (UV) light.
The state in which hot carriers (electrons) are injected into the single-poly floating gate is called a “programmed” state and data is stored in this state, and in contrast, the state in which electrons are not injected into the single-poly floating gate is called an “erased” state and data is cleared in this state. The above-described single-poly OTP memory cell may be erased by UV light.
It is one object of the invention to provide a UV-erasable memory device with improved UV erase efficiency.
It is another object of the invention to provide a method for fabricating a UV-erasable memory device with a UV transmitting window.
According to one embodiment of the invention, a method for fabricating a UV-erasable memory device with a UV transmitting window is disclosed. A substrate is provided. Two serially connected PMOS transistors are formed on the substrate. The two PMOS transistors are then covered with an interlayer dielectric (ILD) layer. A first intermetal dielectric (IMD) layer is then deposited on the ILD layer. An intermediate layer is deposited on the first IMD layer. A UV transmitting window is formed in the intermediate layer. A second intermetal dielectric (IMD) layer is then deposited on the first IMD layer and into the UV transmitting window.
According to one embodiment of the invention, the two serially connected PMOS transistors comprise a select transistor and a floating gate transistor. The floating gate transistor comprises a polysilicon gate for charge storage. The UV transmitting window is positioned directly above the polysilicon gate for charge storage.
According to another aspect of the invention, a UV-erasable memory device with a UV transmitting window is disclosed. The UV-erasable memory device includes a substrate, two serially connected PMOS transistors on the substrate, an interlayer dielectric (ILD) layer covering the two PMOS transistors, a first intermetal dielectric (IMD) layer on the ILD layer, an intermediate layer on the first IMD layer, a UV transmitting window in the intermediate layer, and a second intermetal dielectric (IMD) layer on the first IMD layer and in the UV transmitting window.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute apart of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings:
It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings are exaggerated or reduced in size, for the sake of clarity and convenience. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.
In the following description, numerous specific details are given to provide a thorough understanding of the invention. It will, however, be apparent to one skilled in the art that the invention may be practiced without these specific details. Furthermore, some well-known system configurations or process steps are not disclosed in detail, as these should be well-known to those skilled in the art.
Likewise, the drawings showing embodiments of the apparatus are semi-diagrammatic and not to scale and some dimensions are exaggerated in the figures for clarity of presentation. Also, where multiple embodiments are disclosed and described as having some features in common, like or similar features will usually be described with like reference numerals for ease of illustration and description thereof.
The present invention pertains to a UV-erasable memory device such as an UV-erasable electrically programmable read only memory (EPROM) device or a single-poly one-time programmable (OTP) memory device with improved UV erase performance.
Please refer to
According to one embodiment of the invention, two serially connected MOS transistors 11 and 12 are formed on the substrate 10. The first MOS transistor 11 acts as a select transistor and may be a PMOS transistor. A polysilicon gate 111 of the first MOS transistor 11 may be coupled to a select gate voltage VSG. A select gate dielectric layer 112 may be provided between the polysilicon gate 111 and the substrate 10. A first node such as a doping region 103 of the first MOS transistor 11 may be coupled to a source line voltage VSL. The doping region 103 may be a P+ doping region.
A second node such as a doping region 105 of the first MOS transistor 11 is coupled to a first node of the second MOS transistor. That is, the first MOS transistor 11 is serially connected to the second MOS transistor 12 through the commonly shared doping region 105. The doping region 105 may be a P+ doping region.
On each sidewall of the polysilicon gate 111, a spacer 113 may be provided. Lightly doped drain (LDD) regions 103a and 105a may be formed in the N well 101 and are disposed directly under the spacers 113, respectively. The LDD regions 103a and 105a may be P-type LDD regions.
A second node such as a doping region 107 of the second MOS transistor 12 is coupled to a bit line voltage VBL. The doping region 107 may be a P+ doping region. The second MOS transistor 12 is a floating gate transistor and may be a PMOS transistor. A polysilicon gate 121 of the second MOS transistor 12 serves as a floating gate for charge storage. A floating gate dielectric layer 122 may be provided between the polysilicon gate 121 and the substrate 10.
Likewise, on each sidewall of the polysilicon gate 121, a spacer 123 may be provided. Lightly doped drain (LDD) regions 105b and 107a may be formed in the N well 101 and are disposed directly under the spacers 123, respectively. The LDD regions 105b and 107a may be P-type LDD regions.
Optionally, a self-aligned silicidation process may be performed to form a silicide layer 131 on the polysilicon gate 111, a silicide layer 133 on the doping region 103, a silicide layer 135 on the doping region, and a silicide layer 137 on the doping region 107. According to one embodiment of the invention, no silicide layer is formed on the polysilicon gate 121 because the polysilicon gate 121 is covered with a salicide block (SAB) layer 130 during the self-aligned silicidation process.
After the formation of the silicide layers 131, 133, 135, and 137, a contact etch stop layer (CESL) 210 is conformally deposited on the substrate 10 to cover the silicide layers 131, 133, 135, and 137, the first MOS transistor 11, and the second MOS transistor 12. According to one embodiment of the invention, the CESL 210 also covers the SAB layer 130 and is not in direct contact with the polysilicon gate 121.
After the deposition of the CESL 210, an interlayer dielectric (ILD) layer 220 is deposited on the CESL 210. For example, the ILD layer 220 may comprise BSG, BPSG, or low dielectric constant (low-k) dielectric materials. Although only one ILD layer 220 is illustrated, it is understood that the ILD layer 220 may comprise more than one layer of dielectric materials. Contact elements (not shown) may be formed in the ILD layer 220.
Subsequently, an etch stop layer 230 such as a silicon nitride layer may be deposited on the ILD layer 220. A first inter-metal dielectric (IMD) layer 240 may be deposited on the etch stop layer 230. The IMD layer 240 may comprise silicon oxide or low-k materials. An intermediate layer 250 is deposited on the first IMD layer 240. According to one embodiment of the invention, the intermediate layer 250 may be a silicon oxy-nitride layer having a thickness ranging between 1500 angstroms and 2500 angstroms, for example, 2000 angstroms.
The relatively thick intermediate layer 250 comprised of silicon oxy-nitride is necessary to the copper dual damascene process such as a via-first copper dual damascene process. However, the relatively thick intermediate layer 250 that is comprised of silicon oxy-nitride blocks UV light during the UV erase operation, which reduces the efficiency of the UV erasure.
As shown in
The photoresist pattern 260 comprises an opening 260a that is aligned with and positioned directly above the polysilicon gate 121. A dry etching process is performed to etch the intermediate layer 250 through the opening 260a, thereby forming a recessed trench 250a that penetrates through the intermediate layer 250 and may partially extend into the first IMD layer 240. Subsequently, the photoresist pattern 260 is removed.
By removing the portion of the intermediate layer 250 that is directly above the polysilicon gate 121, a UV transmitting window 300 is formed.
As shown in
During UV erase operation, the UV-erasable memory device 1 is exposed to a short-wavelength radiation 400 such UV light. By providing the UV transmitting window 300 between the IMD layers, the efficiency of the UV erasure is significantly improved.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
This application claims the benefit of U.S. provisional application No. 62/362,068 filed Jul. 14, 2016.
| Number | Date | Country | |
|---|---|---|---|
| 62362068 | Jul 2016 | US |
