Claims
- 1. A high density flash memory device comprising:an array comprising a plurality of sub-units, each of said plurality of sub-units comprising one or more single level flash memory cells, each of said plurality of sub-units being coupled with a sub-unit pre-decoder, said sub-unit pre-decoder being operative to enable an operation on said one or more single level flash memory cells of said corresponding sub-unit; a sector selector coupled with said sub-unit pre-decoders and operative to decode an input memory address and activate one or more of said sub-unit pre-decoders corresponding to said input memory address for said operation; and a sector size control register coupled with said sector selector and operative to control the number of sub-unit pre-decoders activated for said input memory address and said operation.
- 2. The high density flash memory device of claim 1, wherein the number of sub-unit pre-decoders activated for a given input address is a function of data stored in said sector size control register.
- 3. The high density flash memory device of claim 2, wherein said data is characterized by first and second values and further wherein:said sector decoder activates two of said sub-unit pre-decoders corresponding to said input memory address when said data is equal to said first value; and said sector decoder activates one of said sub-unit pre-decoders corresponding to said input memory address when said data is equal to said second value.
- 4. The high density flash memory device of claim 1, wherein each of said plurality of sub-units comprises 512 Kilobits of single level flash memory cells.
- 5. The high density flash memory device of claim 1, wherein said operation is an erase operation.
- 6. The high density flash memory device of claim 1, wherein said operation is a program operation.
- 7. A method of Varying the sector size of a high density flash memory device comprising an array of single level flash memory cells and a sector size control register, said method comprising:(a) subdividing said array of single level flash memory cells into a plurality of sub-units, each of said sub-units further comprising a sub-unit pre-decoder; (b) storing data in said sector size control register, said stored data representing the number of sub-units to be enabled for a memory address of said array; (c) decoding an input memory address; and (d) enabling one or more of said sub-unit pre-decoders based on said decoded input memory address and said stored data.
- 8. The method of claim 7, wherein each of said plurality of sub-units comprises 512 Kilobits of single level flash memory cells.
- 9. The method of claim 7, wherein said data is characterized by first and second values and further wherein (d) further comprises enabling two sub-unit pre-decoders when said data equals said first value and enabling one sub-unit pre-decoder when said data equals said second value.
- 10. The method of claim 7, further comprising:(e) performing a memory operation on said enabled one or more sub-units.
- 11. The method of claim 10, wherein said operation further comprises erasing said enabled one or more sub-units.
- 12. The method of claim 10, wherein said operation further comprises programming said enabled one or more sub-units.
- 13. A sector decoder for a flash memory array, said flash memory array being sub-divided into a plurality of sub-units, said sector decoder comprising:a sector size register operative to store data representing the number of said plurality of sub-units to be enabled for a memory operation; an address decoder operative to decode an input memory address; selection logic coupled with said address decoder, said sector size register and said flash memory array and operative to enable one or more of said plurality of sub-units corresponding to said decoded input memory address and said stored data for said operation.
- 14. The sector decoder of claim 13, wherein said data is characterized by first and second values and further wherein said selection logic is further operative to enable two of said one or more sub-units when said data is equal to said first value and enable one of said one or more sub-units when said data is equal to said second value.
- 15. The sector decoder of claim 13, wherein said operation is an erase operation.
- 16. The sector decoder of claim 13, wherein said operation is a program operation.
REFERENCE TO EARLIER FILED APPLICATION
This application claims the benefit of the filing date pursuant to 35 U.S.C. §119(e) of Provisional Application Serial No. 60/199,671, filed Apr. 25, 2000, the disclosure of which is hereby incorporated by reference.
US Referenced Citations (11)
Non-Patent Literature Citations (3)
Entry |
US 5,612,921, 3/1997, Chang et al. (withdrawn) |
AMD Datasheet for Am29LV640D/Am29LV641D, (first published May 4, 1999—see revision history on last page). |
AMD Press Release #9965—“AMD Announces Industry's First 3.0-Volt, 64-Megabit Nor Flash Memory Device”, p. 1 of 1, Apr. 26, 1999, ©1999 Advanced Micro Devices, Inc. |
Provisional Applications (1)
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Number |
Date |
Country |
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60/199671 |
Apr 2000 |
US |