Variable size cache memory support within an integrated circuit

Abstract

An integrated circuit 2 is provided with a cache memory 6 and a cache controller 10 coupled to the cache memory 6 via a cache memory interface 8. The cache controller supports different cache memory sizes. The cache memory 6 includes masking logic 14 responsive to cache memory size signals to form masked address values for use in accessing the cache memory 6. The cache controller 10 can be part of a processor core 4 which may be hardened in its design and yet able to cope with variable cache memory sizes since the masking logic 14 is provided within the cache memory 6 outside of the hardened periphery of the processor core 4.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically illustrates an integrated circuit incorporating a cache controller and a cache memory of variable cache memory size;

FIG. 2 illustrates cache size encodings which may be used with the example embodiment of FIG. 1; and

FIG. 3 illustrates logical statements defining the masking functionality provided by the masking logic of the example embodiment of FIG. 1.

Claims

1. An integrated circuit comprising: a cache memory; anda cache controller coupled to said cache memory via a cache memory interface having a cache controller side and a cache memory side, said cache controller and said cache memory interface supporting operation with cache memories of different cache memory sizes connected to said cache memory side of cache memory interface; whereinsaid cache memory includes masking logic responsive to one or more cache memory size signals received via said cache memory interface to apply variable masking to an address value generated by said cache controller to form at least one masked address value for use in accessing said cache memory, said masking applied by said masking logic being varied in dependence upon said one or more cache memory size signals to match a cache memory size of said cache memory.

2. An integrated circuit as claimed in claim 1, wherein said cache memory includes a tag memory and said at least one masked address value include a tag address to address said tag memory.

3. An integrated circuit as claimed in claim 2, wherein a first portion of said address value with a bit-size selected by said masking logic in dependence upon said at least one cache size signal forms said tag address.

4. An integrated circuit as claimed in claim 1, wherein said cache memory includes a data memory and said at least one masked address value includes a data address to address said data memory.

5. An integrated circuit as claimed in claim 4, wherein a second portion of said address value with a bit-size selected by said masking logic in dependence upon said at least one cache size signal forms said data address.

6. An integrated circuit as claimed in claim 1, wherein said cache memory passes via said cache memory interface limit signals representing a minimum cache memory size and a maximum cache memory size with which said cache memory can be configured to operate.

7. An integrated circuit as claimed in claim 1, comprising a software programmable register storing a cache memory size value.

8. An integrated circuit as claimed in claim 7, wherein said cache controller reads said cache memory size value from said software programmable register as a parameter controlling cache management operations performed by said cache controller upon said cache memory.

9. An integrated circuit as claimed in claim 7, wherein said at least one cache memory size signal is generated from said cache memory size value stored in said software programmable register.

10. An integrated circuit as claimed in claim 6, comprising clipping logic responsive to said limit signals to clip a cache memory size value being written to said software programmable register so as to be subject to said minimum cache memory size and said maximum cache memory size.

11. An integrated circuit as claimed in claim 7, wherein said software programmable register is a register within a configuration coprocessor.

12. An integrated circuit as claimed in claim 1, wherein said cache memory includes an instruction cache memory and a data cache memory with respective cache memory size signals.

13. An integrated circuit as claimed in claim 1, wherein said cache controller is part of a processor core that is validated separately from said cache memory.

14. An integrated circuit as claimed in claim 13, wherein validation of said processor core is independent of said cache memory size.

15. An integrated circuit comprising: cache memory means; andcache controller means coupled to said cache memory means via a cache memory interface having a cache controller side and a cache memory side, said cache controller means and said cache memory interface supporting operation with cache memory means of different cache memory sizes connected to said cache memory side of cache memory interface; whereinsaid cache memory means includes masking logic means responsive to one or more cache memory size signals received via said cache memory interface to apply variable masking to an address value generated by said cache controller means to form at least one masked address value for use in accessing said cache memory means, said masking applied by said masking logic means being varied in dependence upon said one or more cache memory size signals to match a cache memory size of said cache memory means.

16. A method of operating an integrated circuit, said method comprising the steps of: storing data within a cache memory;controlling said cache memory with a cache controller coupled to said cache memory via a cache memory interface having a cache controller side and a cache memory side, said cache controller and said cache memory interface supporting operation with cache memories of different cache memory sizes connected to said cache memory side of cache memory interface; andusing masking logic within said cache memory responsive to one or more cache memory size signals received via said cache memory interface to apply variable masking to an address value generated by said cache controller to form at least one masked address value for use in accessing said cache memory, said masking applied by said masking logic being varied in dependence upon said one or more cache memory size signals to match a cache memory size of said cache memory.