Patent Application
20080303095
The present invention relates generally to semiconductor devices and more particularly to multi-gate transistors (MuGFETs).
As the performance and process limitations on scaling planar transistors are reached, attention has been recently directed to transistor designs having multiple gates (e.g., three-dimensional MOS transistors), which may also be referred to as Multi-Gate Field Effect Transistors (MuGFETs). In theory, these designs provide more control over a scaled channel by situating the gate around two or more sides of a silicon fin in which a conductive channel is formed.
By alleviating the short channel effects seen in traditional scaled planar transistors, multi-gate designs offer the prospect of improved transistor performance. This is due primarily to the ability to invert a larger portion of the channel silicon because the gate extends on more than one side of the channel. In practice, however, the conventional multi-gate approaches have suffered from cost and performance shortcomings.
Accordingly, to realize the advantages of scaling while overcoming the shortcomings of traditional multi-gate transistors, there remains a need for improved multi-gate transistors and manufacturing techniques.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary presents one or more concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later and is not an extensive overview of the invention. In this regard, the summary is not intended to identify key or critical elements of the invention, nor does the summary delineate the scope of the invention.
One embodiment of the present invention relates to an integrated circuit that includes a first multi-gate transistor that has a first fin width and a first threshold voltage. The integrated circuit also includes a second multi-gate transistor that has a second fin width that is greater than the first width and a second threshold voltage that is less than the first threshold voltage.
The following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed.
The present invention will now be described with reference to the attached drawing figures, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures and devices are not necessarily drawn to scale.
One concept of the invention allows a designer to tailor a MuGFET's voltage threshold (VT) where strong inversion occurs as a function of the MuGFET's fin width (W). Thus, an integrated circuit may be provided that has MuGFETs of varying fin widths, where MuGFETs with narrower fins have higher VT's and MuGFETs with wider fins have lower VT's. For example,
While
Referring now to
The MuGFET 200 comprises a gate electrode 208 that straddles an undoped silicon fin 210, where a channel region 212, is associated with the fin 210. A dielectric layer 214 is sandwiched between the fin 210 and the gate electrode 208, and electrically separates the fin 210 from the gate electrode 208. A source 216 and drain 218, which are typically characterized by a relatively high dopant concentration (relative to the doping in the channel region 212), are formed within the fin 210 laterally separated from one another by a gate length L1 as measured across the channel region 212 under the gate electrode 208. In one short-channel embodiment, the fin width W1 could be approximately half of the gate length L1. Generally, current in the form of charged carriers (i.e., negatively charged electrons or positively charged holes) flows along the length L1 of the device though the channel region 212.
As shown, the gate electrode 208 may comprise two layers, namely, a first gate electrode layer 220, which is typically a metal, and a second gate electrode layer 222, which is typically polysilicon. Other layers (e.g., dielectrics, vias, metal1, metal2, etc.), which are not shown for the purposes of simplicity, may also be formed over the gate electrode 208 and other surfaces.
In one embodiment, the first gate electrode layer 220 of the relatively narrow MuGFET 200 and the first gate electrode layer 320 of the relatively wide MuGFET 300 comprise the same metal. This metal could be a mid-gap metal. Mid-gap means that the work function is about mid-way between the valence band and the conduction band of the substrate. One advantage of using a single mid-gap metal over all MuGFET devices on the integrated circuit is that it requires fewer mask steps than depositing one metal over p-type devices and another metal over n-type devices, which is another option in the manufacture of MuGFETs. However, prior solutions have suffered from a drawback in that the use of a single mid-gap metal over both p-type and n-type MuGFETs has hereforeto provided a relatively high VT for the devices. Thus, by widening a MuGFET, one can reduce the VT of the MuGFET to compensate for a high VT, which allows multiple VT's across the integrated circuit while still retaining the benefits of using a single mid-gap metal.
Although the MuGFETs 200, 300 often have some similar features, they may also have features that are different. For example, as mentioned the MuGFETs 200, 300 differ in their respective fin widths W1, W2, where W2>W1. In addition, they can also differ in their respective gate lengths L1, L2. For example, the wide MuGFET 300 (
During operation of the MuGFETs 200,300, a gate-source voltage (VGS) may be applied to the gate electrode (e.g., 208) relative to the source (e.g., 216). This VGS can alter the number of charged carriers in the channel region (e.g., 212) to facilitate desired functionality. In various embodiments, the previously described MuGFETs can be implemented as accumulation mode devices or enhancement/depletion mode devices.
Enhancement/depletion mode devices typically have one type of dopant in the source/drain regions (e.g., 216/218) and an opposite type of dopant in the channel region (e.g., 212). For example,
By comparison, accumulation mode devices typically have one type of dopant in the source/drain regions (e.g., 216/218) and the same or similar type of dopant in the channel region (e.g., 212). For example,
In digital applications where a MuGFET represents either a one-state or a zero-state, good noise margins and fast state transitions are typically desired. A high VT (narrow MuGFET) may help facilitate good noise margins by increasing the voltage margin between the one-state and the zero-state. Further, because the digital devices often switch quickly and do not typically drive a large current, a short channel MuGFET may also be appropriate for digital applications. Thus, FIG. 3A's MuGFET 200 could be used in a digital manner, because it has a relatively narrow width W1 (high VT), which could facilitate good noise margins, and because it is has a relatively short gate length L1, which would allow it to switch quickly due to low capacitance. In other various short channel embodiments to control the short channel effects, the fin width W1 should be less than one half of the gate length L1.
Conversely, in analog applications where a MuGFET represents a continuum of a near infinite number of states, precise matching between MuGFETs and significant drive current may be required. To this end, a low VT (wide MuGFET) may facilitate good matching. In addition, because analog device may need significant drive current, a long channel MuGFET with a low VT may better source the current needed for these drive currents—due in part because more overdrive voltage (VDD-VT) can be achieved. Thus, FIG. 4A's MuGFET 300 could be used in an analog manner, because it has a relatively wide width W2 (low VT), which could facilitate good matching, and because it has a relatively long gate length L2, which would provide it with larger drive current. In other various long channel embodiments, to control the short channel effects, the fin width W2 should be less than one half of the gate length L2; as long as the fin width W2 is less than 1.5 times the fin height h. When the fin width W2 is greater than 1.5 times the fin height, the device may deviate from MuGFET operational mode and becomes more like a fully depleted planar MOSFET.
In theory, in one embodiment where the first gate electrode layer is a mid-gap metal, the low end of VT is approximately equal to φf. This is expressed by the following VT equation:
where Φms is the difference in the work function between the first gate electrode layer and the semiconductor substrate; φf is the energy difference between the doped semiconductor in the channel region and the undoped intrinsic semiconductor Fermi level; Cox is the gate capacitance; Qox is the charge in the gate dielectric layer; Qch is the depletion charge in the channel region controlled by the gate electrode; and Vinv is an additional gate voltage required beyond strong inversion 2φf as a result of thin fins (Vinv tends to decrease as fins become wider, and in one embodiment Vinv is approximately zero for fins having a width more than 50 nm). For a p-type substrate, φf>0, while for an n-type substrate φf<0, and the magnitude of φf equals kT/q*In(Na/ni), where Na is the doping concentration in the channel and ni is the intrinsic carrier concentration for the semiconductor material. If the work function of the first gate electrode layer is close to mid-gap, then Φms˜0V. Accordingly, in one embodiment for example, the silicon could have a doping concentration of 1E15/cm3, φf˜0.3V and Qch/Cox˜0V. Since Qox/Cox˜0V, the long channel VT=Φms+2φf, and for a mid-gap metal gate we expect that VT=φf.
Although one type of MuGFET was illustrated and described above where multiple gate surfaces may be controlled by a single gate electrode, other types of MuGFETs could also be used. For example, in another type of MuGFET (called a multiple independent gate field effect transistor or MIGFET), multiple gates are controlled by multiple independent gate electrodes. The invention is applicable to gate-all-around (GAA) transistors and other various types of multi-gate transistors.
Although the invention has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising”.
