Verification method for nonvolatile semiconductor memory device

Abstract

The present invention provides nonvolatile semiconductor memory devices which operate with low power consumption. In a nonvolatile semiconductor memory device, a plurality of nonvolatile memory elements are connected in series. The plurality of nonvolatile memory elements include a semiconductor layer including a channel forming region and a control gate provided to overlap with the channel forming region. Operations of write, erase, a first read, and a second read in a verify operation of data to the nonvolatile memory elements, are conducted by changing voltage to the control gates of the nonvolatile memory elements. The second read in the verify operation after erase operation is conducted by changing only one of a potential of the control gate of a nonvolatile memory element which are selected from the plurality of nonvolatile memory elements, and as the potential, a potential different from a potential of the first read is used.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 shows a potential change of each control line in a verify operation for erase;

FIG. 2 is a block diagram showing a verify operation of a conventional nonvolatile memory;

FIG. 3 is a block diagram showing a verify operation of a conventional nonvolatile memory;

FIG. 4 shows electric characteristics of a single memory element;

FIG. 5 shows a relation between potentials of control lines when data is read from a nonvolatile memory element M30;

FIG. 6 shows a relation between potentials of control lines when data is written;

FIG. 7 shows a relation between potentials of control lines when data is erased;

FIG. 8 shows a relation between control lines when data is read in a verify operation for erase;

FIG. 9 shows an example of a block diagram of a nonvolatile semiconductor memory device according to an aspect of the present invention;

FIG. 10 shows an example of a read circuit;

FIG. 11 shows an example of an equivalent circuit of a NAND type memory cell array;

FIG. 12 is a cross sectional view of a nonvolatile memory element shown in Embodiment Mode 2;

FIG. 13 shows a structure of a plasma treatment apparatus;

FIG. 14 is a cross sectional view of a nonvolatile memory element shown in Embodiment Mode 2;

FIG. 15 is a band diagram of a nonvolatile memory element;

FIG. 16 is a band diagram of a nonvolatile memory element;

FIG. 17 is a band diagram of a conventional nonvolatile memory element;

FIGS. 18A and 18B show write and read operations of a nonvolatile memory element;

FIG. 19 is a band diagram of a nonvolatile memory element when data is written;

FIG. 20 is a band diagram of a nonvolatile memory element when charges are stored;

FIGS. 21A and 21B show an erase operation of a nonvolatile memory element;

FIG. 22 is a band diagram of a nonvolatile memory element when data is erased;

FIG. 23 shows an example of a top view of a nonvolatile semiconductor memory device according to an aspect of the present invention;

FIG. 24 shows an example of a top view of a nonvolatile semiconductor memory device according to an aspect of the present invention;

FIG. 25 shows an example of a top view of a nonvolatile semiconductor memory device according to an aspect of the present invention;

FIGS. 26A to 26C show an example of a manufacturing method of a nonvolatile semiconductor memory device according to an aspect of the present invention;

FIGS. 27A and 27B show an example of a manufacturing method of a nonvolatile semiconductor memory device according to an aspect of the present invention;

FIGS. 28A to 28C show an example of a manufacturing method of a nonvolatile semiconductor memory device according to an aspect of the present invention;

FIGS. 29A to 29C show an example of a manufacturing method of a nonvolatile semiconductor memory device according to an aspect of the present invention;

FIGS. 30A to 30C show an example of application use of a nonvolatile semiconductor memory device according to an aspect of the present invention; and

FIGS. 31A to 31E each shows an example of application use of a nonvolatile semiconductor memory device according to an aspect of the present invention.

Claims

1. A verify method of a semiconductor device having a first and second nonvolatile memory elements connected in series, comprising: setting potential of a control gate of the first nonvolatile memory element to be a first potential and potential of a control gate of the second nonvolatile memory element to be a second potential, for erasing a data stored in the first nonvolatile memory element; andsetting potential of a control gate of the first nonvolatile memory element to be a third potential and potential of a control gate of the second nonvolatile memory element to be the second potential, for reading a data stored in the first nonvolatile memory element after erasing a data stored in the first nonvolatile memory element.

2. The verify method according to claim 1, wherein each of the first and second nonvolatile memory elements has a semiconductor layer including a channel forming region and a floating gate, andwherein the floating gate is formed from a semiconductor material having a smaller energy gap than the semiconductor layer.

3. The verify method according to claim 1, wherein each of the first and second nonvolatile memory elements has a semiconductor layer including a channel forming region and a floating gate, andwherein the floating gate is formed from germanium or a germanium compound.

4. The verify method according to claim 1, wherein the semiconductor device is incorporated in at least one of electronic device selected from the group consisting of a camera, a goggle display, a navigation system, an audio reproducing apparatus, a computer, a game machine, a portable information terminal, and an image reproducing device.

5. The verify method according to claim 1, wherein the semiconductor device is incorporated in at least one of paper money, a coin, securities, a certificate, a bearer bond, a packaging container, a book, a recording media, a vehicle, a food, a clothing, a health product, a commodity, and chemicals.

6. The verify method according to claim 1, wherein the first and second nonvolatile memory elements share a same semiconductor layer.

7. The verify method according to claim 1, wherein the first and second nonvolatile memory elements are formed over a substrate having an insulating surface.

8. The verify method according to claim 1, wherein the first and second nonvolatile memory elements are formed over a substrate containing silicon.

9. A verify method of a semiconductor device having a plurality of nonvolatile memory elements connected in series, comprising: selecting one of the plurality of nonvolatile memory elements;setting potential of control gates of the plurality of nonvolatile memory elements so that potential of the selected nonvolatile memory element to be a first potential and the other nonvolatile memory elements to be a second potential, while erasing a data stored in the selected nonvolatile memory element; andsetting potential of control gates of the plurality of nonvolatile memory elements so that potential of the selected nonvolatile memory element to be a third potential and the other nonvolatile memory elements to be the second potential, while reading a data stored in the selected nonvolatile memory element after erasing a data stored in the selected nonvolatile memory element.

10. The verify method according to claim 9, wherein each of the plurality of nonvolatile memory elements has a semiconductor layer including a channel forming region and a floating gate, andwherein the floating gate is formed from a semiconductor material having a smaller energy gap than the semiconductor layer.

11. The verify method according to claim 9, wherein each of the plurality of nonvolatile memory elements has a semiconductor layer including a channel forming region and a floating gate, andwherein the floating gate is formed from germanium or a germanium compound.

12. The verify method according to claim 9, wherein the semiconductor device is incorporated in at least one of electronic device selected from the group consisting of a camera, a goggle display, a navigation system, an audio reproducing apparatus, a computer, a game machine, a portable information terminal, and an image reproducing device.

13. The verify method according to claim 9, wherein the semiconductor device is incorporated in at least one of paper money, a coin, securities, a certificate, a bearer bond, a packaging container, a book, a recording media, a vehicle, a food, a clothing, a health product, a commodity, and chemicals.

14. The verify method according to claim 9, wherein the plurality of nonvolatile memory elements share a same semiconductor layer.

15. The verify method according to claim 9, wherein the plurality of nonvolatile memory elements are formed over a substrate having an insulating surface.

16. The verify method according to claim 9, wherein the plurality of nonvolatile memory elements are formed over a substrate containing silicon.