Patent Application
20200395467
The present invention relates to field effect transistors, and more specifically, to vertical field effect transistors.
A field-effect transistor (FET) is an electronic device which uses an electric field to control the flow of current. FETs are 3-terminalled devices, having a source, gate, and drain terminal. FETs control the flow of current by the application of a voltage to the gate terminal, which in turn alters the conductivity between the drain and source terminals.
An embodiment of the invention may include a method of forming a semiconductor structure. The method may include removing a gate region from a layered stack located on a source/drain layer. The layered stack includes a first spacer located on the source drain layer, a dummy layer located on the first spacer, and a second spacer located on the dummy layer. The method may include forming a channel material above the source/drain layer in the gate region. The method may include forming a top source/drain on the channel material. The method may include forming a hardmask surrounding the top source/drain. The method may include removing a portion of the layered stack that is not beneath the hardmask.
An embodiment of the invention may include a method of forming a semiconductor structure. The method may include removing a gate region from a layered stack located on a source/drain layer. The layered stack includes a first spacer located on the source drain layer, a dummy layer located on the first spacer, and a second spacer located on the dummy layer. The method may include forming a channel material above the source/drain layer in the gate region. The method may include forming a top source/drain on the channel material. The method may include forming a hardmask surrounding the top source/drain. The method may include performing an anneal causing the source/drain layer forming a bottom source/drain extension and causing the top source/drain into the channel material forming a top source/drain extension.
An embodiment of the invention may include a semiconductor structure. The semiconductor structure may include a bottom source/drain located on a substrate. The semiconductor structure may include a channel material located on the bottom source drain. The semiconductor structure may include a top source/drain located on a top surface of the channel material. The channel material includes a channel region, a top source/drain extension, and a bottom source/drain extension, and wherein the top source/drain extension and the bottom source/drain extension are substantially similar.
Elements of the figures are not necessarily to scale and are not intended to portray specific parameters of the invention. For clarity and ease of illustration, dimensions of elements may be exaggerated. The detailed description should be consulted for accurate dimensions. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements.
Exemplary embodiments now will be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will convey the scope of this disclosure to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.
For purposes of the description hereinafter, terms such as “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. Terms such as “above”, “overlying”, “atop”, “on top”, “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
In the interest of not obscuring the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations that are known in the art may have been combined together for presentation and for illustration purposes and in some instances may have not been described in detail. In other instances, some processing steps or operations that are known in the art may not be described at all. It should be understood that the following description is rather focused on the distinctive features or elements of various embodiments of the present invention.
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Source/drain 110 may be located on substrate 100, acting as one of the source/drains for the vertical transistor. Source/drain 110 may be formed by doping a top layer of substrate 100, or alternatively from epitaxially growing the source/drain material above the substrate 100. In an example embodiment the source/drain 110 may be silicon-germanium. In such an embodiment, the semiconductor material may contain, for example, approximately 20% to approximately 100% germanium, approximately 0% to approximately 80% silicon, and may be doped with p-type dopants such as boron in concentrations ranging from approximately 1×1020 atoms/cm3 to approximately 2×1021 atoms/cm3. In another example embodiment, the semiconductor material may be carbon doped silicon. In such an embodiment, the semiconductor material may contain, for example, approximately 0.5% to approximately 2.5% carbon, approximately 97.5% to approximately 99.5% silicon, and may be doped with n-type dopants such as arsenic or phosphorus in concentrations ranging from approximately 1×1020 atoms/cm3 to approximately 2×1021 atoms/cm3. Source/drain 110 may have a thickness ranging from approximately 20 nm to approximately 100 nm, preferably approximately 30 nm to approximately 60 nm.
A first spacer layer 120 may be located on the source/drain layer 110. The first spacer layer 120 may be made of any insulating material, such as silicon nitride, silicon oxide, silicon oxynitrides, or a combination thereof, and may have a thickness ranging from 4 nm to approximately 15 nm, preferably approximately 5 nm to approximately 10 nm. The first spacer layer 120 may be formed by any method known in the art.
A dummy layer 130 may be located on the first spacer layer 120. The dummy layer 130 may include a sacrificial gate structure, that may be later removed and replaced by a replacement gate dielectric, an optional work function metal and a replacement gate electrode. In an example embodiment, the dummy gate material may be made of a SiO or SiCO. Dummy layer 130 may have a thickness ranging from approximately 10 nm to approximately 30 nm, preferably approximately 15 nm to approximately 25 nm.
A second spacer layer 140 may be located on the source/drain layer 130. The second spacer layer 140 may be made of any insulating material, such as silicon nitride, silicon oxide, silicon oxynitrides, or a combination thereof, and may have a thickness ranging from 4 nm to approximately 15 nm, preferably approximately 5 nm to approximately 10 nm. The second spacer layer 140 may be formed by any method known in the art.
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The terms “epitaxial growth and/or deposition” and “epitaxially formed and/or grown” mean the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown may have the same crystalline characteristics as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxial semiconductor material may have the same crystalline characteristics as the deposition surface on which it may be formed. For example, an epitaxial semiconductor material deposited on a {100} crystal surface may take on a {100} orientation. In some embodiments, epitaxial growth and/or deposition processes may be selective to forming on semiconductor surfaces, and may not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces.
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Following the removal of the dummy gate 137, the gate dielectric layer 220 may be conformally deposited by ALD and/or CVD. The gate dielectric layer 220 may be a high-k material, including but not limited to metal oxides such as hafnium oxide (e.g., HfO2), hafnium silicon oxide (e.g., HfSiO4), hafnium silicon oxynitride (HfwSixOyNz), lanthanum oxide (e.g., La2O3), lanthanum aluminum oxide (e.g., LaAlO3), zirconium oxide (e.g., ZrO2), zirconium silicon oxide (e.g., ZrSiO4), zirconium silicon oxynitride (ZrwSixOyNz), tantalum oxide (e.g., TaO2, Ta2O5), titanium oxide (e.g., TiO2), barium strontium titanium oxide (e.g., BaTiO3-SrTiO3), barium titanium oxide (e.g., BaTiO3), strontium titanium oxide (e.g., SrTiO3), yttrium oxide (e.g., Y2O3), aluminum oxide (e.g., Al2O3), lead scandium tantalum oxide (Pb(ScxTa1-x)O3), and lead zinc niobate (e.g., PbZn⅓ Nb⅔ O3). The high-k dielectric material may further include dopants such as lanthanum and/or aluminum. The stoichiometry of the high-k dielectric material may vary. In various embodiments, the gate dielectric layer 220 may have a thickness in the range of about 1.5 nm to about 2.5 nm.
In one or more embodiments, an optional work function layer may be deposited over the gate dielectric layer 220, where the optional work function layer may be conformally deposited by ALD and/or CVD. The optional work function layer may be a nitride, including but not limited to titanium nitride (TiN), hafnium nitride (HfN), hafnium silicon nitride (HfSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN); a carbide, including but not limited to titanium carbide (TiC), tantalum carbide (TaC), hafnium carbide (HfC), and combinations thereof. The optional work function layer may have a thickness in the range of about 1 nm to about 11 nm, or may have a thickness in the range of about 2 nm to about 5 nm.
In one or more embodiments, the optional work function layer may include a thin a gate metal layer (not shown) which may be formed on the optional work function layer, where the gate metal layer may include a thin layer conformally deposited on the optional work function layer. A gate conductor 230 is deposited and patterned to form a gate electrode. The gate metal layer may be conformally deposited by ALD or CVD, where the gate metal layer may have a thickness in the range of about 5 Å to about 15 Å. The gate metal layer may be tungsten (W), aluminum (Al), titanium nitride (TiN), cobalt (Co), or a combination thereof. The total thickness of the gate metal layer and the optional work function layer may be in the range of about 6 nm to about 12 nm. Unneeded metal(s) (for portions of gate metal layer, optional work function layer, and gate conductor 230) may be etched away. Portions of the high-k layer 250 may also be removed in defining the gate structure for each channel region 155. In various embodiments, the high-k layer 250, the gate conductor 230, and optional work function layer may form a gate structure at least on opposite sides of the channel region 155. In various embodiments, the gate structure may wrap around three sides or four sides of the vertical fin.
In one or more embodiments, the gate conductor 230 may be deposited on high-k layer 250. In one or more embodiments, the gate conductor 230 may include tungsten (W). In various embodiments, the gate conductor 230 may extend laterally beyond the second spacer 147 to allow formation of a metal contact to the gate structure. The gate conductor 230 may be electrically isolated from the channel region 155 by first spacer 127.
Following the Replacement Metal Gate process, a reliability anneal may be performed. The reliability anneal, may be performed at a temperature from 700° C. to 1300° C., depending on the annealing time. Further, the reliability anneal may diffuse dopants from the intermediate bottom source/drain 115 into a bottom portion of the channel region 155 and to provide the bottom source/drain 117, and dopants from the VFET top source/drain 160 into the upper portion of the channel region 155 and to create a top source/drain 165. Typically higher temperatures require less annealing times. Annealing can be done by rapid thermal anneal (RTA), laser anneal, flash anneal, furnace anneal, or any suitable combination of those techniques. In one embodiment, the anneal is done at 1000° C. for 0.5 seconds. Other temperatures may also be used as long as the anneal temperature is capable of forming the bottom source/drain 117 and the top source/drain 165 shown in
Following the drive in anneal, bottom source/drain 117 and top source drain 165 may include bottom extension region 117E and top extension region 165E, that are the result of dopant diffusion from the intermediate bottom source/drain 115 and VFET top source/drain 160 to the channel region 155. In embodiments where the intermediate bottom source/drain 115 and the VFET top source/drain are made of similar materials, the bottom extension region 117E and top extension region 165E may similar thicknesses, chemical composition, and chemical gradients due to the simultaneous drive in anneal that was performed. This may additionally form a symmetric channel region 155, whereas the amount of the channel region 155 that extends beyond the dummy gate 137, is substantially similar on the top and bottom end of the channel region 155. Such uniformity of geometry may lead to better, and more uniform, performance of the resulting VFET structure.
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The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable other of ordinary skill in the art to understand the embodiments disclosed herein. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated but fall within the scope of the appended claims.
