Patent Application
20120080725
Solid state memories (SSMs) provide an efficient mechanism for storing and transferring data in a wide variety of applications, such as hand-held portable electronic devices. Individual memory cells within such memories can be volatile or non-volatile, and can store data by the application of suitable write currents to the cells to store a sequence of bits. The stored bits can be subsequently read during a read access operation by applying suitable read currents and sensing voltage drops across the cells.
Some SSM cell configurations employ a memory element coupled to a channel based switching device such as a metal oxide semiconductor field effect transistor (MOSFET). The switching device provides selective access to the memory element during read and write operations. Examples of memory cells with this type of memory element-switching device arrangement include, but are not limited to, volatile dynamic random access memory (DRAM), non-volatile resistive random access memory (RRAM), and non-volatile spin-torque transfer random access memory (STRAM).
While operable, a limitation with the use of MOSFETs and other types of switching devices in a memory cell is the areal extent (size) of such devices. A horizontal MOSFET layout is often used in which the associated drain and source regions are placed adjacent one another in a base substrate, with the channel region extending horizontally therebetween. The memory element is formed above either the source or the drain.
Horizontal MOSFETs may require a minimum size of about 4 F2 where F is the minimum feature dimension of the associated manufacturing process (e.g., F=70 nm, etc.). Since this is significantly larger than the areal size of many types of memory elements, the switching device size can be a limiting factor in achieving greater areal densities in a memory array.
The amount of current needed to operate STRAM memory elements can be quite large, of the order of 500-1000 uA. Because the horizontal MOSFET (i.e., select device) conducts current primarily in the surface region of the device, its conductivity is limited, often requiring a large MOSFET to be used in order to delivered sufficient current to program the STRAM cell. Larger MOSFET devices lead to larger STRAM cell areas, and increase die size and product cost. Also, horizontal select devices have certain alignment tolerances built into their design, to avoid device failures, this adds parasitic resistance and capacitance which slows down the operation of the STRAM, as well as increasing its total area (and cost).
Some recent semiconductor memory designs have proposed a stacked memory cell arrangement whereby the memory element and the transistor are vertically aligned as a pillar, or stack, above a base substrate. In a stacked memory cell, the drain and source regions are located one above the other, with the channel region extending vertically therebetween. While advantageously promoting an enhanced areal data density, it can be difficult to form the pillar structure of the vertical transistor so that the transistor can operate optimally.
The present disclosure relates to a memory array that includes a plurality of non-volatile variable resistive memory cells where each memory cell is electrically connected to a vertical pillar transistor with an electrically conducting interconnect element. The electrically conducting interconnect element can reduce interface resistance and/or stress forces between the memory cell and the vertical pillar transistor. Methods of forming the same are also disclosed.
In one particular embodiment, a method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. An electrically conducting interconnect element is deposited onto at least selected vertical pillar transistors and a non-volatile variable resistive memory cell is deposited onto the electrically conducting interconnect layer to form a vertical transistor memory array.
These and various other features and advantages will be apparent from a reading of the following detailed description.
The disclosure may be more completely understood in consideration of the following detailed description of various embodiments of the disclosure in connection with the accompanying drawings, in which:
The figures are not necessarily to scale. Like numbers used in the figures refer to like components. However, it will be understood that the use of a number to refer to a component in a given figure is not intended to limit the component in another figure labeled with the same number.
In the following description, reference is made to the accompanying set of drawings that form a part hereof and in which are shown by way of illustration several specific embodiments. It is to be understood that other embodiments are contemplated and may be made without departing from the scope or spirit of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense. The definitions provided herein are to facilitate understanding of certain terms used frequently herein and are not meant to limit the scope of the present disclosure.
Unless otherwise indicated, all numbers expressing feature sizes, amounts, and physical properties used in the specification and claims are to be understood as being modified in all instances by the term “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the foregoing specification and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by those skilled in the art utilizing the teachings disclosed herein.
The recitation of numerical ranges by endpoints includes all numbers subsumed within that range (e.g. 1 to 5 includes 1, 1.5, 2, 2.75, 3, 3.80, 4, and 5) and any range within that range.
As used in this specification and the appended claims, the singular forms “a”, “an”, and “the” encompass embodiments having plural referents, unless the content clearly dictates otherwise. As used in this specification and the appended claims, the term “or” is generally employed in its sense including “and/or” unless the content clearly dictates otherwise.
Spatially related terms, including but not limited to, “lower”, “upper”, “beneath”, “below”, “above”, and “on top”, if used herein, are utilized for ease of description to describe spatial relationships of an element(s) to another. Such spatially related terms encompass different orientations of the device in use or operation in addition to the particular orientations depicted in the figures and described herein. For example, if a cell depicted in the figures is turned over or flipped over, portions previously described as below or beneath other elements would then be above those other elements.
As used herein, when an element, component or layer for example is described as forming a “coincident interface” with, or being “on” “connected to”, “coupled with” or “in contact with” another element, component or layer, it can be directly on, directly connected to, directly coupled with, in direct contact with, or intervening elements, components or layers may be on, connected, coupled or in contact with the particular element, component or layer, for example. When an element, component or layer for example is referred to as begin “directly on”, “directly connected to”, “directly coupled with”, or “directly in contact with” another element, there are no intervening elements, components or layers for example.
The present disclosure relates to a memory array that includes a plurality of non-volatile variable resistive memory cells and in particular, spin-torque transfer memory cells (i.e., STRAM) where each memory cell is electrically connected to a vertical pillar transistor with an electrically conducting interconnect element. The electrically conducting interconnect element reduces the interface resistance and/or reduces stress forces between the memory cell and the vertical pillar transistor. Since the vertical transistor is cylindrical, its total conductive surface is roughly 2πF, where F is the minimum feature size. By comparison, a horizontal transistor only scales as F. This means that vertical devices conduct roughly 6× the amount of current for a given area, enabling the memory cell to be scaled down to nearly 4 F2 (which is the theoretical minimum cell size). In addition a silicided interface provides the minimum parasitic contact resistance, and allows the device to be fully scalable with device size. In other words, the parasitic contact resistances are linear with devices size. Methods of forming the same are also disclosed. While the present disclosure is not so limited, an appreciation of various aspects of the disclosure will be gained through a discussion of the examples provided below.
The present disclosure is generally directed to an apparatus characterized as a multi-wafer structure with embedded (bottom side) control lines, and an associated method for making the same. The embedded control lines provide electrical interconnection with vertically stacked semiconductor elements within the multi-wafer structure. The stacked semiconductor elements form vertical pillar transistors that can be formed via a hardening implantation step as described below.
In various embodiments, an acceptor wafer is formed that incorporates various control circuitry, and a donor wafer is formed that incorporates a matrix from which individual channel based switching devices (e.g., vertical pillar transistors) are subsequently formed.
The acceptor wafer and the donor wafer are each provided with a metal layer on a respective facing surface. The acceptor and donor wafers are attached to form the multi-wafer structure, and during this attachment process the respective metal layers are brought together to form a single combined metal layer that is embedded within the multi-wafer structure. The combined metal layer is transformed during subsequent processing into individual embedded bottom side control lines (e.g., embedded source lines).
A programmable controller 102 provides top level control of the device 100 during operation. An interface circuit (I/F) 104 communicates with the host and transfers data to be stored in a semiconductor memory 106.
The semiconductor memory 106 is characterized as a non-volatile storage space formed from one or more arrays 108 of non-volatile memory cells (e.g., RRAM or STRAM. In other embodiments, the memory 106 can take the form of a volatile memory space such as a DRAM cache. Additional hierarchical memory storage layers can be provided such as a downstream non-volatile main storage (e.g., a magnetic disc, etc.).
Each cell 110 in the array 108 includes a switching device 112 connected in series with a resistive memory element 114. In some embodiments, the switching devices 112 are characterized as n-channel MOSFETs (transistors), and the memory elements 114 are programmable resistive sense elements such as but not limited to resistive random access memory (RRAM) elements, spin-torque transfer random access memory (STRAM) elements or programmable metallization cells (PMCs).
A number of bit lines 116 denoted as BL0-BL3 interconnect a first end (“top side”) of each of the cells along each column. Source lines 118 denoted as SL0-SL3 interconnect an opposing, second end (“bottom side”) of each of the cells along each column. Word lines 120 denoted as WL0-WL2 interconnect the gate regions of the MOSFETs 112 along each row. It will be appreciated that other arrangements and interconnection schemes can be employed, so that the schematic representation of
The memory element 114 is characterized in
To program the memory cell 110 to a desired state, the WL driver 130 will assert the WL 120 and respective SL and BL drivers 140, 142 will direct current through the memory element 114 in the appropriate direction and at the appropriate voltage and current magnitudes. The programmed state of the element 114 can be subsequently read by asserting the WL 120, passing a smaller read bias current through the memory cell 110 such as from SL driver 140 to BL driver 142, and comparing the resulting voltage on the SL 116 to a reference voltage using a separate sense amplifier (not shown).
The stacked nature of the memory cell 110 in
One prior art solution uses filled via structures such as depicted in
While operable, it can be appreciated that the approach in
Another prior art solution that has been employed with stacked cells is the use of a common source plane (SP), such as depicted at 156 in
While operable, limitations with
Accordingly, various embodiments of the present invention are generally directed to a manufacturing process that efficiently and easily forms bottom-side control lines (e.g., source lines) for an array of vertically stacked memory cells. To illustrate such processing, reference is first made to
The acceptor wafer 160 includes a circuit layer 162 in which various control circuits, including CMOS circuitry, are formed during prior processing. This circuitry may include the various drivers shown in
The donor wafer 170 includes a number of layers including a base layer 172, which may be a bulk oxide. A doped silicon matrix 174 is formed in the base layer, and includes regions 176, 178 and 180 of respective NPN doping levels to ultimately form the respective drain, source and channel regions 122, 124 and 126 in
The respective wafers 160, 170 are mated as shown in
As will become apparent from the following discussion, the individual control (source lines) are eventually formed from this metal layer 186, so the metal layer can be characterized as a planar extent of conductive material with a substantially uniform thickness and overall length and width dimensions substantially corresponding to the overall length and width dimensions of the multi-wafer structure. In this way, the finished control lines will fully extend across the array in parallel, spaced apart fashion in the desired direction (e.g., in the row direction or the column direction, as required).
The base oxide layer 172 is removed and localized areas (dots) of photoresist (PR) 188 are applied to the top of the silicon matrix, as shown in
A hard mask is applied as shown in
An etching process is carried out in
An underlying dielectric material, such as an oxide 194, is deposited around the bases of the stacks or plurality of pillar structures up to the desired height. The plurality of pillar structures extends orthogonally from the semiconductor wafer or circuitry layer 162.
Each pillar structure will form a vertical pillar transistor 112 having a top surface 111 and a side surface 113 orthogonal to the top surface. The top surface 111 is generally planar and parallel with the major surface of the semiconductor wafer or circuitry layer 162. In many embodiments the cross-sectional or top view shape of the pillar structure includes sharp angles where the sides surfaces of the pillar structure intersect. These sharp angles can decrease the performance of the formed vertical pillar transistor 112. Thus rounding these sharp edges or corners is desired.
One illustrative method of rounding these sharp edges or corners of the side surfaces of the pillar structure is to implant a hardening species into the vertical pillar transistor top surface and not in the vertical pillar transistor side surface(s). The hardening implant step implants a particular ion (e.g., nitrogen) into the semiconductor material surface (e.g., silicon) so that when that implanted semiconductor material surface is oxidized, it forms an oxide that includes the implanted ion (e.g, silicon oxynitride). The remaining non-implanted surfaces will form a different oxide species upon the oxidation step. Then the two different oxide layers can be preferentially removed utilizing an appropriately oxide selective removal or etching step.
As illustrated in
The silicide layer 199 can be formed of any useful silicide material that can assist in reducing interface resistance. In many embodiments the silicide layer 199 is a cobalt disilicide material or a nickel disilicide material. The silicide layer 199 can be formed using any useful process that does not degrade the properties of the vertical pillar transistors 112. In particular, the silicide layer 199 can be formed with a chemical vapor deposition process at a temperature that is less than 400 degrees centigrade or from 200 to 375 degrees centigrade. Then the silicide layer 199 can be annealed to diffuse the silicide layer 199 into the surface of the vertical pillar transistors 112 and to react all unreacted ferromagnetic materials on the siliscon surface. In many embodiments, the anneal temperature is less than 525 degrees centigrade or less than 500 degrees centigrade or less than 450 degrees centigrade or less than 400 degrees centigrade. One illustrative silicide layer deposition process is described in U.S. Pat. No. 6,346,477 which is incorporated by reference herein.
The memory cell 214 can have a similar cross-sectional shape as the vertical pillar transistor 112. In many embodiments the memory cell 214 and the vertical pillar transistor 112 are in vertical registration and both have a circular cross-sectional shape. In other embodiments, the memory cell 214 and the vertical pillar transistor 112 are in vertical registration and the vertical pillar transistor 112 has a circular cross-sectional shape and the memory cell 214 has an elliptical cross-sectional shape.
Then a memory cell 214 is deposited onto the bottom electrode layer 213 utilizing known semiconductor techniques. The memory cell 214 is a non-volatile variable resistive memory cell such as a STRAM or RRAM memory cell, as described above. The memory cell 214 is offset (i.e., vertically offset) from the vertical pillar transistor 112 and the electrically conducting interconnect element 210. It is believed that a top surface of the electrically conducting interconnect element 210 is a concave surface and thus offsetting the memory cell 214 from the top surface of the electrically conducting interconnect element 210 can help reduce interface stress forces between the memory cell 214 from the top surface of the electrically conducting interconnect element 210.
The memory cell 214 can have a similar cross-sectional shape as the vertical pillar transistor 112. In many embodiments the vertical pillar transistor 112 has a circular cross-sectional shape and the memory cell 214 has a circular cross-sectional shape. In other embodiments, the vertical pillar transistor 112 has a circular cross-sectional shape and the memory cell 214 has an elliptical cross-sectional shape. The elliptical cross-sectional shape of the memory cell 214 can assist in reducing the surface area needed for the memory array.
A bit line BL is deposited onto the memory cells 214. The memory cell 214 is electrically connected to the corresponding electrically conducting interconnect element to form a vertical transistor memory array, as illustrated.
The deposited bit line material forms a layer of uniform thickness that covers the length and width dimensions of the overall array. Suitable masking and etching processing (not separately depicted) removes portions of this material to form the parallel, spaced apart bit lines 216. It is noted that in this embodiment the bit lines 216 and source lines 118 are parallel and orthogonal to the word lines 120, corresponding to the schematic depiction of
By forming the memory cell 214 subsequently to forming the vertical pillar transistor 112 provides several advantages. The memory cell 214 and the vertical pillar transistor 112 can each possess a different cross-sectional shape. For example, the memory cell 214 can have an elliptical shape and the vertical pillar transistor 112 can have a cylindrical shape. The elliptical shape can be orientated at an angle relative to the both the source line and bit line, such as an angle from 40 to 50 degrees, or 45 degrees. This configuration can allow for an increased density of memory cells in the array.
It will now be appreciated that the various embodiments as presented herein provide a number of advantages over the prior art. Spaced apart bottom side control lines can be easily and efficiently formed during manufacturing, eliminating the need for additional interconnections and conductive layers. Unlike top side interconnection techniques, the present process allows the source lines to run independently of the bit lines. Enhanced data densities can be achieved and multiple concurrent access operations can be carried out on different parts of the array, as desired.
Thus, embodiments of the VERTICAL TRANSISTOR STRAM ARRAY are disclosed. The implementations described above and other implementations are within the scope of the following claims. One skilled in the art will appreciate that the present disclosure can be practiced with embodiments other than those disclosed. The disclosed embodiments are presented for purposes of illustration and not limitation, and the present invention is limited only by the claims that follow.
