The technology of the disclosure relates generally to Internet Protocol (IP) packet processing in an electronic device.
Mobile communication devices have become increasingly common in current society. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.
Mobile communication devices are increasingly capable of providing a variety of communication services based on a variety of communication protocols. For example, mobile communication devices are often configured to provide wide-area wireless communication services (e.g., long-term evolution (LTE)), local-area wireless communication services (e.g., Wi-Fi), and local-area wired communication services (e.g., Ethernet).
Internet Protocol (IP) is a data communication protocol created by the Internet Engineering Task Force (IETF) for providing a common data transport mechanism across the variety of communication protocols (e.g., LTE communication protocol, Wi-Fi communication protocol, and Ethernet communication protocol). In this regard, application-specific data are first encoded into IP packets before being communicated based on communication protocols corresponding to the variety of communication services. IP packet processing is a heavy task and usually requires dedicated hardware and/or software support in the mobile communication devices. As such, it is desired to optimize efficiency of dedicated IP packet processing hardware, thus achieving increased data throughput, decreased processing latency, and reduced power consumption in the mobile communication devices.
Aspects disclosed in the detailed description include a virtualized Internet Protocol (IP) packet processing system. In this regard, in one aspect, a computing circuit for processing IP packets is shared among a plurality of virtual clients. The computing circuit includes a plurality of hardware functional blocks each configured to perform a predefined IP packet processing function (e.g., IP packet header ciphering/deciphering, IP packet header filtering, and IP packet payload processing). In another aspect, a virtual channel is created for each of the virtual clients and assigned with one or more of the hardware functional blocks. In this regard, IP packets associated with each of the virtual clients may be processed by respective assigned hardware functional blocks based on a specified processing sequence. By sharing the computing circuit among the virtual clients and assigning respective hardware functional blocks to each virtual client, it is possible to optimize processing efficiency of the computing circuit, thus improving throughput, latency, and power consumption of the virtualized IP packet processing system.
In this regard, in one aspect, a virtualized IP packet processing system is provided. The virtualized IP packet processing system includes a client interface. The client interface is configured to be coupled to a plurality of virtual clients. The virtualized IP packet processing system also includes hardware-based IP packet processing circuitry including a computing circuit. The computing circuit includes a plurality of hardware functional blocks each configured to perform a predefined IP packet processing function. The virtualized IP packet processing system also includes a resource controller. The resource controller is configured to receive an IP process request from a virtual client among the plurality of virtual clients via the client interface to perform a predefined IP packet process. The resource controller is also configured to define a virtual channel for the virtual client. The resource controller is also configured to assign one or more hardware functional blocks among the plurality of hardware functional blocks to the virtual channel based on the predefined IP packet process. The resource controller is also configured to configure the one or more assigned hardware functional blocks to perform the predefined IP packet process according to a specified processing sequence.
In another aspect, a virtualized IP packet processing system is provided. The virtualized IP packet processing system includes a means for coupling to a plurality of virtual clients. The virtualized IP packet processing system also includes a means for processing IP packets. The means for processing IP packets includes a computing circuit. The computing circuit includes a plurality of hardware functional blocks each configured to perform a predefined IP packet processing function. The virtualized IP packet processing system also includes a means for controlling resources. The means for controlling resources is configured to receive an IP process request from a virtual client among the plurality of virtual clients via a client interface to perform a predefined IP packet process. The means for controlling resources is also configured to define a virtual channel for the virtual client. The means for controlling resources is also configured to assign one or more hardware functional blocks among the plurality of hardware functional blocks to the virtual channel based on the predefined IP packet process. The means for controlling resources is also configured to configure the one or more assigned hardware functional blocks to perform the predefined IP packet process according to a specified processing sequence.
In another aspect, a method for processing IP packets is provided. The method includes receiving an IP process request from a virtual client among a plurality of virtual clients via a client interface to perform a predefined IP packet process. The method also includes defining a virtual channel for the virtual client. The method also includes assigning one or more hardware functional blocks among a plurality of hardware functional blocks to the virtual channel based on the predefined IP packet process. Each of the plurality of hardware functional blocks is configured to perform a predefined IP packet processing function. The method also includes configuring the one or more assigned hardware functional blocks to perform the predefined IP packet process according to a specified processing sequence.
With reference now to the drawing figures, several exemplary aspects of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
Aspects disclosed in the detailed description include a virtualized Internet Protocol (IP) packet processing system. In this regard, in one aspect, a computing circuit for processing IP packets is shared among a plurality of virtual clients. The computing circuit includes a plurality of hardware functional blocks each configured to perform a predefined IP packet processing function (e.g., IP packet header ciphering/deciphering, IP packet header filtering, and IP packet payload processing). In another aspect, a virtual channel is created for each of the virtual clients and assigned with one or more of the hardware functional blocks. In this regard, IP packets associated with each of the virtual clients may be processed by respective assigned hardware functional blocks based on a specified processing sequence. By sharing the computing circuit among the virtual clients and assigning respective hardware functional blocks to each virtual client, it is possible to optimize processing efficiency of the computing circuit, thus improving throughput, latency, and power consumption of the virtualized IP packet processing system.
Before discussing exemplary aspects of a virtualized IP packet processing system that includes specific aspects of the present disclosure, a brief overview of IP version 4 (IPv4) and IP version 6 (IPv6) packet formats is first provided in
In this regard,
IP packets (e.g., the IPv4 packet 100 and the IPv6 packet 110) can provide common data transport across a variety of communication protocols (e.g., long-term evolution (LTE) communication protocol, Wi-Fi communication protocol, and Ethernet communication protocol). In this regard,
With reference to
In a transmit direction 210, the application-specific clients 202(1)-202(N) provide application-specific data packets 212(1)-212(N) to the IP packet processing functions 204(1)-204(N), respectively. The IP packet processing functions 204(1)-204(N) are configured to encode the application-specific data packets 212(1)-212(N) into IP packets 214O(1)-214O(N), respectively. The IP packets 214O(1)-214O(N) are received by a plurality of communication circuits 216(1)-216(N), respectively. In a non-limiting example, the communication circuit 216(1) is a Wi-Fi circuit, the communication circuit 216(2) is an LTE circuit, and the communication circuit 216(N) is an Ethernet circuit. The communication circuits 216(1)-216(N) encode the IP packets 214O(1)-214O(N) into medium access control (MAC) packets 218O(1)-218O(N), respectively. In a non-limiting example, the MAC packet 218O(1) is encoded according to Wi-Fi communication protocol, the MAC packet 218O(2) is encoded according to LTE communication protocol, and the MAC packet 218O(N) is encoded according to Ethernet communication protocol.
In a receive direction 220, the communication circuits 216(1)-216(N) decode a plurality of MAC packets 218I(1)-218I(N) into a plurality of IP packets 214I(1)-214I(N), respectively. The IP packet processing functions 204(1)-204(N) in turn decode the IP packets 214I(1)-214I(N) into the application-specific data packets 212(1)-212(N), respectively.
With continuing reference to
In this regard,
With reference to
The virtualized IP packet processing system 302 may include a client interface 310 configured to be coupled to the virtual clients 304(1)-304(M). As such, the virtual clients 304(1)-304(M) are communicatively coupled to the virtualized IP packet processing system 302. In this regard, in a non-limiting example, the client interface 310 provides a means for coupling the virtualized IP packet processing system 302 to the virtual clients 304(1)-304(M).
The hardware-based IP packet processing circuitry 306 includes a computing circuit 312. The computing circuit 312 includes a plurality of hardware functional blocks 314(1)-314(K). Each of the hardware functional blocks 314(1)-314(K) is configured to perform a predefined IP packet processing function. In a non-limiting example, the hardware functional blocks 314(1)-314(K) are configured to perform a variety of predefined IP packet processing functions, including an IP packet header deciphering function, an IP packet header ciphering function, an IP packet header filtering function, an IP packet header checksum function, an IP packet header insertion function, an IP packet header removal function, an IP packet payload processing function, an IP packet aggregation function, an IP packet de-aggregation function, an IP packet routing function, and an IP packet network address translation (NAT) function. In another non-limiting example, the hardware functional blocks 314(1)-314(K) are also configured to support direct memory access (DMA) for non-IP based data. For example, each of the hardware functional blocks 314(1)-314(K) can be configured to support a general DMA copy (e.g., data movement for a non-IP channel) and/or non-IP control messages (e.g., sending in-band, non-IP control message within an IP data stream).
The hardware-based IP packet processing circuitry 306 includes storage media 316. The storage media 316 includes a plurality of storage elements 318(1)-318(L) (e.g., registers). The computing circuit 312 is communicatively coupled to the storage media 316 via a connection path 320. The connection path 320 may be a direct connection path or an indirect connection path between the computing circuit 312 and the storage media 316.
With continuing reference to
The resource controller 322 receives one or more IP process requests 326(1)-326(M) from the virtual clients 304(1)-304(M), respectively, via the client interface 310. Each of the IP process requests 326(1)-326(M) requests the virtualized IP packet processing system 302 to perform a predefined IP packet process. As is further discussed later, the predefined IP packet process includes an IP packet encoding process and an IP packet decoding process.
For the convenience of reference and discussion, the virtual client 304(1) is discussed and illustrated hereinafter as a non-limiting example. It shall be appreciated that the configuration and operation principles discussed hereinafter with reference to the virtual client 304(1) are applicable to the virtual clients 304(2)-304(M) as well.
With continuing reference to
The resource controller 322 determines the assigned hardware functional blocks 314 based on the predefined IP packet process. For example, when the predefined IP packet process is the IP packet encoding process, the assigned hardware functional blocks 314 may include hardware functional blocks configured to provide the IP packet header ciphering function, the IP packet header checksum function, the IP packet header insertion function, and the IP packet payload processing function. Alternatively, when the predefined IP packet process is the IP packet decoding process, the assigned hardware functional blocks 314 may include hardware functional blocks configured to provide the IP packet header removal function, the IP packet header deciphering function, and the IP packet header checksum function.
Subsequent to assigning the assigned hardware functional blocks 314 to the virtual channel 328, the resource controller 322 configures the assigned hardware functional blocks 314 to perform the predefined IP packet process according a specified processing sequence. In a non-limiting example, the specified processing sequence defines an execution order for the assigned hardware functional blocks 314. As previously mentioned, the virtual channel 328 may include physical channels each configured to communicate a respective virtual channel flow with the virtual client 304(1). As such, the specified processing sequence may be determined based on the respective virtual channel flow. In this regard, it may be possible to define a plurality of specified processing sequences for the physical channels included in the virtual channel 328. According to the above example of the IP packet encoding process, the specified processing sequence indicates that the IP packet encoding process is performed in the order of IP packet header ciphering, IP packet header checksum, IP packet header insertion, and IP packet payload processing. The resource controller 322 may determine the specified processing sequence based on IP packet processing information received in the IP process request 326(1).
In a first non-limiting example, the virtual client 304(1) is in a transmit mode, and the predefined IP packet process is the IP packet encoding process. The virtual client 304(1) can indicate selection of the IP packet encoding process in the IP process request 326(1). In this regard, the virtual client 304(1) provides one or more application-specific packets 330 to the virtualized IP packet processing system 302 for encoding into one or more IP packets 332. The application-specific packets 330 may be encoded in the transport control protocol (TCP) packet format, the user datagram protocol (UDP) packet format, or other packets formats as appropriate. The virtual client 304(1) may provide the application-specific packets 330 to the virtualized IP packet processing system 302 either via the client interface 310 or via alternative connection paths (e.g., system bus) (not shown) in the electronic device 300.
The assigned hardware functional blocks 314 receive the application-specific packets 330 from an input queue 334 in a first packet order. The input queue 334 is communicatively coupled to the hardware-based IP packet processing circuitry 306 and, thus is accessible to the assigned hardware functional blocks 314. The assigned hardware functional blocks 314 encode the application-specific packets 330 into the IP packets 332 according to the specified processing sequence. The assigned hardware functional blocks 314 add the IP packets 332 into an output queue 336 in a second packet order, which may be identical to or different from the first packet order. The IP packets 332 can be retrieved from the output queue 336 by a communication circuit (not shown) (e.g., LTE communication circuit, Wi-Fi communication circuit, Ethernet communication circuit, etc.) in the electronic device 300 for further encoding.
In a second non-limiting example, the virtual client 304(1) is in a receive mode, and the predefined IP packet process is the IP packet decoding process. The virtual client 304(1) can indicate selection of the IP packet decoding process in the IP process request 326(1). In this regard, the assigned hardware functional blocks 314 receive one or more IP packets 338 from the input queue 334 in the first packet order. The IP packets 338 may be received from the communication circuit (e.g., LTE communication circuit, Wi-Fi communication circuit, Ethernet communication circuit, etc.) in the electronic device 300. The assigned hardware functional blocks 314 decode the IP packets 338 into one or more application-specific packets 340 according to the specified processing sequence. The assigned hardware functional blocks 314 add the application-specific packets 340 to the output queue 336 in the second packet order, which may be identical to or different from the first packet order. The virtual client 304(1) may retrieve the application-specific packets 340 from the output queue 336 either via the client interface 310 or via alternative connection paths (e.g., system bus) in the electronic device 300.
With continuing reference to
The allocated storage elements 318 are accessible exclusively by the virtual channel 328, thus providing security protection to the virtual channel 328 and the virtual client 304(1). In a non-limiting example, it is possible to associate the virtual channel 328 with a respective security credential.
The resource controller 322 may configure the assigned hardware functional blocks 314 to perform the predefined IP packet process based on a process. In this regard,
With reference to
A virtualized IP packet processing system according to aspects disclosed herein may be provided in or integrated into any processor-based device, such as virtualized IP packet processing system 302 of
In this regard,
Other master and slave devices can be connected to the system bus 508. As illustrated in
The CPU(s) 502 may also be configured to access the display controller(s) 518 over the system bus 508 to control information sent to one or more displays 526. The display controller(s) 518 sends information to the display(s) 526 to be displayed via one or more video processors 528, which process the information to be displayed into a format suitable for the display(s) 526. The display(s) 526 can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.
Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both. The master devices and slave devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To illustrate clearly this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).
The aspects disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.
It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.